Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

Mali-G57.

This device tree is wrong (missing clocks and/or power domains). Needs
pd_ignore_unused clk_ignore_unused to work.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

TODO: Handle.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

Some Valhall GPUs require resets when encountering bus faults. Add the issue bit
for this and handle it.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

Logically, this function is free of side effects, so any pointers it
takes should be const. Needed to avoid a warning in the next patch.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

Add handling for the HW_ISSUE_TTRX_2968_TTRX_3162 quirk. Logic ported
from kbase. kbase lists this workaround as used on Mali-G57.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

Add the features, issues, and GPU IDs associated with Mali-G57, a
Valhall GPU found in the MediaTek MT8192.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

Alyssa Rosenzweig authored Jan 07, 2022 and Alyssa Rosenzweig committed Jan 09, 2022

Increase the MAX_PM_DOMAINS constant from 3 to 5, to support the extra
power domains required by the Mali-G57 on the MT8192.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

Required for Mali-G57 on the Mediatek MT8192, which uses even more
power domains than the MT8183 before it.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

Not sure this is the right approach, but this allows a driver to get
internal drm_file for kernel-generated rendering, for instance in errata
workarounds.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

Workaround from the downstream Mali drivers shipped in ChromeOS. The
code there is unsuitable for mainline but good as a reference for the
hardware behaviour:

https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/2781271/5



I don't see a good reason to add this platform-specific hack to the 3D
driver and need mt8192-specific DT extensions for Panfrost ... as
opposed to setting the appropriate bit in the clock driver already owning this
register so the GPU works as-is.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

Nícolas F. R. A. Prado authored Dec 17, 2021 and Alyssa Rosenzweig committed Jan 07, 2022

USB seemed to work fine without them but probably safer to include them
to avoid any misterious issue. This also removes the missing regulator
warnings in the log.

Nícolas F. R. A. Prado authored Dec 13, 2021 and Alyssa Rosenzweig committed Jan 07, 2022

MFG0 power domain requires an extra power supply on mt8192.

BUG=b:178776793
TEST=boot asurada and check display

[Similar patch is being upstreamed for 8183, we can wait for that
to land upstream, then upstream this as well]

Change-Id: I01f46bed82d927ea5871a15dc47e4d9093354f30
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/2699573


Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Commit-Queue: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>

Nícolas F. R. A. Prado authored Dec 13, 2021 and Alyssa Rosenzweig committed Jan 07, 2022

The HW should be the same as mt8183 anyway so use its compatible so aal
probes and the drm driver can finish probing.

Nícolas F. R. A. Prado authored Dec 09, 2021 and Alyssa Rosenzweig committed Jan 07, 2022

Just in case this is needed for the display bringup...

Nícolas F. R. A. Prado authored Dec 08, 2021 and Alyssa Rosenzweig committed Jan 07, 2022

Now that the 8192 clk configs were enabled, the display power domain no
longer fails to probe since the clk-mt8192-mm driver is there to enable
the mmsys clocks. Reenable the display power domain.

Nícolas F. R. A. Prado authored Dec 08, 2021 and Alyssa Rosenzweig committed Jan 07, 2022

These clocks are required for the platform bringup, in particular for
the display power domain.

Nícolas F. R. A. Prado authored Dec 07, 2021 and Alyssa Rosenzweig committed Jan 07, 2022

With this the kernel is able to load the rootfs from the USB stick and
reach the shell.

Chun-Jie Chen authored Aug 25, 2021 and Alyssa Rosenzweig committed Jan 07, 2022

update i2c 0 ~ 9 clocks to the real ones.

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>

Chun-Jie Chen authored Aug 25, 2021 and Alyssa Rosenzweig committed Jan 07, 2022

update nor flash clock to the real one.

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>

Chun-Jie Chen authored Aug 25, 2021 and Alyssa Rosenzweig committed Jan 07, 2022

update uart0 ~ 7 clocks to the real ones.

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>

Chun-Jie Chen authored Aug 25, 2021 and Alyssa Rosenzweig committed Jan 07, 2022

update uart0 and uart1 bus clock to the real one.

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>

Chun-Jie Chen authored Aug 25, 2021 and Alyssa Rosenzweig committed Jan 07, 2022

update systimer clock to the real one.

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>

Nícolas F. R. A. Prado authored Dec 06, 2021 and Alyssa Rosenzweig committed Jan 07, 2022

This reverts commit 4d050acf1a368b72ef673a393a6b84ce29bf922b.

Will apply all the clock fixes from mediatek.