1. 14 Aug, 2017 1 commit
  2. 23 Jun, 2017 1 commit
  3. 23 May, 2017 1 commit
  4. 22 May, 2017 2 commits
    • Paul Cercueil's avatar
      pinctrl: add a pinctrl driver for the Ingenic jz47xx SoCs · b5c23aa4
      Paul Cercueil authored
      This driver handles pin configuration and pin muxing for the
      JZ4740 and JZ4780 SoCs from Ingenic.
      Signed-off-by: Paul Cercueil's avatarPaul Cercueil <paul@crapouillou.net>
      Signed-off-by: Linus Walleij's avatarLinus Walleij <linus.walleij@linaro.org>
    • Shawn Guo's avatar
      pinctrl: add ZTE ZX pinctrl driver support · cbff0c4d
      Shawn Guo authored
      The pin controller on ZTE ZX platforms is kinda of hybrid.  It consists
      of a main controller and an auxiliary one.  For example, on ZX296718 SoC,
      the main controller is TOP_PMM and the auxiliary one is AON_IOCFG.  Both
      controllers work together to control pin multiplexing and configuration.
      For most of pins, the pinmux function is controlled by main controller
      only, and this type of pins are meant by term 'TOP pins'.  For other
      pins, the pinmux is controlled by both main and auxiliary controllers,
      as the available multiplexing functions for the pin spread in both
      controllers.  This type of pins are called 'AON pins'.  Though pinmux
      implementation is quite different, pinconf is same for both types of
      pins.  Both are controlled by auxiliary controller, i.e. AON_IOCFG on
      The patch adds the ZTE ZX core pinctrl driver to support this hybrid
      pin controller as well as ZX296718 SoC specific pin data.
      Signed-off-by: Shawn Guo's avatarShawn Guo <shawn.guo@linaro.org>
      Signed-off-by: Linus Walleij's avatarLinus Walleij <linus.walleij@linaro.org>
  5. 24 Apr, 2017 1 commit
  6. 07 Apr, 2017 1 commit
  7. 09 Jan, 2017 1 commit
    • Nishanth Menon's avatar
      pinctrl: Introduce TI IOdelay configuration driver · 003910eb
      Nishanth Menon authored
      SoC family such as DRA7 family of processors have, in addition
      to the regular muxing of pins (as done by pinctrl-single), a separate
      hardware module called IODelay which is also expected to be configured.
      The "IODelay" module has it's own register space that is independent
      of the control module and the padconf register area.
      With recent changes to the pinctrl framework, we can now support
      this hardware with a reasonably minimal driver by using #pinctrl-cells,
      It is advocated strongly in TI's official documentation considering
      the existing design of the DRA7 family of processors during mux or
      IODelay reconfiguration, there is a potential for a significant glitch
      which may cause functional impairment to certain hardware. It is
      hence recommended to do as little of muxing as absolutely necessary
      without I/O isolation (which can only be done in initial stages of
      NOTE: with the system wide I/O isolation scheme present in DRA7 SoC
      family, it is not reasonable to do stop all I/O operations for every
      such pad configuration scheme. So, we will let it glitch when used in
      this mode.
      Even with the above limitation, certain functionality such as MMC has
      mandatory need for IODelay reconfiguration requirements, depending on
      speed of transfer. In these cases, with careful examination of usecase
      involved, the expected glitch can be controlled such that it does not
      impact functionality.
      In short, IODelay module support as a padconf driver being introduced
      here is not expected to do SoC wide I/O Isolation and is meant for
      a limited subset of IODelay configuration requirements that need to
      be dynamic and whose glitchy behavior will not cause functionality
      failure for that interface.
      IMPORTANT NOTE: we take the approach of keeping LOCK_BITs cleared
      to 0x0 at all times, even when configuring Manual IO Timing Modes.
      This is done by eliminating the LOCK_BIT=1 setting from Step
      of the Manual IO timing Mode configuration procedure. This option
      leaves the CFG_* registers unprotected from unintended writes to the
      CTRL_CORE_PAD_* registers while Manual IO Timing Modes are configured.
      This approach is taken to allow for a generic driver to exist in kernel
      world that has to be used carefully in required usecases.
      Signed-off-by: default avatarNishanth Menon <nm@ti.com>
      Signed-off-by: default avatarLokesh Vutla <lokeshvutla@ti.com>
      [tony@atomide.com: updated to use generic pinctrl functions, added
       binding documentation, updated comments]
      Acked-by: Rob Herring's avatarRob Herring <robh@kernel.org>
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      Signed-off-by: Linus Walleij's avatarLinus Walleij <linus.walleij@linaro.org>
  8. 07 Dec, 2016 1 commit
  9. 24 Oct, 2016 1 commit
    • Neil Armstrong's avatar
      pinctrl: Add SX150X GPIO Extender Pinctrl Driver · 9e80f906
      Neil Armstrong authored
      Since the I2C sx150x GPIO expander driver uses platform_data to manage
      the pins configurations, rewrite the driver as a pinctrl driver using
      pinconf to get/set pin configurations from DT or debugfs.
      The pinctrl driver is functionnally equivalent as the gpio-only driver
      and can use DT for pinconf. The platform_data confirmation is dropped.
      This patchset removed the gpio-only driver and selects the Pinctrl driver
      config instead. This patchset also migrates the gpio dt-bindings to pinctrl
      and add the pinctrl optional properties.
      The driver was tested with a SX1509 device on a BeagleBone black with
      interrupt support and on an X86_64 machine over an I2C to USB converter.
      This is a fixed version that builds and runs on non-OF platforms and on
      arm based OF. The GPIO version is removed and the bindings are also moved
      to the pinctrl bindings.
      Changes since v2
       - rebased on v4.9-rc1
       - removed MODULE_DEVICE_TABLE as in upstream bb411e77
         ("gpio: sx150x: fix implicit assumption module.h is present")
      Changes since v1
       - Fix Kconfig descriptions on pinctrl and gpio
       - Fix Kconfig dependency
       - Remove oscio support for non-789 devices
       - correct typo in dt bindings
       - remove probe reset for non-789 devices
      Changes since RFC
       - Put #ifdef CONFIG_OF/CONFIG_OF_GPIO to remove OF code for non-of platforms
       - No more rely on OF_GPIO config
       - Moved and enhanced bindings to pinctrl bindings
       - Removed gpio-sx150x.c
       - Temporary select PINCTRL_SX150X when GPIO_SX150X
       - Temporary mark GPIO_SX150X as deprecated
      Signed-off-by: Neil Armstrong's avatarNeil Armstrong <narmstrong@baylibre.com>
      Tested-by: default avatarPeter Rosin <peda@axentia.se>
      Acked-by: Rob Herring's avatarRob Herring <robh@kernel.org>
      ested-by: default avatarAndrey Smirnov <andrew.smirnov@gmail.com>
      Signed-off-by: Linus Walleij's avatarLinus Walleij <linus.walleij@linaro.org>
  10. 07 Sep, 2016 1 commit
    • Andrew Jeffery's avatar
      pinctrl: Add core support for Aspeed SoCs · 4d3d0e42
      Andrew Jeffery authored
      The Aspeed SoCs typically provide more than 200 pins for GPIO and other
      functions. The signal enabled on a pin is determined on a priority
      basis, where a given pin can provide a number of different signal types.
      In addition to the priority levels, the Aspeed pin controllers describe
      the signal active on a pin by compound logical expressions involving
      multiple operators, registers and bits. Some difficulty arises as a
      pin's function bit masks for each priority level are frequently not the
      same (i.e. we cannot just flip a bit to change from a high to low
      priority signal), or even in the same register(s). Some configuration
      bits affect multiple pins, while in other cases the signals for a bus
      must each be enabled individually.
      Together, these features give rise to some complexity in the
      implementation. A more complete description of the complexities is
      provided in the associated header file.
      The patch doesn't implement pinctrl/pinmux/pinconf for any particular
      Aspeed SoC, rather it adds the framework for defining pinmux
      Signed-off-by: default avatarAndrew Jeffery <andrew@aj.id.au>
      Reviewed-by: Joel Stanley's avatarJoel Stanley <joel@jms.id.au>
      Signed-off-by: Linus Walleij's avatarLinus Walleij <linus.walleij@linaro.org>
  11. 22 Jun, 2016 1 commit
    • Axel Lin's avatar
      pinctrl: tegra: Fix build dependency · 19b5a917
      Axel Lin authored
      I got below build error:
      ERROR: "tegra_xusb_padctl_legacy_probe"
       [drivers/phy/tegra/phy-tegra-xusb.ko] undefined!
      with below build configuration:
      The problem is below line in drivers/pinctrl/Makefile
      obj-$(CONFIG_PINCTRL_TEGRA)     += tegra/
      So even CONFIG_PINCTRL_TEGRA_XUSB=y is set, kbuild still does not compile
      the code in drivers/pinctrl/tegra folder if !CONFIG_PINCTRL_TEGRA.
      phy-tegra-xusb.c does not use any symbol from pinctrl-tegra.c,
      so build pinctrl-tegra.c only when CONFIG_PINCTRL_TEGRA is set.
      Signed-off-by: default avatarAxel Lin <axel.lin@ingics.com>
      Acked-by: default avatarJon Hunter <jonathanh@nvidia.com>
      Signed-off-by: Linus Walleij's avatarLinus Walleij <linus.walleij@linaro.org>
  12. 13 Jun, 2016 1 commit
  13. 30 May, 2016 2 commits
  14. 13 Feb, 2016 1 commit
  15. 09 Feb, 2016 1 commit
  16. 05 Feb, 2016 2 commits
  17. 28 Jan, 2016 2 commits
  18. 27 Jan, 2016 1 commit
  19. 10 Dec, 2015 1 commit
  20. 01 Dec, 2015 3 commits
  21. 31 Oct, 2015 1 commit
  22. 21 Sep, 2015 1 commit
  23. 27 Jul, 2015 1 commit
    • Baruch Siach's avatar
      pinctrl: driver for Conexant Digicolor CX92755 pin mapping · 38b0e507
      Baruch Siach authored
      This adds pinctrl and gpio driver to the CX92755 SoC "General
      Purpose Pin Mapping" hardware block. The CX92755 is one SoC
      from the Conexant Digicolor series. Pin mapping hardware supports
      configuring pins as either GPIO, or up to 3 other "client select"
      functions. This driver adds support for pin muxing using the
      generic device tree binding, and a basic gpiolib driver for
      the GPIO functionality.
      This driver does not currently support GPIO interrupts, and
      pad configuration.
      * Address review comments for Linus Walleij:
        - Add a pointer to pinctrl_desc in struct dc_pinmap
        - Drop the now redundant pinctrl_pin_desc field
        - Adapt dc_get_group_{name,pins} to these changes, and
          add a comment explaining the 1-to-1 pin-groups relation
      * Staticise dc_pmxops
      * Protect the GP_CLIENTSEL clct parameter with parenthesis
      Signed-off-by: default avatarBaruch Siach <baruch@tkos.co.il>
      Signed-off-by: Linus Walleij's avatarLinus Walleij <linus.walleij@linaro.org>
  24. 16 Jul, 2015 2 commits
  25. 12 May, 2015 1 commit
  26. 06 May, 2015 1 commit
  27. 18 Mar, 2015 3 commits
  28. 09 Mar, 2015 1 commit
  29. 26 Jan, 2015 1 commit
  30. 11 Jan, 2015 1 commit
    • Soren Brinkmann's avatar
      pinctrl: Add driver for Zynq · add958ce
      Soren Brinkmann authored
      This adds a pin-control driver for Zynq.
      Changes since v2:
      - driver-specific DT properties are passed to the core in two arrays,
        one for the actual DT parsing one for the debugfs representation.
        Issue a compiler warning when the number of entries is not the same
        for both arrays.
      Changes since v1:
       - fix EMIO_SD1_CD pin name
       - add USB to pinmux options
      changes since RFCv2:
       - let Zynq select PINCTRL_ZYNQ. Boot hangs when pinctrl information is
         present in DT but no driver available.
       - add #defines to get rid of magical constants
       - add commas at end of initializers
       - separate changes in mach-zynq in separate patch
       - add driver specific io-standard DT property
       - refactored pinconf set function to not require arguments for
         argument-less properties
       - squash other patches in
         - support for IO-standard property
         - support for low-power mode property
         - migration to pinconf_generic_dt_node_to_map_all()
       - use newly created infrastructure to add pass driver-specific DT
         params to pinconf-generic
      changes since RFC:
       - use syscon/regmap to access registers in SLCR space
       - rebase to 3.18: rename enable -> set_mux
       - add kernel-doc
       - support pinconf
         - supported attributes
           - pin-bias: pull up, tristate, disable
           - slew-rate: 0 == slow, 1 == fast; generic pinconf does not display
      Signed-off-by: default avatarSoren Brinkmann <soren.brinkmann@xilinx.com>
      Tested-by: default avatarAndreas Färber <afaerber@suse.de>
      Signed-off-by: Linus Walleij's avatarLinus Walleij <linus.walleij@linaro.org>
  31. 10 Jan, 2015 1 commit