1. 11 May, 2009 3 commits
    • Yinghai Lu's avatar
      x86/acpi: move pin_programmed bit map to io_apic.c · bdfe8ac1
      Yinghai Lu authored
      
      
      Prepare to call setup_io_apic_routing() in pcibios_irq_enable()
      also remove not needed member apic_id.
      
      [ Impact: clean up, prepare for future change ]
      Signed-off-by: default avatarYinghai Lu <yinghai@kernel.org>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
      Cc: Len Brown <lenb@kernel.org>
      LKML-Reference: <4A01C3DD.3050104@kernel.org>
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      bdfe8ac1
    • Yinghai Lu's avatar
      x86/acpi: call mp_config_acpi_gsi() in mp_register_gsi() · a31f8205
      Yinghai Lu authored
      
      
      The patch to call mp_config_acpi_gsi() from the ACPI IRQ registration
      code never got mainline because there were open discussions about it.
      
      This call is needed to properly update the kernel's copy of the mptable,
      when the update_mptable boot parameter is needed.
      
      Now that the dust has settled with the APIC unification, and since there
      were no objections when the patch was re-submitted, try this again.
      
      [ Impact: fix the update_mptable boot parameter ]
      Signed-off-by: default avatarYinghai Lu <yinghai@kernel.org>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
      Cc: Len Brown <lenb@kernel.org>
      LKML-Reference: <4A01C387.7090103@kernel.org>
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      a31f8205
    • Yinghai Lu's avatar
      x86/acpi: remove irq-compression trick on 32-bit · b9e0353f
      Yinghai Lu authored
      
      
      We already have a per cpu vector on 32-bit via recent changes, and
      don't need this trick any more (which trick obfuscates the real GSI
      mappings and which only triggers on larger systems to begin with):
      
      On 3 ioapic system (24 per ioapic) before patch I got:
      
      ACPI: PCI Interrupt Link [ILSB] enabled at IRQ 71
      IOAPIC[2]: Set routing entry (10-23 -> 0xa9 -> IRQ 64 Mode:1 Active:1)
      pci 0000:80:01.1: PCI INT A -> Link[ILSB] -> GSI 71 (level, low) -> IRQ 64
      ACPI: PCI Interrupt Link [LE5B] enabled at IRQ 67
      IOAPIC[2]: Set routing entry (10-19 -> 0xb1 -> IRQ 65 Mode:1 Active:1)
      pci 0000:83:00.0: PCI INT B -> Link[LE5B] -> GSI 67 (level, low) -> IRQ 65
      ACPI: PCI Interrupt Link [LE5A] enabled at IRQ 66
      IOAPIC[2]: Set routing entry (10-18 -> 0xb9 -> IRQ 66 Mode:1 Active:1)
      pci 0000:83:00.1: PCI INT A -> Link[LE5A] -> GSI 66 (level, low) -> IRQ 66
      ACPI: PCI Interrupt Link [LE5D] enabled at IRQ 65
      IOAPIC[2]: Set routing entry (10-17 -> 0xc1 -> IRQ 67 Mode:1 Active:1)
      pci 0000:84:00.0: PCI INT B -> Link[LE5D] -> GSI 65 (level, low) -> IRQ 67
      ACPI: PCI Interrupt Link [LE5C] enabled at IRQ 64
      IOAPIC[2]: Set routing entry (10-16 -> 0xc9 -> IRQ 68 Mode:1 Active:1)
      pci 0000:84:00.1: PCI INT A -> Link[LE5C] -> GSI 64 (level, low) -> IRQ 68
      pci 0000:87:00.0: PCI INT B -> Link[LE5A] -> GSI 66 (level, low) -> IRQ 66
      pci 0000:87:00.1: PCI INT A -> Link[LE5D] -> GSI 65 (level, low) -> IRQ 67
      pci 0000:88:00.0: PCI INT B -> Link[LE5C] -> GSI 64 (level, low) -> IRQ 68
      pci 0000:88:00.1: PCI INT A -> Link[LE5B] -> GSI 67 (level, low) -> IRQ 65
      pci 0000:8b:00.0: PCI INT B -> Link[LE5A] -> GSI 66 (level, low) -> IRQ 66
      pci 0000:8b:00.1: PCI INT A -> Link[LE5D] -> GSI 65 (level, low) -> IRQ 67
      pci 0000:8c:00.0: PCI INT B -> Link[LE5C] -> GSI 64 (level, low) -> IRQ 68
      pci 0000:8c:00.1: PCI INT A -> Link[LE5B] -> GSI 67 (level, low) -> IRQ 65
      
      after the patch we get:
      
      ACPI: PCI Interrupt Link [ILSB] enabled at IRQ 71
      IOAPIC[2]: Set routing entry (10-23 -> 0xa9 -> IRQ 71 Mode:1 Active:1)
      pci 0000:80:01.1: PCI INT A -> Link[ILSB] -> GSI 71 (level, low) -> IRQ 71
      ACPI: PCI Interrupt Link [LE5B] enabled at IRQ 67
      IOAPIC[2]: Set routing entry (10-19 -> 0xb1 -> IRQ 67 Mode:1 Active:1)
      pci 0000:83:00.0: PCI INT B -> Link[LE5B] -> GSI 67 (level, low) -> IRQ 67
      ACPI: PCI Interrupt Link [LE5A] enabled at IRQ 66
      IOAPIC[2]: Set routing entry (10-18 -> 0xb9 -> IRQ 66 Mode:1 Active:1)
      pci 0000:83:00.1: PCI INT A -> Link[LE5A] -> GSI 66 (level, low) -> IRQ 66
      ACPI: PCI Interrupt Link [LE5D] enabled at IRQ 65
      IOAPIC[2]: Set routing entry (10-17 -> 0xc1 -> IRQ 65 Mode:1 Active:1)
      pci 0000:84:00.0: PCI INT B -> Link[LE5D] -> GSI 65 (level, low) -> IRQ 65
      ACPI: PCI Interrupt Link [LE5C] enabled at IRQ 64
      IOAPIC[2]: Set routing entry (10-16 -> 0xc9 -> IRQ 64 Mode:1 Active:1)
      pci 0000:84:00.1: PCI INT A -> Link[LE5C] -> GSI 64 (level, low) -> IRQ 64
      pci 0000:87:00.0: PCI INT B -> Link[LE5A] -> GSI 66 (level, low) -> IRQ 66
      pci 0000:87:00.1: PCI INT A -> Link[LE5D] -> GSI 65 (level, low) -> IRQ 65
      pci 0000:88:00.0: PCI INT B -> Link[LE5C] -> GSI 64 (level, low) -> IRQ 64
      pci 0000:88:00.1: PCI INT A -> Link[LE5B] -> GSI 67 (level, low) -> IRQ 67
      pci 0000:8b:00.0: PCI INT B -> Link[LE5A] -> GSI 66 (level, low) -> IRQ 66
      pci 0000:8b:00.1: PCI INT A -> Link[LE5D] -> GSI 65 (level, low) -> IRQ 65
      pci 0000:8c:00.0: PCI INT B -> Link[LE5C] -> GSI 64 (level, low) -> IRQ 64
      pci 0000:8c:00.1: PCI INT A -> Link[LE5B] -> GSI 67 (level, low) -> IRQ 67
      
      As it can be seen that GSIs now get mapped lineary.
      
      [ Impact: simplify irq number mapping on bigger 32-bit systems ]
      Signed-off-by: default avatarYinghai Lu <yinghai@kernel.org>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
      Cc: Len Brown <lenb@kernel.org>
      LKML-Reference: <4A01C35C.7060207@kernel.org>
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      b9e0353f
  2. 28 Apr, 2009 1 commit
    • Yinghai Lu's avatar
      irq: change ACPI GSI APIs to also take a device argument · a2f809b0
      Yinghai Lu authored
      
      
      We want to use dev_to_node() later on, to be aware of the 'home node'
      of the GSI in question.
      
      [ Impact: cleanup, prepare the IRQ code to be more NUMA aware ]
      Signed-off-by: default avatarYinghai Lu <yinghai@kernel.org>
      Acked-by: default avatarLen Brown <lenb@kernel.org>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      Cc: Suresh Siddha <suresh.b.siddha@intel.com>
      Cc: "Eric W. Biederman" <ebiederm@xmission.com>
      Cc: Rusty Russell <rusty@rustcorp.com.au>
      Cc: Len Brown <lenb@kernel.org>
      Cc: Bjorn Helgaas <bjorn.helgaas@hp.com>
      Cc: Tony Luck <tony.luck@intel.com>
      Cc: linux-acpi@vger.kernel.org
      Cc: linux-ia64@vger.kernel.org
      LKML-Reference: <49F65560.20904@kernel.org>
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      a2f809b0
  3. 04 Apr, 2009 1 commit
    • Suresh Siddha's avatar
      x86, ACPI: add support for x2apic ACPI extensions · 7237d3de
      Suresh Siddha authored
      
      
      All logical processors with APIC ID values of 255 and greater will have their
      APIC reported through Processor X2APIC structure (type-9 entry type) and all
      logical processors with APIC ID less than 255 will have their APIC reported
      through legacy Processor Local APIC (type-0 entry type) only. This is the
      same case even for NMI structure reporting.
          
      The Processor X2APIC Affinity structure provides the association between the
      X2APIC ID of a logical processor and the proximity domain to which the logical
      processor belongs.
          
      For OSPM, Procssor IDs outside the 0-254 range are to be declared as Device()
      objects in the ACPI namespace.
      Signed-off-by: default avatarSuresh Siddha <suresh.b.siddha@intel.com>
      Signed-off-by: default avatarLen Brown <len.brown@intel.com>
      7237d3de
  4. 03 Apr, 2009 1 commit
  5. 17 Feb, 2009 2 commits
  6. 09 Feb, 2009 8 commits
  7. 30 Jan, 2009 1 commit
  8. 29 Jan, 2009 2 commits
  9. 28 Jan, 2009 3 commits
  10. 14 Jan, 2009 2 commits
  11. 09 Jan, 2009 1 commit
  12. 03 Jan, 2009 2 commits
  13. 23 Dec, 2008 1 commit
  14. 08 Dec, 2008 1 commit
  15. 12 Nov, 2008 1 commit
    • Bjorn Helgaas's avatar
      ACPI: pci_link: remove acpi_irq_balance_set() interface · 32836259
      Bjorn Helgaas authored
      
      
      This removes the acpi_irq_balance_set() interface from the PCI
      interrupt link driver.
      
      x86 used acpi_irq_balance_set() to tell the PCI interrupt link
      driver to configure links to minimize IRQ sharing.  But the link
      driver can easily figure out whether to turn on IRQ balancing
      based on the IRQ model (PIC/IOAPIC/etc), so we can get rid of
      that external interface.
      
      It's better for the driver to figure this out at init-time.  If
      we set it externally via the x86 code, the interface reduces
      modularity, and we depend on the fact that acpi_process_madt()
      happens before we process the kernel command line.
      Signed-off-by: default avatarBjorn Helgaas <bjorn.helgaas@hp.com>
      Signed-off-by: default avatarLen Brown <len.brown@intel.com>
      32836259
  16. 22 Oct, 2008 2 commits
  17. 16 Oct, 2008 3 commits
  18. 15 Oct, 2008 1 commit
  19. 07 Oct, 2008 1 commit
    • Ingo Molnar's avatar
      x86: SB450: deprioritize DMI quirks · 8d89adf4
      Ingo Molnar authored
      This PCI ID based quick should be a full solution for the IRQ0 override
      related slowdown problem on SB450 based systems:
      
        33fb0e4e
      
      : x86: SB450: skip IRQ0 override if it is not routed to INT2 of IOAPIC
      
      Emit a warning in those cases where the DMI quirk triggers but
      the PCI ID based quirk didnt.
      
      If this warning does not trigger then we can phase out the DMI quirks.
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      8d89adf4
  20. 06 Oct, 2008 1 commit
  21. 27 Aug, 2008 1 commit
  22. 21 Aug, 2008 1 commit
    • Yinghai Lu's avatar
      x86: fix apic version warning · 11494547
      Yinghai Lu authored
      after following patch,
      
      commit 1b313f4a
      
      
      Author: Cyrill Gorcunov <gorcunov@gmail.com>
      Date:   Mon Aug 18 20:45:57 2008 +0400
      
          x86: apic - generic_processor_info
      
          - use physid_set instead of phys_cpu and physids_or
          - set phys_cpu_present_map bit AFTER check for allowed
            number of processors
          - add checking for APIC valid version in 64bit mode
            (mostly not needed but added for merging purpose)
          - add apic_version definition for 64bit mode which
            is used now
      
      we are getting warning for acpi path on 64 bit system.
      
      make the 64-bit side fill in apic_version[] as well.
      
      [ mingo@elte.hu: build fix ]
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      11494547