1. 16 Sep, 2015 1 commit
    • Thomas Gleixner's avatar
      genirq: Remove irq argument from irq flow handlers · bd0b9ac4
      Thomas Gleixner authored
      Most interrupt flow handlers do not use the irq argument. Those few
      which use it can retrieve the irq number from the irq descriptor.
      
      Remove the argument.
      
      Search and replace was done with coccinelle and some extra helper
      scripts around it. Thanks to Julia for her help!
      Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
      Cc: Julia Lawall <Julia.Lawall@lip6.fr>
      Cc: Jiang Liu <jiang.liu@linux.intel.com>
      bd0b9ac4
  2. 28 Jul, 2015 1 commit
    • Rob Herring's avatar
      ARM: kill off set_irq_flags usage · e8d36d5d
      Rob Herring authored
      set_irq_flags is ARM specific with custom flags which have genirq
      equivalents. Convert drivers to use the genirq interfaces directly, so we
      can kill off set_irq_flags. The translation of flags is as follows:
      
      IRQF_VALID -> !IRQ_NOREQUEST
      IRQF_PROBE -> !IRQ_NOPROBE
      IRQF_NOAUTOEN -> IRQ_NOAUTOEN
      
      For IRQs managed by an irqdomain, the irqdomain core code handles clearing
      and setting IRQ_NOREQUEST already, so there is no need to do this in
      .map() functions and we can simply remove the set_irq_flags calls. Some
      users also modify IRQ_NOPROBE and this has been maintained although it
      is not clear that is really needed. There appears to be a great deal of
      blind copy and paste of this code.
      Signed-off-by: Rob Herring's avatarRob Herring <robh@kernel.org>
      Cc: Russell King <linux@arm.linux.org.uk>
      Cc: Sekhar Nori <nsekhar@ti.com>
      Cc: Kevin Hilman <khilman@deeprootsystems.com>
      Cc: Jason Cooper <jason@lakedaemon.net>
      Cc: Andrew Lunn <andrew@lunn.ch>
      Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
      Cc: Gregory Clement <gregory.clement@free-electrons.com>
      Acked-by: default avatarHans Ulli Kroll <ulli.kroll@googlemail.com>
      Acked-by: default avatarShawn Guo <shawnguo@kernel.org>
      Cc: Sascha Hauer <kernel@pengutronix.de>
      Cc: Imre Kaloz <kaloz@openwrt.org>
      Acked-by: default avatarKrzysztof Halasa <khalasa@piap.pl>
      Cc: Greg Ungerer <gerg@uclinux.org>
      Cc: Roland Stigge <stigge@antcom.de>
      Cc: Tony Lindgren <tony@atomide.com>
      Cc: Daniel Mack <daniel@zonque.org>
      Cc: Haojian Zhuang <haojian.zhuang@gmail.com>
      Cc: Robert Jarzmik <robert.jarzmik@free.fr>
      Cc: Simtec Linux Team <linux@simtec.co.uk>
      Cc: Kukjin Kim <kgene@kernel.org>
      Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com>
      Acked-by: default avatarWan ZongShun <mcuos.com@gmail.com>
      Cc: linux-arm-kernel@lists.infradead.org
      Cc: linux-omap@vger.kernel.org
      Cc: linux-samsung-soc@vger.kernel.org
      Tested-by: default avatarKevin Hilman <khilman@linaro.org>
      Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
      e8d36d5d
  3. 13 Jul, 2015 1 commit
    • Thomas Gleixner's avatar
      ARM/dove: Prepare pmu_irq_handler for irq argument removal · 1c2d4afa
      Thomas Gleixner authored
      The irq argument of most interrupt flow handlers is unused or merily
      used instead of a local variable. The handlers which need the irq
      argument can retrieve the irq number from the irq descriptor.
      
      Search and update was done with coccinelle and the invaluable help of
      Julia Lawall.
      Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
      Cc: Julia Lawall <Julia.Lawall@lip6.fr>
      Cc: Jiang Liu <jiang.liu@linux.intel.com>
      Cc: Russell King <linux+kernel@arm.linux.org.uk>
      Cc: linux-arm-kernel@lists.infradead.org
      1c2d4afa
  4. 24 Jun, 2015 1 commit
  5. 26 Apr, 2014 1 commit
  6. 21 Nov, 2012 1 commit
    • Russell King - ARM Linux's avatar
      Dove: Attempt to fix PMU/RTC interrupts · 5d3df935
      Russell King - ARM Linux authored
      Fix the acknowledgement of PMU interrupts on Dove: some Dove hardware
      has not been sensibly designed so that interrupts can be handled in a
      race free manner.  The PMU is one such instance.
      
      The pending (aka 'cause') register is a bunch of RW bits, meaning that
      these bits can be both cleared and set by software (confirmed on the
      Armada-510 on the cubox.)
      
      Hardware sets the appropriate bit when an interrupt is asserted, and
      software is required to clear the bits which are to be processed.  If
      we write ~(1 << bit), then we end up asserting every other interrupt
      except the one we're processing.  So, we need to do a read-modify-write
      cycle to clear the asserted bit.
      
      However, any interrupts which occur in the middle of this cycle will
      also be written back as zero, which will also clear the new interrupts.
      
      The upshot of this is: there is _no_ way to safely clear down interrupts
      in this register (and other similarly behaving interrupt pending
      registers on this device.)  The patch below at least stops us creating
      new interrupts.
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      Cc: stable@vger.kernel.org
      Signed-off-by: default avatarJason Cooper <jason@lakedaemon.net>
      5d3df935
  7. 21 Sep, 2012 1 commit
  8. 14 Sep, 2012 1 commit
  9. 27 Jul, 2012 1 commit
  10. 29 Mar, 2011 3 commits
  11. 03 Mar, 2011 1 commit
  12. 13 Jan, 2011 1 commit
  13. 27 Nov, 2009 1 commit