- 24 Sep, 2018 3 commits
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Laurent Pinchart authored
DSYSR is a DU channel register that also contains group fields. It is thus written to by both the group and CRTC code, using read-update-write sequences. As the register isn't initialized explicitly at startup time, this can lead to invalid or otherwise unexpected values being written to some of the fields if they have been modified by the firmware or just not reset properly. To fix this we can write a fully known value to the DSYSR register when turning a channel's functional clock on. However, the mix of group and channel fields complicate this. A simpler solution is to cache the register and initialize the cached value to the desired hardware defaults. Signed-off-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Tested-by:
Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by:
Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
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Laurent Pinchart authored
On selected SoCs, the DU can use the clock output by the LVDS encoder PLL as its input dot clock. This feature is optional, but on the D3 and E3 SoC it is often the only way to obtain a precise dot clock frequency, as the other available clocks (CPG-generated clock and external clock) usually have fixed rates. Add a DU model information field to describe which DU channels can use the LVDS PLL output clock as their input clock, and configure clock routing accordingly. This feature is available on H2, M2-W, M2-N, D3 and E3 SoCs, with D3 and E3 being the primary targets. It is left disabled in this commit, and will be enabled per-SoC after careful testing. At the hardware level, clock routing is configured at runtime in two steps, first selecting an internal dot clock between the LVDS PLL clock and the external DOTCLKIN clock, and then selecting between the internal dot clock and the CPG-generated clock. The first part requires stopping the whole DU group in order for the change to take effect, thus causing flickering on the screen. For this reason we currently hardcode the clock source to the LVDS PLL clock if available, and allow flicker-free selection of the external DOTCLKIN clock or CPG-generated clock otherwise. A more dynamic clock selection process can be implemented later if the need arises. Signed-off-by:
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Laurent Pinchart authored
The rcar_du_crtc_get() function is always immediately followed by a call to rcar_du_crtc_setup(). Call the later from the former to simplify the code, and add a comment to explain how the get and put calls are balanced. Signed-off-by:
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- 15 Sep, 2018 4 commits
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Jacopo Mondi authored
The ESCR and OTAR registers exist in each DU channel, but at different offsets for odd and even channels. This led to usage of the group register access API to write them, with offsets macros named ESCR/OTAR and ESCR2/OTAR2 for the first and second ESCR/OTAR register in the group respectively. The names are confusing as it suggests that the ESCR/OTAR registers for DU0 and DU2 are taken into account, especially with writes performed to the group register access API. Rename the offsets to ESCR/OTAR02 and ESCR/OTAR13, and use the CRTC register access API to clarify the code. The offsets values are updated accordingly. Cosmetic patch, no functional changes intended. Signed-off-by:
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Jacopo Mondi authored
Document and re-name the 'dpll_ch' field to a more precise 'dpll_mask' for consistency with the 'channels_mask' field defined in 'struct rcar_du_device_info'. Signed-off-by:
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Jacopo Mondi authored
DU channels not equipped with a DPLL use an SoC internal (provided by the CPG) or external clock source combined with a DU internal divider to generate the desired output dot clock frequency. The current clock selection procedure does not fully exploit the ability of external clock sources to generate the exact dot clock frequency by themselves, but relies instead on tuning the internal DU clock divider only, resulting in a less precise clock generation process. When possible, and desirable, ask the external clock source for the exact output dot clock frequency, and select the clock source that produces the frequency closest to the desired output dot clock. This patch specifically targets platforms (like Salvator-X[S] and ULCBs) where the DU's input dotclock.in is generated by the versaclock VC5 clock source, which is capable of generating the exact rate the DU needs as pixel clock output. This patch fixes higher resolution modes which requires an high pixel clock output currently not working on non-HDMI DU channel (such as 1920x1080@60Hz on the VGA output). Fixes: 1b30dbde ("drm: rcar-du: Add support for external pixel clock") Signed-off-by:
Jacopo Mondi <jacopo@jmondi.org> [Factor out code to a helper function] Signed-off-by:
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Laurent Pinchart authored
The DU channels that have a display PLL (DPLL) can only use external clock sources, and don't have an internal clock divider (with the exception of H3 ES1.x where the post-divider is present and needs to be used as a workaround for a DPLL silicon issue). Rework the clock configuration to take this into account, avoiding selection of non-existing clock sources or usage of a missing post-divider. Signed-off-by:
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- 14 Sep, 2018 3 commits
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Kieran Bingham authored
Upcoming implementations of the R-Car DU have removed support for interlaced display pipelines. Provide a means to determine this based on the feature flags of the hardware configuration structs. Signed-off-by:
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Kieran Bingham authored
Use the newly exposed VSP1 interface to enable interlaced frame support through the VSP1 LIF pipelines. The DSMR register is updated to set the ODEV flag on interlaced pipelines, thus defining an interlaced stream as having the ODD field located in the second half (BOTTOM) of the frame buffer. Signed-off-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
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Kuninori Morimoto authored
Kconfig doesn't have license line, thus, it is GPL-2.0 as default. rcar_du_regs.h, rcar_lvds_regs.h are GPL-2.0, and all other files are GPL-2.0+ as original license. Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by:
Simon Horman <horms+renesas@verge.net.au> Signed-off-by:
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- 22 Aug, 2018 1 commit
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Mahesh Kumar authored
This patch make changes to allocate crc-entries buffer before enabling CRC generation. It moves all the failure check early in the function before setting the source or memory allocation. Now set_crc_source takes only two variable inputs, values_cnt we already gets as part of verify_crc_source. Changes since V1: - refactor code to use single spin lock Changes since V2: - rebase Changes since V3: - rebase on top of VKMS driver Signed-off-by:
Mahesh Kumar <mahesh1.kumar@intel.com> Cc: dri-devel@lists.freedesktop.org Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: Haneen Mohammed <hamohammed.sa@gmail.com> Reviewed-by:
Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Acked-by: Leo Li <sunpeng.li@amd.com> (V2) Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> (V3) Signed-off-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180821083858.26275-3-mahesh1.kumar@intel.com
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- 13 Aug, 2018 2 commits
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Mahesh Kumar authored
This patch implements get_crc_sources callback, which returns list of all the crc sources supported by driver in current platform. Changes Since V1: - move sources list per-crtc - init sources-list only for gen3 Changes Since V2: - Adopt to driver style - Address other review comments from Laurent Pinchart Changes Since V3/4/5: (Laurent Pinchart review) - s/rcar_du_crtc_crc_sources_list_init/rcar_du_crtc_crc_init - s/rcar_du_crtc_crc_sources_list_uninit/rcar_du_crtc_crc_cleanup - other cleanup Signed-off-by:
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Mahesh Kumar authored
This patch implements "verify_crc_source" callback function for rcar drm driver. Changes Since V1: - avoid duplication of code Changes Since V2: - further optimize the code Changes Since V3: - Adopt to driver style - Address review comments from Laurent Pinchart Signed-off-by:
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- 17 May, 2018 1 commit
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Laurent Pinchart authored
Implement CRC computation configuration and reporting through the DRM debugfs-based CRC API. The CRC source can be configured to any input plane or the pipeline output. Signed-off-by:
Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
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- 05 May, 2018 1 commit
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Kieran Bingham authored
The DU CRTC driver does not support distinguishing between a hardware index, and a software (CRTC) index in the event that a DU channel might not be populated by the hardware. Support this by adapting the rcar_du_device_info structure to store a bitmask of available channels rather than a count of CRTCs. The count can then be obtained by determining the hamming weight of the bitmask. This allows the rcar_du_crtc_create() function to distinguish between both index types, and non-populated DU channels will be skipped without leaving a gap in the software CRTC indexes. Signed-off-by:
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- 14 Feb, 2018 2 commits
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Kuninori Morimoto authored
In general, PLL has VCO (= Voltage controlled oscillator), one of the very important electronic feature called as "jitter" is related to this VCO. In academic generalism, VCO should be maximum to be more small jitter. In high frequency clock, jitter will be large impact. Thus, selecting Hi VCO is general theory. fin fvco fout fclkout in --> [1/M] --> |PD| -> [LPF] -> [VCO] -> [1/P] -+-> [1/FDPLL] -> out +-> | | | | | +-----------------[1/N]<-------------+ fclkout = fvco / P / FDPLL -- (1) In PD, it will loop until fin/M = fvco/P/N fvco = fin * P * N / M -- (2) (1) + (2) indicates fclkout = fin * N / M / FDPLL In this device, N = (n + 1), M = (m + 1), P = 2, FDPLL = (fdpll + 1). fclkout = fin * (n + 1) / (m + 1) / (fdpll + 1) This is the datasheet formula. One note here is that it should be 2kHz < fvco < 4096MHz To be smaller jitter, fvco should be maximum, in other words, N as large as possible, M as small as possible driver should select. Here, basically M=1. This patch do it. Reported-by:HIROSHI INOSE <hiroshi.inose.rb@renesas.com> Signed-off-by:
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Kuninori Morimoto authored
It is difficult to understand its scale if number has many 0s. This patch uses "* 1000" to avoid it in rcar_du_dpll_divider(). Signed-off-by:
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- 04 Dec, 2017 2 commits
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Laurent Pinchart authored
Unlike the KMS API, the hardware doesn't support planes exceeding the screen boundaries or planes being located fully off-screen. We need to clip plane coordinates to support the use case. Fortunately the DRM core offers a drm_atomic_helper_check_plane_state() helper that validates the scaling factor and clips the plane coordinates. Use it to implement the plane atomic check and use the clipped source and destination rectangles from the plane state instead of the unclipped source and CRTC coordinates to configure the device. Signed-off-by:
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Kieran Bingham authored
An early implementation of suspend-resume helpers are available in the CRTC module, however they are unused and no longer needed. With suspend and resume handled by the core DRM atomic helpers, we can remove the unused functions. Signed-off-by:
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- 03 Aug, 2017 7 commits
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Kieran Bingham authored
The driver recently switched from handling page flip completion in the DU vertical blanking handler to the VSP frame end handler to fix a race condition. This unfortunately resulted in incorrect timestamps in the vertical blanking events sent to userspace as vertical blanking is now handled after sending the event. To fix this we must reverse the order of the two operations. The easiest way is to handle vertical blanking in the VSP frame end handler before sending the event. The VSP frame end interrupt occurs approximately 50µs earlier than the DU frame end interrupt, but this should not cause any undue harm. As we need to handle vertical blanking even when page flip completion is delayed, the VSP driver now needs to call the frame end completion callback unconditionally, with a new argument to report whether page flip has completed. With this new scheme the DU vertical blanking interrupt isn't needed anymore, so we can stop enabling it. Fixes: d503a43a ("drm: rcar-du: Register a completion callback with VSP1") Signed-off-by:
Mauro Carvalho Chehab <mchehab@s-opensource.com>
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Laurent Pinchart authored
When stopping the CRTC the driver must disable all planes and wait for the change to take effect at the next vblank. Merely calling drm_crtc_wait_one_vblank() is not enough, as the function doesn't include any mechanism to handle the race with vblank interrupts. Replace the drm_crtc_wait_one_vblank() call with a manual mechanism that handles the vblank interrupt race. Signed-off-by:
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Laurent Pinchart authored
When implementing support for interlaced modes, the driver switched from reporting vblank events on the vertical blanking (VBK) interrupt to the frame end interrupt (FRM). This incorrectly divided the reported refresh rate by two. Fix it by moving back to the VBK interrupt. Fixes: 906eff7f ("drm: rcar-du: Implement support for interlaced modes") Signed-off-by:
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Laurent Pinchart authored
Commit 52055baf ("drm: rcar-du: Move plane commit code from CRTC start to CRTC resume") changed the order of the plane commit and CRTC enable operations to accommodate the runtime PM requirements. However, this introduced corruption in the first displayed frame, as the CRTC is now enabled without any plane configured. On Gen2 hardware the first frame will be black and likely unnoticed, but on Gen3 hardware we end up starting the display before the VSP compositor, which is more noticeable. To fix this, revert the order of the commit operations back, and handle runtime PM requirements in the CRTC .atomic_begin() and .atomic_enable() helper operation handlers. Signed-off-by:
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Laurent Pinchart authored
The H3 ES1.x exhibits dot clock duty cycle stability issues. We can work around them by configuring the DPLL to twice the desired frequency, coupled with a /2 post-divider. This isn't needed on other SoCs and breaks HDMI output on M3-W for a currently unknown reason, so restrict the workaround to H3 ES1.x. From an implementation point of view, move work around handling outside of the rcar_du_dpll_divider() function by requesting a x2 DPLL output frequency explicitly. The existing post-divider calculation mechanism will then take care of dividing the clock by two automatically. While at it, print a more useful debugging message to ease debugging clock rate issues. Signed-off-by:
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Laurent Pinchart authored
On R-Car H3 ES2.0, DU channels 0 and 3 are served by two separate pipelines from the same VSP. Support this in the DU driver. Signed-off-by:
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Laurent Pinchart authored
To avoid mixing comment styles when new comments complying with the kernel coding style are introduced, fix all multiline comments in one go. Signed-off-by:
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- 30 Jun, 2017 2 commits
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Laurent Pinchart authored
The CRTC .disable() helper operation is deprecated for atomic drivers, the new .atomic_disable() helper operation being preferred. Convert all atomic drivers to .atomic_disable() to avoid cargo-cult use of .disable() in new drivers. Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/20170630093646.7928-3-laurent.pinchart+renesas@ideasonboard.com
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Laurent Pinchart authored
The old state is useful for drivers that need to perform operations at enable time that depend on the transition between the old and new states. While at it, rename the operation to .atomic_enable() to be consistent with .atomic_disable(), as the .enable() operation is used by atomic helpers only. Signed-off-by:
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- 22 May, 2017 2 commits
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Kieran Bingham authored
Currently we process page flip events on every display interrupt, however this does not take into consideration the processing time needed by the VSP1 utilised in the pipeline. Register a callback with the VSP driver to obtain completion events, and track them so that we only perform page flips when the full display pipeline has completed for the frame. Signed-off-by:
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Laurent Pinchart authored
The page flip event is armed in the atomic begin handler, creating a race condition with the frame end interrupt that could send the event before the atomic operation actually completes. To avoid that, arm the event in the atomic flush handler after queuing the page flip. This change doesn't fully close the race window, as the frame end interrupt could be generated before the page flip is committed to hardware but only handled after the event is armed. However, the race window is now much smaller. Signed-off-by:
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- 04 Apr, 2017 3 commits
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Koji Matsuoka authored
The implementation hardcodes a workaround for the H3 ES1.x SoC regardless of the SoC revision, as the workaround can be safely applied on all devices in the Gen3 family without any side effect. Signed-off-by:
Koji Matsuoka <koji.matsuoka.xm@renesas.com> Signed-off-by:
Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by:
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Laurent Pinchart authored
The atomic commit helper requires drivers to clear the event pointer stored in the CRTC state when the event is handled. In preparation to using the helper, fix the driver. Signed-off-by: -
Laurent Pinchart authored
The driver currently handles vblank events only when updating planes on a CRTC. The atomic update API however allows requesting an event when disabling a CRTC. This currently leads to event objects being leaked in the kernel and to events not being sent out. Fix it. Signed-off-by:
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- 09 Feb, 2017 1 commit
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Shawn Guo authored
The vblank hooks in struct drm_driver are deprecated and only meant for legacy drivers. For modern drivers with DRIVER_MODESET flag, the hooks in struct drm_crtc_funcs should be used instead. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by:
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- 14 Nov, 2016 2 commits
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Koji Matsuoka authored
The VSL and HSL bits in the DSMR register set the corresponding horizontal and vertical sync signal polarity to active high. The code got it the wrong way around, fix it. Signed-off-by:
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Koji Matsuoka authored
There is a bug in the setting of the DES (Display Enable Signal) register. This current setting occurs 1 dot left shift. The DES register should be set minus one value about the specifying value with H/W specification. This patch corrects it. Signed-off-by:
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- 29 Jul, 2016 1 commit
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Benjamin Gaignard authored
version 6: rebased patch on top rcar-du changes for zpos version 4: fix null pointer issue while setting zpos in plane reset function This patch replaces zpos property handling custom code in rcar DRM driver with calls to generic DRM code. Signed-off-by:
Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by:
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- 12 Jul, 2016 1 commit
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Gustavo Padovan authored
Remove legacy usage of drm_handle_vblank() Signed-off-by:
Gustavo Padovan <gustavo.padovan@collabora.co.uk> Signed-off-by:
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- 02 May, 2016 1 commit
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Gustavo Padovan authored
Replace the legacy drm_send_vblank_event() with the new helper function. Signed-off-by:
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- 04 Mar, 2016 1 commit
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Carlos Palminha authored
This patch set nukes all the dummy crtc mode_fixup implementations. (made on top of Daniel topic/drm-misc branch) Signed-off-by:
Carlos Palminha <palminha@synopsys.com> Reviewed-by:
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