1. 01 Sep, 2017 1 commit
  2. 31 Aug, 2017 1 commit
    • Eugeniy Paltsev's avatar
      ARC: clk: introduce HSDK pll driver · daeeb438
      Eugeniy Paltsev authored
      
      
      HSDK board manages its clocks using various PLLs. These PLL have same
      dividers and corresponding control registers mapped to different addresses.
      So we add one common driver for such PLLs.
      
      Each PLL on HSDK board consists of three dividers: IDIV, FBDIV and
      ODIV. Output clock value is managed using these dividers.
      
      We add pre-defined tables with supported rate values and appropriate
      configurations of IDIV, FBDIV and ODIV for each value.
      
      As of today we add support for PLLs that generate clock for the
      HSDK arc cpus, system, ddr, AXI tunnel and hdmi.
      
      By this patch we add support for several plls (arc cpus pll and others),
      so we had to use two different init types: CLK_OF_DECLARE for arc cpus pll
      and regular probing for others plls.
      Signed-off-by: default avatarEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
      Reviewed-by: default avatarVineet Gupta <vgupta@synopsys.com>
      Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      daeeb438
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  15. 15 Jun, 2017 1 commit
    • Tony Lindgren's avatar
      Documentation: dt-bindings: Add binding documentation for TI clkctrl clocks · 35395a9c
      Tony Lindgren authored
      
      
      Texas Instruments omap variant SoCs starting with omap4 have a clkctrl
      clock controller instance for each interconnect target module. The clkctrl
      controls functional and interface clocks for the module.
      
      The clkctrl clocks are currently handled by arch/arm/mach-omap2 hwmod code.
      With this binding and a related clock device driver we can start moving the
      clkctrl clock handling to live in drivers/clk/ti.
      
      Note that this binding allows keeping the clockdomain related parts out of
      drivers/clock. The CLKCTCTRL and DYNAMICDEP registers can be handled by
      a separate driver in drivers/soc/ti and genpd. If the clockdomain driver
      needs to know it's clocks, we can just set the the clkctrl device
      instances to be children of the related clockdomain device.
      
      Each clkctrl clock can have multiple optional gate clocks, and multiple
      optional mux clocks. To represent this in device tree, it seems that
      it is best done using four clock cells #clock-cells = <2> property.
      
      The reasons for using #clock-cells = <2> are:
      
      1. We need to specify the clkctrl offset from the instance base. Otherwise
         we end up with a large number of device tree nodes that need to be
         patched when new clocks are discovered in a clkctrl clock with minor
         hardware revision changes for example
      
      2. On omap5 CM_L3INIT_USB_HOST_HS_CLKCTRL has ten OPTFCLKEN bits. So we
         need to use a separate cell for optional gate clocks to avoid address
         space conflicts
      
      There is probably no need to list input clocks for each clkctrl clock
      instance in the binding. If we want to add them, the standard clocks
      binding can be used for that.
      
      For hardware reference, see omap4430 TRM "Table 3-1312. L4PER_CM2 Registers
      Mapping Summary" for example. It shows one instance of a clkctrl clock
      controller with multiple clkctrl registers.
      
      Cc: Paul Walmsley <paul@pwsan.com>
      Acked-by: Rob Herring's avatarRob Herring <robh@kernel.org>
      Signed-off-by: Tony Lindgren's avatarTony Lindgren <tony@atomide.com>
      Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
      35395a9c
  16. 13 Jun, 2017 1 commit
  17. 12 Jun, 2017 1 commit
    • Martin Blumenstingl's avatar
      clk: meson: meson8b: add compatibles for Meson8 and Meson8m2 · 855f06a1
      Martin Blumenstingl authored
      
      
      The clock controller on Meson8, Meson8b and Meson8m2 is very similar
      based on the code from the Amlogic GPL kernel sources. Add separate
      compatibles for each SoC to make sure that we can easily implement
      all the small differences for each SoC later on.
      
      In general the Meson8 and Meson8m2 seem to be almost identical as they
      even share the same mach-meson8 directory in Amlogic's GPL kernel
      sources.
      The main clocks on Meson8, Meson8b and Meson8m2 are very similar,
      because they are all using the same PLL values, 90% of the clock gates
      are the same (the actual diffstat of the mach-meson8/clock.c and
      mach-meson8b/clock.c files is around 30 to 40 lines, when excluding
      all commented out code).
      The difference between the Meson8 and Meson8b clock gates seem to be:
      - Meson8 has AIU_PCLK, HDMI_RX, VCLK2_ENCT, VCLK2_ENCL, UART3,
        CSI_DIG_CLKIN gates which don't seem to be available on Meson8b
      - the gate on Meson8 for bit 7 seems to be named "_1200XXX" instead
        of "PERIPHS_TOP" (on Meson8b)
      - Meson8b has a SANA gate which doesn't seem to exist on Meson8 (or
        on Meson8 the same bit is used by the UART3 gate in Amlogic's GPL
        kernel sources)
      None of these gates is added for now, since it's unclear whether these
      definitions are actually correct (the VCLK2_ENCT gate for example is
      defined, but only used in some commented block).
      
      The main difference between all three SoCs seem to be the video (VPU)
      clocks. Apart from different supported clock rates (according to vpu.c
      in mach-meson8 and mach-meson8b from Amlogic's GPL kernel sources) the
      most notable difference is that Meson8m2 has a GP_PLL clock and a mux
      (probably the same as on the Meson GX SoCs) to support glitch-free
      (clock rate) switching.
      None of these VPU clocks are not supported by our mainline meson8b
      clock driver yet though.
      Signed-off-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
      Acked-by: Rob Herring's avatarRob Herring <robh@kernel.org>
      Acked-by: default avatarKevin Hilman <khilman@baylibre.com>
      Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
      855f06a1
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