1. 10 Feb, 2010 1 commit
    • Suresh Siddha's avatar
      x86, apic: Don't use logical-flat mode when CPU hotplug may exceed 8 CPUs · 681ee44d
      Suresh Siddha authored
      We need to fall back from logical-flat APIC mode to physical-flat mode
      when we have more than 8 CPUs.  However, in the presence of CPU
      hotplug(with bios listing not enabled but possible cpus as disabled cpus in
      MADT), we have to consider the number of possible CPUs rather than
      the number of current CPUs; otherwise we may cross the 8-CPU boundary
      when CPUs are added later.
      
      32bit apic code can use more cleanups (like the removal of vendor checks in
      32bit default_setup_apic_routing()) and more unifications with 64bit code.
      Yinghai has some patches in works already. This patch addresses the boot issue
      that is reported in the virtualization guest context.
      
      [ hpa: incorporated function annotation feedback from Yinghai Lu ]
      Signed-off-by: default avatarSuresh Siddha <suresh.b.siddha@intel.com>
      LKML-Reference: <1265767304.2833.19.camel@sbs-t61.sc.intel.com>
      Acked-by: default avatarShaohui Zheng <shaohui.zheng@intel.com>
      Reviewed-by: default avatarYinghai Lu <yinghai@kernel.org>
      Cc: <stable@kernel.org>
      Signed-off-by: default avatarH. Peter Anvin <hpa@zytor.com>
      681ee44d
  2. 06 Jan, 2010 1 commit
  3. 04 Dec, 2009 1 commit
  4. 28 Aug, 2009 1 commit
    • Feng Tang's avatar
      ACPI, x86: expose some IO-APIC routines when CONFIG_ACPI=n · 2a4ab640
      Feng Tang authored
      Some IO-APIC routines are ACPI specific now, but need to
      be exposed when CONFIG_ACPI=n for the benefit of SFI.
      
      Remove #ifdef ACPI around these routines:
      
      io_apic_get_unique_id(int ioapic, int apic_id);
      io_apic_get_version(int ioapic);
      io_apic_get_redir_entries(int ioapic);
      
      Move these routines from ACPI-specific boot.c to io_apic.c:
      
      uniq_ioapic_id(u8 id)
      mp_find_ioapic()
      mp_find_ioapic_pin()
      mp_register_ioapic()
      
      Also, since uniq_ioapic_id() is now no longer static,
      re-name it to io_apic_unique_id() for consistency
      with the other public io_apic routines.
      
      For simplicity, do not #ifdef the resulting code ACPI || SFI,
      thought that could be done in the future if it is important
      to optimize the !ACPI !SFI IO-APIC x86 kernel for size.
      Signed-off-by: default avatarFeng Tang <feng.tang@intel.com>
      Signed-off-by: default avatarLen Brown <len.brown@intel.com>
      Cc: x86@kernel.org
      2a4ab640
  5. 27 Aug, 2009 1 commit
  6. 14 Jul, 2009 1 commit
  7. 13 Jun, 2009 3 commits
  8. 02 Jun, 2009 1 commit
    • Naga Chumbalkar's avatar
      x86: Print real IOAPIC version for x86-64 · 58f892e0
      Naga Chumbalkar authored
      Fix the fact that the IOAPIC version number in the x86_64 code path always
      gets assigned to 0, instead of the correct value.
      
      Before the patch: (from "dmesg" output):
      
       ACPI: IOAPIC (id[0x08] address[0xfec00000] gsi_base[0])
       IOAPIC[0]: apic_id 8, version 0, address 0xfec00000, GSI 0-23     <---
      
       After the patch:
       ACPI: IOAPIC (id[0x08] address[0xfec00000] gsi_base[0])
       IOAPIC[0]: apic_id 8, version 32, address 0xfec00000, GSI 0-23    <---
      
      History:
      
      io_apic_get_version() was compiled out of the x86_64 code path in the commit
      f2c2cca3:
      
      Author: Andi Kleen <ak@suse.de>
      Date:   Tue Sep 26 10:52:37 2006 +0200
      
          [PATCH] Remove APIC version/cpu capability mpparse checking/printing
      
          ACPI went to great trouble to get the APIC version and CPU capabilities
          of different CPUs before passing them to the mpparser. But all
          that data was used was to print it out.  Actually it even faked some data
          based on the boot cpu, not on the actual CPU being booted.
      
          Remove all this code because it's not needed.
      
          Cc: len.brown@intel.com
      
      At the time, the IOAPIC version number was deliberately not printed
      in the x86_64 code path. However, after the x86 and x86_64 files were
      merged, the net result is that the IOAPIC version is printed incorrectly
      in the x86_64 code path.
      
      The patch below provides a fix. I have tested it with acpi, and with
      acpi=off, and did not see any problems.
      Signed-off-by: default avatarNaga Chumbalkar <nagananda.chumbalkar@hp.com>
      Acked-by: default avatarYinghai Lu <yhlu.kernel@gmail.com>
      LKML-Reference: <20090416014230.4885.94926.sendpatchset@localhost.localdomain>
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      *************************
      58f892e0
  9. 18 May, 2009 2 commits
    • Yinghai Lu's avatar
      x86, irq: don't call mp_config_acpi_gsi() if update_mptable is not enabled · f1bdb523
      Yinghai Lu authored
      Len expressed concern that the update_mptable feature has
      side-effects on the ACPI code.
      
      Make it sure explicitly that the code only ever gets called if
      the (default disabled) update_mptable boot quirk option is
      disabled.
      
      [ Impact: isolate the update_mptable feature from ACPI code more ]
      Signed-off-by: default avatarYinghai Lu <yinghai@kernel.org>
      Cc: Len Brown <lenb@kernel.org>
      LKML-Reference: <4A0DC832.5090200@kernel.org>
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      f1bdb523
    • Yinghai Lu's avatar
      x86, apic: introduce io_apic_irq_attr · e5198075
      Yinghai Lu authored
      according to Ingo, io_apic irq-setup related functions have too many
      parameters with a repetitive signature.
      
      So reduce related funcs to get less params by passing a pointer
      to a newly defined io_apic_irq_attr structure.
      
      v2: io_apic_irq ==> irq_attr
          triggering ==> trigger
      
      v3: add set_io_apic_irq_attr
      
      [ Impact: cleanup ]
      Signed-off-by: default avatarYinghai Lu <yinghai@kernel.org>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
      Cc: Len Brown <lenb@kernel.org>
      LKML-Reference: <4A08ACD3.2070401@kernel.org>
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      e5198075
  10. 11 May, 2009 3 commits
    • Yinghai Lu's avatar
      x86/acpi: move pin_programmed bit map to io_apic.c · bdfe8ac1
      Yinghai Lu authored
      Prepare to call setup_io_apic_routing() in pcibios_irq_enable()
      also remove not needed member apic_id.
      
      [ Impact: clean up, prepare for future change ]
      Signed-off-by: default avatarYinghai Lu <yinghai@kernel.org>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
      Cc: Len Brown <lenb@kernel.org>
      LKML-Reference: <4A01C3DD.3050104@kernel.org>
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      bdfe8ac1
    • Yinghai Lu's avatar
      x86/acpi: call mp_config_acpi_gsi() in mp_register_gsi() · a31f8205
      Yinghai Lu authored
      The patch to call mp_config_acpi_gsi() from the ACPI IRQ registration
      code never got mainline because there were open discussions about it.
      
      This call is needed to properly update the kernel's copy of the mptable,
      when the update_mptable boot parameter is needed.
      
      Now that the dust has settled with the APIC unification, and since there
      were no objections when the patch was re-submitted, try this again.
      
      [ Impact: fix the update_mptable boot parameter ]
      Signed-off-by: default avatarYinghai Lu <yinghai@kernel.org>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
      Cc: Len Brown <lenb@kernel.org>
      LKML-Reference: <4A01C387.7090103@kernel.org>
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      a31f8205
    • Yinghai Lu's avatar
      x86/acpi: remove irq-compression trick on 32-bit · b9e0353f
      Yinghai Lu authored
      We already have a per cpu vector on 32-bit via recent changes, and
      don't need this trick any more (which trick obfuscates the real GSI
      mappings and which only triggers on larger systems to begin with):
      
      On 3 ioapic system (24 per ioapic) before patch I got:
      
      ACPI: PCI Interrupt Link [ILSB] enabled at IRQ 71
      IOAPIC[2]: Set routing entry (10-23 -> 0xa9 -> IRQ 64 Mode:1 Active:1)
      pci 0000:80:01.1: PCI INT A -> Link[ILSB] -> GSI 71 (level, low) -> IRQ 64
      ACPI: PCI Interrupt Link [LE5B] enabled at IRQ 67
      IOAPIC[2]: Set routing entry (10-19 -> 0xb1 -> IRQ 65 Mode:1 Active:1)
      pci 0000:83:00.0: PCI INT B -> Link[LE5B] -> GSI 67 (level, low) -> IRQ 65
      ACPI: PCI Interrupt Link [LE5A] enabled at IRQ 66
      IOAPIC[2]: Set routing entry (10-18 -> 0xb9 -> IRQ 66 Mode:1 Active:1)
      pci 0000:83:00.1: PCI INT A -> Link[LE5A] -> GSI 66 (level, low) -> IRQ 66
      ACPI: PCI Interrupt Link [LE5D] enabled at IRQ 65
      IOAPIC[2]: Set routing entry (10-17 -> 0xc1 -> IRQ 67 Mode:1 Active:1)
      pci 0000:84:00.0: PCI INT B -> Link[LE5D] -> GSI 65 (level, low) -> IRQ 67
      ACPI: PCI Interrupt Link [LE5C] enabled at IRQ 64
      IOAPIC[2]: Set routing entry (10-16 -> 0xc9 -> IRQ 68 Mode:1 Active:1)
      pci 0000:84:00.1: PCI INT A -> Link[LE5C] -> GSI 64 (level, low) -> IRQ 68
      pci 0000:87:00.0: PCI INT B -> Link[LE5A] -> GSI 66 (level, low) -> IRQ 66
      pci 0000:87:00.1: PCI INT A -> Link[LE5D] -> GSI 65 (level, low) -> IRQ 67
      pci 0000:88:00.0: PCI INT B -> Link[LE5C] -> GSI 64 (level, low) -> IRQ 68
      pci 0000:88:00.1: PCI INT A -> Link[LE5B] -> GSI 67 (level, low) -> IRQ 65
      pci 0000:8b:00.0: PCI INT B -> Link[LE5A] -> GSI 66 (level, low) -> IRQ 66
      pci 0000:8b:00.1: PCI INT A -> Link[LE5D] -> GSI 65 (level, low) -> IRQ 67
      pci 0000:8c:00.0: PCI INT B -> Link[LE5C] -> GSI 64 (level, low) -> IRQ 68
      pci 0000:8c:00.1: PCI INT A -> Link[LE5B] -> GSI 67 (level, low) -> IRQ 65
      
      after the patch we get:
      
      ACPI: PCI Interrupt Link [ILSB] enabled at IRQ 71
      IOAPIC[2]: Set routing entry (10-23 -> 0xa9 -> IRQ 71 Mode:1 Active:1)
      pci 0000:80:01.1: PCI INT A -> Link[ILSB] -> GSI 71 (level, low) -> IRQ 71
      ACPI: PCI Interrupt Link [LE5B] enabled at IRQ 67
      IOAPIC[2]: Set routing entry (10-19 -> 0xb1 -> IRQ 67 Mode:1 Active:1)
      pci 0000:83:00.0: PCI INT B -> Link[LE5B] -> GSI 67 (level, low) -> IRQ 67
      ACPI: PCI Interrupt Link [LE5A] enabled at IRQ 66
      IOAPIC[2]: Set routing entry (10-18 -> 0xb9 -> IRQ 66 Mode:1 Active:1)
      pci 0000:83:00.1: PCI INT A -> Link[LE5A] -> GSI 66 (level, low) -> IRQ 66
      ACPI: PCI Interrupt Link [LE5D] enabled at IRQ 65
      IOAPIC[2]: Set routing entry (10-17 -> 0xc1 -> IRQ 65 Mode:1 Active:1)
      pci 0000:84:00.0: PCI INT B -> Link[LE5D] -> GSI 65 (level, low) -> IRQ 65
      ACPI: PCI Interrupt Link [LE5C] enabled at IRQ 64
      IOAPIC[2]: Set routing entry (10-16 -> 0xc9 -> IRQ 64 Mode:1 Active:1)
      pci 0000:84:00.1: PCI INT A -> Link[LE5C] -> GSI 64 (level, low) -> IRQ 64
      pci 0000:87:00.0: PCI INT B -> Link[LE5A] -> GSI 66 (level, low) -> IRQ 66
      pci 0000:87:00.1: PCI INT A -> Link[LE5D] -> GSI 65 (level, low) -> IRQ 65
      pci 0000:88:00.0: PCI INT B -> Link[LE5C] -> GSI 64 (level, low) -> IRQ 64
      pci 0000:88:00.1: PCI INT A -> Link[LE5B] -> GSI 67 (level, low) -> IRQ 67
      pci 0000:8b:00.0: PCI INT B -> Link[LE5A] -> GSI 66 (level, low) -> IRQ 66
      pci 0000:8b:00.1: PCI INT A -> Link[LE5D] -> GSI 65 (level, low) -> IRQ 65
      pci 0000:8c:00.0: PCI INT B -> Link[LE5C] -> GSI 64 (level, low) -> IRQ 64
      pci 0000:8c:00.1: PCI INT A -> Link[LE5B] -> GSI 67 (level, low) -> IRQ 67
      
      As it can be seen that GSIs now get mapped lineary.
      
      [ Impact: simplify irq number mapping on bigger 32-bit systems ]
      Signed-off-by: default avatarYinghai Lu <yinghai@kernel.org>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
      Cc: Len Brown <lenb@kernel.org>
      LKML-Reference: <4A01C35C.7060207@kernel.org>
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      b9e0353f
  11. 28 Apr, 2009 1 commit
    • Yinghai Lu's avatar
      irq: change ACPI GSI APIs to also take a device argument · a2f809b0
      Yinghai Lu authored
      We want to use dev_to_node() later on, to be aware of the 'home node'
      of the GSI in question.
      
      [ Impact: cleanup, prepare the IRQ code to be more NUMA aware ]
      Signed-off-by: default avatarYinghai Lu <yinghai@kernel.org>
      Acked-by: default avatarLen Brown <lenb@kernel.org>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      Cc: Suresh Siddha <suresh.b.siddha@intel.com>
      Cc: "Eric W. Biederman" <ebiederm@xmission.com>
      Cc: Rusty Russell <rusty@rustcorp.com.au>
      Cc: Len Brown <lenb@kernel.org>
      Cc: Bjorn Helgaas <bjorn.helgaas@hp.com>
      Cc: Tony Luck <tony.luck@intel.com>
      Cc: linux-acpi@vger.kernel.org
      Cc: linux-ia64@vger.kernel.org
      LKML-Reference: <49F65560.20904@kernel.org>
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      a2f809b0
  12. 04 Apr, 2009 1 commit
    • Suresh Siddha's avatar
      x86, ACPI: add support for x2apic ACPI extensions · 7237d3de
      Suresh Siddha authored
      All logical processors with APIC ID values of 255 and greater will have their
      APIC reported through Processor X2APIC structure (type-9 entry type) and all
      logical processors with APIC ID less than 255 will have their APIC reported
      through legacy Processor Local APIC (type-0 entry type) only. This is the
      same case even for NMI structure reporting.
          
      The Processor X2APIC Affinity structure provides the association between the
      X2APIC ID of a logical processor and the proximity domain to which the logical
      processor belongs.
          
      For OSPM, Procssor IDs outside the 0-254 range are to be declared as Device()
      objects in the ACPI namespace.
      Signed-off-by: default avatarSuresh Siddha <suresh.b.siddha@intel.com>
      Signed-off-by: default avatarLen Brown <len.brown@intel.com>
      7237d3de
  13. 03 Apr, 2009 1 commit
  14. 17 Feb, 2009 2 commits
  15. 09 Feb, 2009 8 commits
  16. 30 Jan, 2009 1 commit
  17. 29 Jan, 2009 2 commits
  18. 28 Jan, 2009 3 commits
  19. 14 Jan, 2009 2 commits
  20. 09 Jan, 2009 1 commit
  21. 03 Jan, 2009 2 commits
  22. 23 Dec, 2008 1 commit