1. 26 Nov, 2018 1 commit
    • Neil Armstrong's avatar
      drm/meson: Fixes for drm_crtc_vblank_on/off support · 2bcd3eca
      Neil Armstrong authored
      Since Linux 4.17, calls to drm_crtc_vblank_on/off are mandatory, and we get
      a warning when ctrc is disabled :
      " driver forgot to call drm_crtc_vblank_off()"
      But, the vsync IRQ was not totally disabled due the transient hardware
      state and specific interrupt line, thus adding proper IRQ masking from
      the HHI system control registers.
      The last change fixes a race condition introduced by calling the added
      drm_crtc_vblank_on/off when an HPD event occurs from the HDMI connector,
      triggering a WARN_ON() in the _atomic_begin() callback when the CRTC
      is disabled, thus also triggering a WARN_ON() in drm_vblank_put() :
      WARNING: CPU: 0 PID: 1185 at drivers/gpu/drm/meson/meson_crtc.c:157 meson_crtc_atomic_begin+0x78/0x80
      Call trace:
      WARNING: CPU: 0 PID: 1185 at drivers/gpu/drm/drm_vblank.c:1026 drm_vblank_put+0xb4/0xc8
       Call trace:
      The issue is that vblank need to be enabled in any occurrence of :
      - atomic_enable()
      - atomic_begin() and state->enable == true, which was not the case
      Moving the CRTC enable code to a common function and calling in one of
      these occurrence solves this race condition and makes sure vblank is
      enabled in each call to _atomic_begin() from the HPD event leading to
      To Summarize :
      - Make sure that the CRTC code will call the drm_crtc_vblank_on()/off()
      - *Really* mask the Vsync IRQ
      - Initialize and enable vblank at the first
      Cc: stable@vger.kernel.org # 4.17+
      Signed-off-by: Neil Armstrong's avatarNeil Armstrong <narmstrong@baylibre.com>
      Reviewed-by: Lyude Paul's avatarLyude Paul <lyude@redhat.com>
      [fixed typos+added cc for stable]
      Signed-off-by: Lyude Paul's avatarLyude Paul <lyude@redhat.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20181122160103.10993-1-narmstrong@baylibre.comSigned-off-by: Sean Paul's avatarSean Paul <seanpaul@chromium.org>
  2. 20 Feb, 2018 1 commit
  3. 30 Jun, 2017 2 commits
  4. 04 Apr, 2017 1 commit
  5. 09 Feb, 2017 1 commit
  6. 01 Dec, 2016 1 commit
    • Neil Armstrong's avatar
      drm: Add support for Amlogic Meson Graphic Controller · bbbe775e
      Neil Armstrong authored
      The Amlogic Meson Display controller is composed of several components :
      DMC|---------------VPU (Video Processing Unit)----------------|------HHI------|
         | vd1   _______     _____________    _________________     |               |
      D  |-------|      |----|            |   |                |    |   HDMI PLL    |
      D  | vd2   | VIU  |    | Video Post |   | Video Encoders |<---|-----VCLK      |
      R  |-------|      |----| Processing |   |                |    |               |
         | osd2  |      |    |            |---| Enci ----------|----|-----VDAC------|
      R  |-------| CSC  |----| Scalers    |   | Encp ----------|----|----HDMI-TX----|
      A  | osd1  |      |    | Blenders   |   | Encl ----------|----|---------------|
      M  |-------|______|----|____________|   |________________|    |               |
      VIU: Video Input Unit
      The Video Input Unit is in charge of the pixel scanout from the DDR memory.
      It fetches the frames addresses, stride and parameters from the "Canvas" memory.
      This part is also in charge of the CSC (Colorspace Conversion).
      It can handle 2 OSD Planes and 2 Video Planes.
      VPP: Video Post Processing
      The Video Post Processing is in charge of the scaling and blending of the
      various planes into a single pixel stream.
      There is a special "pre-blending" used by the video planes with a dedicated
      scaler and a "post-blending" to merge with the OSD Planes.
      The OSD planes also have a dedicated scaler for one of the OSD.
      VENC: Video Encoders
      The VENC is composed of the multiple pixel encoders :
       - ENCI : Interlace Video encoder for CVBS and Interlace HDMI
       - ENCP : Progressive Video Encoder for HDMI
       - ENCL : LCD LVDS Encoder
      The VENC Unit gets a Pixel Clocks (VCLK) from a dedicated HDMI PLL and clock
      tree and provides the scanout clock to the VPP and VIU.
      The ENCI is connected to a single VDAC for Composite Output.
      The ENCI and ENCP are connected to an on-chip HDMI Transceiver.
      This driver is a DRM/KMS driver using the following DRM components :
       - GEM-CMA
       - PRIME-CMA
       - Atomic Modesetting
       - FBDev-CMA
      For the following SoCs :
       - GXBB Family (S905)
       - GXL Family (S905X, S905D)
       - GXM Family (S912)
      The current driver only supports the CVBS PAL/NTSC output modes, but the
      CRTC/Planes management should support bigger modes.
      But Advanced Colorspace Conversion, Scaling and HDMI Modes will be added in
      a second time.
      The Device Tree bindings makes use of the endpoints video interface definitions
      to connect to the optional CVBS and in the future the HDMI Connector nodes.
      HDMI Support is planned for a next release.
      Acked-by: Daniel Vetter's avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      Signed-off-by: Neil Armstrong's avatarNeil Armstrong <narmstrong@baylibre.com>