1. 24 Aug, 2005 1 commit
  2. 27 Jul, 2005 1 commit
    • David Gibson's avatar
      [PATCH] ppc64: dynamically allocate segment tables · 533f0817
      David Gibson authored
      
      
      PPC64 machines before Power4 need a segment table page allocated for each
      CPU.  Currently these are allocated statically in a big array in head.S for
      all CPUs.  The segment tables need to be in the first segment (so
      do_stab_bolted doesn't take a recursive fault on the stab itself), but
      other than that there are no constraints which require the stabs for the
      secondary CPUs to be statically allocated.
      
      This patch allocates segment tables dynamically during boot, using
      lmb_alloc() to ensure they are within the first 256M segment.  This reduces
      the kernel image size by 192k...
      
      Tested on RS64 iSeries, POWER3 pSeries, and POWER5.
      Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
      Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
      533f0817
  3. 26 Jul, 2005 1 commit
  4. 08 Jul, 2005 2 commits
  5. 25 Jun, 2005 1 commit
    • R Sharada's avatar
      [PATCH] ppc64: kexec support for ppc64 · fce0d574
      R Sharada authored
      
      
      This patch implements the kexec support for ppc64 platforms.
      
      A couple of notes:
      
      1)  We copy the pages in virtual mode, using the full base kernel
          and a statically allocated stack.   At kexec_prepare time we
          scan the pages and if any overlap our (0, _end[]) range we
          return -ETXTBSY.
      
          On PowerPC 64 systems running in LPAR (logical partitioning)
          mode, only a small region of memory, referred to as the RMO,
          can be accessed in real mode.  Since Linux runs with only one
          zone of memory in the memory allocator, and it can be orders of
          magnitude more memory than the RMO, looping until we allocate
          pages in the source region is not feasible.  Copying in virtual
          means we don't have to write a hash table generation and call
          hypervisor to insert translations, instead we rely on the pinned
          kernel linear mapping.  The kernel already has move to linked
          location built in, so there is no requirement to load it at 0.
      
          If we want to load something other than a kernel, then a stub
          can be written to copy a linear chunk in real mode.
      
      2)  The start entry point gets passed parameters from the kernel.
          Slaves are started at a fixed address after copying code from
          the entry point.
      
          All CPUs get passed their firmware assigned physical id in r3
          (most calling conventions use this register for the first
          argument).
      
          This is used to distinguish each CPU from all other CPUs.
          Since firmware is not around, there is no other way to obtain
          this information other than to pass it somewhere.
      
          A single CPU, referred to here as the master and the one executing
          the kexec call, branches to start with the address of start in r4.
          While this can be calculated, we have to load it through a gpr to
          branch to this point so defining the register this is contained
          in is free.  A stack of unspecified size is available at r1
          (also common calling convention).
      
          All remaining running CPUs are sent to start at absolute address
          0x60 after copying the first 0x100 bytes from start to address 0.
          This convention was chosen because it matches what the kernel
          has been doing itself.  (only gpr3 is defined).
      
          Note: This is not quite the convention of the kexec bootblock v2
          in the kernel.  A stub has been written to convert between them,
          and we may adjust the kernel in the future to allow this directly
          without any stub.
      
      3)  Destination pages can be placed anywhere, even where they
          would not be accessible in real mode.  This will allow us to
          place ram disks above the RMO if we choose.
      Signed-off-by: default avatarMilton Miller <miltonm@bga.com>
      Signed-off-by: default avatarR Sharada <sharada@in.ibm.com>
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
      Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
      fce0d574
  6. 23 Jun, 2005 3 commits
    • Andy Whitcroft's avatar
      [PATCH] ppc64: sparsemem memory model · 145e6642
      Andy Whitcroft authored
      
      
      Provide the architecture specific implementation for SPARSEMEM for PPC64
      systems.
      Signed-off-by: default avatarAndy Whitcroft <apw@shadowen.org>
      Signed-off-by: default avatarDave Hansen <haveblue@us.ibm.com>
      Signed-off-by: Mike Kravetz <kravetz@us.ibm.com> (in part)
      Signed-off-by: default avatarMartin Bligh <mbligh@aracnet.com>
      Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
      Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
      145e6642
    • David Gibson's avatar
      [PATCH] Maple powerdown patch · d7152fe1
      David Gibson authored
      
      
      Currently reset and powerdown are not implemented on the Maple board,
      and attempting to do so will (incorrectly return).  This implements
      the proper communication with the service processor, allowing correct
      reset and powerdown on the Maple board, by communicating with the
      service processor.  If somehow it's unable to communicate with the
      service processor it will loop forever instead.
      
      Note that powerdown on the Maple will power down the CPUs, but not the
      fans or other board components due to hardware and firmware
      limitations.
      Signed-off-by: default avatarDavid Gibson <dwg@au1.ibm.com>
      Signed-off-by: default avatarFrank Rowand <frowand@mvista.com>
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      d7152fe1
    • Mike Strosaker's avatar
      [PATCH] correct printing to operator panel · 8f586b22
      Mike Strosaker authored
      
      
      This patch corrects the printing of progress indicators to the op
      panel on p/iSeries ppc64 systems.  Each discrete reference code should
      begin with a form feed char to clear the op panel, and the first and
      second lines should be separated with a CR/LF sequence.  Padding with
      spaces is not necessary.
      
      Also, capitalize the hex value printed on the first line, to be
      consistent with the values printed by firmware, service processor,
      etc.
      
      It turns out that there's an ibm,form-feed property; this patch uses
      it in the pSeries-specific progress routine.  This patch also checks
      the number of rows and the specific width of each row (the second row
      on power5 systems can actually hold 80 characters).  If the displayed
      text is too wide for the physical display, it can be viewed in the ASM
      menus, or by selecting option 14 on the op panel.
      Signed-off-by: default avatarMike Strosaker <strosake@austin.ibm.com>
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      8f586b22
  7. 22 Jun, 2005 3 commits
  8. 02 Jun, 2005 1 commit
  9. 16 Apr, 2005 1 commit
    • Linus Torvalds's avatar
      Linux-2.6.12-rc2 · 1da177e4
      Linus Torvalds authored
      Initial git repository build. I'm not bothering with the full history,
      even though we have it. We can create a separate "historical" git
      archive of that later if we want to, and in the meantime it's about
      3.2GB when imported into git - space that would just make the early
      git days unnecessarily complicated, when we don't have a lot of good
      infrastructure for it.
      
      Let it rip!
      1da177e4