1. 14 Aug, 2013 2 commits
  2. 25 Jun, 2013 1 commit
    • Srinivas KANDAGATLA's avatar
      pinctrl: st: Add pinctrl and pinconf support. · 701016c0
      Srinivas KANDAGATLA authored
      This patch add pinctrl support to ST SoCs.
      
      About hardware:
      ST Set-Top-Box parts have two blocks called PIO and PIO-mux which handle
      pin configurations.
      
      Each multi-function pin is controlled, driven and routed through the PIO
      multiplexing block. Each pin supports GPIO functionality (ALT0) and
      multiple alternate functions(ALT1 - ALTx) that directly connect the pin
      to different hardware blocks. When a pin is in GPIO mode, Output Enable
      (OE), Open Drain(OD), and Pull Up (PU) are driven by the related PIO
      block. Otherwise the PIO multiplexing block configures these parameters
      and retiming the signal.
      
      About driver:
      This pinctrl driver manages both PIO and PIO-mux block using pinctrl,
      pinconf, pinmux, gpio subsystems. All the pinctrl related config
      information can only come from device trees.
      Signed-off-by: default avatarSrinivas Kandagatla <srinivas.kandagatla@st.com>
      Acked-by: Linus Walleij's avatarLinus Walleij <linus.walleij@linaro.org>
      Signed-off-by: default avatarMark Brown <broonie@linaro.org>
      701016c0
  3. 24 Jun, 2013 2 commits
    • James Hogan's avatar
      pinctrl-tz1090-pdc: add TZ1090 PDC pinctrl driver · b58f0273
      James Hogan authored
      Add a pin control driver for the TZ1090's low power pins via the
      powerdown controller SOC_GPIO_CONTROL registers.
      
      These pins have individually controlled pull-up, and group controlled
      schmitt, slew-rate, drive-strength, and power-on-start (pos).
      
      The pdc_gpio0 and pdc_gpio1 pins can also be muxed onto the
      ir_mod_stable_out and ir_mod_power_out functions respectively. If no
      function is set they remain in GPIO mode. These muxes can be overridden
      by requesting them as GPIOs.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Grant Likely <grant.likely@linaro.org>
      Cc: Rob Herring <rob.herring@calxeda.com>
      Cc: Rob Landley <rob@landley.net>
      Cc: Linus Walleij <linus.walleij@linaro.org>
      Cc: linux-doc@vger.kernel.org
      Cc: devicetree-discuss@lists.ozlabs.org
      Signed-off-by: Linus Walleij's avatarLinus Walleij <linus.walleij@linaro.org>
      b58f0273
    • James Hogan's avatar
      pinctrl-tz1090: add TZ1090 pinctrl driver · d5025f9f
      James Hogan authored
      Add a pin control driver for the main pins on the TZ1090 SoC. This
      doesn't include the low-power pins as they're controlled separately via
      the Powerdown Controller (PDC) registers.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Grant Likely <grant.likely@linaro.org>
      Cc: Rob Herring <rob.herring@calxeda.com>
      Cc: Rob Landley <rob@landley.net>
      Cc: Linus Walleij <linus.walleij@linaro.org>
      Cc: linux-doc@vger.kernel.org
      Cc: devicetree-discuss@lists.ozlabs.org
      Signed-off-by: Linus Walleij's avatarLinus Walleij <linus.walleij@linaro.org>
      d5025f9f
  4. 18 Jun, 2013 1 commit
  5. 16 Jun, 2013 4 commits
  6. 20 May, 2013 1 commit
    • Heiko Stuebner's avatar
      pinctrl: Add pinctrl-s3c24xx driver · af99a750
      Heiko Stuebner authored
      The s3c24xx pins follow a similar pattern as the other Samsung SoCs and
      can therefore reuse the already introduced infrastructure.
      
      The s3c24xx SoCs have one design oddity in that the first 4 external
      interrupts do not reside in the eint pending register but in the main
      interrupt controller instead. We solve this by forwarding the external
      interrupt from the main controller into the irq domain of the pin bank.
      The masking/acking of these interrupts is handled in the same way.
      
      Furthermore the S3C2412/2413 SoCs contain another oddity in that they
      keep the same 4 eints in the main interrupt controller and eintpend
      register and requiring ack operations to happen in both. This is solved
      by using different compatible properties for the wakeup eint node which
      set a property accordingly.
      Signed-off-by: Heiko Stuebner's avatarHeiko Stuebner <heiko@sntech.de>
      Reviewed-by: default avatarTomasz Figa <t.figa@samsung.com>
      Reviewed-by: default avatarSylwester Nawrocki <s.nawrocki@samsung.com>
      Acked-by: Linus Walleij's avatarLinus Walleij <linus.walleij@linaro.org>
      Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
      af99a750
  7. 09 Apr, 2013 2 commits
  8. 04 Apr, 2013 1 commit
  9. 27 Mar, 2013 1 commit
  10. 05 Feb, 2013 4 commits
  11. 30 Jan, 2013 2 commits
  12. 25 Jan, 2013 1 commit
  13. 22 Jan, 2013 1 commit
  14. 18 Jan, 2013 2 commits
  15. 22 Nov, 2012 1 commit
  16. 11 Nov, 2012 1 commit
  17. 13 Oct, 2012 1 commit
  18. 01 Oct, 2012 1 commit
    • Simon Arlott's avatar
      pinctrl: add bcm2835 driver · e1b2dc70
      Simon Arlott authored
      The BCM2835 GPIO module is a combined GPIO controller, (GPIO) interrupt
      controller, and pinmux/control device.
      
      Original driver by Simon Arlott.
      Rewrite including GPIO chip device by Chris Boot.
      
      Upstreaming changes by Stephen Warren:
      * Wrote DT binding documentation.
      * Changed brcm,function to an integer to more directly match the
        datasheet, and to match brcm,pins being an integer.
      * Implemented pull-up/down pin config.
      * Removed read-only DT property and related code. The restriction this
        implemented are driven by the board, not the GPIO HW block, so don't
        really make sense of a HW block binding, were in general incomplete
        (since they could only know about the few pins hard-coded into the
        Raspberry Pi B board design and not the uncommitted GPIOS), and are
        better represented simply by not writing incorrect data into pin
        configuration nodes.
      * Don't set GPIO_IN function select in gpio_request_enable() to avoid
        glitches; defer this to gpio_set_direction(). Consequently, removed
        empty bcm2835_pmx_gpio_request_enable().
      * Simplified enabled_irq_map[]; make it explicitly 1 entry per bank.
      * Lifted use of enabled_irq_map[] outside the per-interrupt loop in
        IRQ handler, thus fixing an issue where the code was indexing into
        enabled_irq_map[] by intra-bank GPIO ID, not global GPIO ID.
      * Removed locking in IRQ handler, since all other code uses
        spin_lock_irqsave() and so guarantees it doesn't run concurrently
        with the handler.
      * Moved duplicated BUILD_BUG_ON()s into probe(). Also check size of
        bcm2835_gpio_pins[].
      * Remove range-checking from bcm2835_pctl_get_groups_count() since we've
        decided to trust the pinctrl core.
      * Made bcm2835_pmx_gpio_disable_free() call bcm2835_pinctrl_fsel_set()
        directly for simplicity.
      * Fixed body of dt_free_map() to match latest dt_node_to_map().
      * Removed GPIO ownership check from bcm2835_pmx_enable() since the pinctrl
        core owns doing this.
      * Made irq_chip and pinctrl_gpio_range .name == MODULE_NAME so it's more
        descriptive.
      * Simplified remove(); removed call to non-existent
        pinctrl_remove_gpio_range(), remove early return on error.
      * Don't force gpiochip's base to 0. Set gpio_range.base to gpiochip's
        base GPIO number.
      * Error-handling cleanups in probe().
      * Switched to module_platform_driver() rather than open-coding.
      * Made pin, group, and function names lower-case.
      * s/broadcom/brcm/ in DT property names.
      * s/2708/2835/.
      * Fixed a couple minor checkpatch warnings, and other minor cleanup.
      Signed-off-by: default avatarSimon Arlott <simon@fire.lp0.eu>
      Signed-off-by: default avatarChris Boot <bootc@bootc.net>
      Signed-off-by: default avatarStephen Warren <swarren@wwwdotorg.org>
      Signed-off-by: Linus Walleij's avatarLinus Walleij <linus.walleij@linaro.org>
      e1b2dc70
  19. 22 Sep, 2012 5 commits
  20. 13 Sep, 2012 2 commits
  21. 06 Sep, 2012 2 commits
  22. 03 Sep, 2012 2 commits