1. 08 Nov, 2018 1 commit
  2. 30 Aug, 2018 1 commit
    • Rob Herring's avatar
      clk: Convert to using %pOFn instead of device_node.name · e665f029
      Rob Herring authored
      In preparation to remove the node name pointer from struct device_node,
      convert printf users to use the %pOFn format specifier.
      Cc: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
      Cc: Michael Turquette <mturquette@baylibre.com>
      Cc: Stephen Boyd <sboyd@kernel.org>
      Cc: linux-clk@vger.kernel.org
      Cc: linux-arm-kernel@lists.infradead.org
      Cc: linux-renesas-soc@vger.kernel.org
      Cc: linux-omap@vger.kernel.org
      Signed-off-by: Rob Herring's avatarRob Herring <robh@kernel.org>
      Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
  3. 21 Dec, 2017 1 commit
  4. 21 Jul, 2017 3 commits
  5. 01 Jun, 2017 1 commit
  6. 09 Dec, 2016 1 commit
  7. 02 Nov, 2016 2 commits
  8. 18 Aug, 2016 1 commit
  9. 20 Apr, 2016 1 commit
    • Julia Lawall's avatar
      clk: qoriq: add __init attribute · 3432a2e3
      Julia Lawall authored
      Add __init attribute on a function that is only called from other __init
      functions and that is not inlined, at least with gcc version 4.8.4 on an
      x86 machine with allyesconfig.  Currently, the function is put in the
      .text.unlikely segment.  Declaring it as __init will cause it to be put in
      the .init.text and to disappear after initialization.
      The result of objdump -x on the function before the change is as follows:
      0000000000000000 l     F .text.unlikely 0000000000000071 sysclk_from_fixed.constprop.5
      And after the change it is as follows:
      0000000000000480 l     F .init.text	000000000000006c sysclk_from_fixed.constprop.5
      Done with the help of Coccinelle.  The semantic patch checks for local
      static non-init functions that are called from an __init function and are
      not called from any other function.
      Signed-off-by: default avatarJulia Lawall <Julia.Lawall@lip6.fr>
      Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
  10. 15 Apr, 2016 1 commit
  11. 30 Nov, 2015 1 commit
  12. 27 Oct, 2015 1 commit
  13. 23 Oct, 2015 1 commit
  14. 21 Oct, 2015 2 commits
    • Scott Wood's avatar
      clk: qoriq: Add ls2080a support. · 9e19ca2f
      Scott Wood authored
      LS2080A is the first implementation of the chassis 3 clockgen, which
      has a different register layout than previous chips.  It is also little
      endian, unlike previous chips.
      Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
      Acked-by: default avatarStephen Boyd <sboyd@codeaurora.org>
    • Scott Wood's avatar
      clk: qoriq: Move chip-specific knowledge into driver · 0dfc86b3
      Scott Wood authored
      The device tree should describe the chips (or chip-like subblocks) in
      the system, but it generally does not describe individual registers --
      it should identify, rather than describe, a programming interface.
      This has not been the case with the QorIQ clockgen nodes.  The
      knowledge of what each bit setting of CLKCnCSR means is encoded in
      three places (binding, pll node, and mux node), and the last also needs
      to know which options are valid on a particular chip.  All three of
      these locations are considered stable ABI, making it difficult to fix
      mistakes (of which I have found several), much less refactor the
      abstraction to be able to address problems, limitations, or new chips.
      Under the current binding, a pll clock specifier of 2 means that the
      PLL is divided by 4 -- and the driver implements this, unless there
      happen to be four clock-output-names rather than 3, in which case it
      interprets it as PLL divided by 3.  This does not appear in the binding
      documentation at all.  That hack is now considered stable ABI.
      The current device tree nodes contain errors, such as saying that
      T1040 can set a core clock to PLL/4 when only PLL and PLL/2 are options.
      The current binding also ignores some restrictions on clock selection,
      such as p5020's requirement that if a core uses the "wrong" PLL, that
      PLL must be clocked lower than the "correct" PLL and be at most 80% of
      the rated CPU frequency.
      Possibly because of the lack of the ability to express such nuance in
      the binding, some valid options are omitted from the device trees, such
      as the ability on p4080 to run cores 0-3 from PLL3 and cores 4-7 from
      PLL1 (again, only if they are at most 80% of rated CPU frequency).
      This omission, combined with excessive caution in the cpufreq driver
      (addressed in a subsequent patch), means that currently on a 1500 MHz
      p4080 with typical PLL configuration, cpufreq can lower the frequency
      to 1200 MHz on half the CPUs and do nothing on the others.  With this
      patchset, all CPUs can be lowered to 1200 MHz on a rev2 p4080, and on a
      rev3 p4080 half can be lowered to 750 MHz and the other half to 600
      The current binding only deals with CPU clocks.  To describe FMan in
      the device tree, we need to describe its clock.  Some chips have
      additional muxes that work like the CPU muxes, but are not described in
      the device tree.  Others require inspecting the Reset Control Word to
      determine which PLL is used.  Rather than continue to extend this mess,
      replace it.  Have the driver bind to the chip-specific clockgen
      compatible, and keep the detailed description of quirky chip variations
      in the driver, where it can be easily fixed, refactored, and extended.
      Older device trees will continue to work (including a workaround for
      old ls1021a device trees that are missing compatible and reg in the
      clockgen node, which even the old binding required).  The pll/mux
      details in old device trees will be ignored, but "clocks" properties
      pointing at the old nodes will still work, and be directed at the
      corresponding new clock.
      Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
      Acked-by: default avatarStephen Boyd <sboyd@codeaurora.org>
  15. 18 Feb, 2015 1 commit
  16. 28 Jan, 2015 7 commits
  17. 20 Jan, 2015 3 commits
  18. 17 Jan, 2015 1 commit
  19. 20 Oct, 2014 1 commit
  20. 02 Jul, 2014 1 commit
    • Jingchang Lu's avatar
      clk: ppc-corenet: Fix Section mismatch warning · da788acb
      Jingchang Lu authored
      WARNING: drivers/built-in.o(.data+0x10258):
      Section mismatch in reference from the variable ppc_corenet_clk_driver
      to the (unknown reference) .init.rodata:(unknown)
      The variable ppc_corenet_clk_driver references
      the (unknown reference) __initconst (unknown)
      If the reference is valid then annotate the
      variable with __init* or __refdata (see linux/init.h) or name the variable:
      *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console
      Signed-off-by: default avatarJingchang Lu <jingchang.lu@freescale.com>
      Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
  21. 20 Mar, 2014 1 commit
  22. 11 Nov, 2013 1 commit
    • Rob Herring's avatar
      powerpc: add missing explicit OF includes for ppc · c11eede6
      Rob Herring authored
      Commit b5b4bb3f (of: only include prom.h on sparc) removed implicit
      includes of of_*.h headers by powerpc's prom.h. Some components were
      missed in initial clean-up patch, so add the necessary includes to fix
      powerpc builds.
      Signed-off-by: default avatarRob Herring <rob.herring@calxeda.com>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Paul Mackerras <paulus@samba.org>
      Cc: Tejun Heo <tj@kernel.org>
      Cc: Matt Mackall <mpm@selenic.com>
      Cc: Herbert Xu <herbert@gondor.apana.org.au>
      Cc: "David S. Miller" <davem@davemloft.net>
      Cc: Vinod Koul <vinod.koul@intel.com>
      Cc: Dan Williams <dan.j.williams@intel.com>
      Cc: linuxppc-dev@lists.ozlabs.org
      Cc: linux-ide@vger.kernel.org
      Cc: linux-crypto@vger.kernel.org
  23. 30 May, 2013 1 commit
  24. 29 May, 2013 1 commit