1. 22 Jun, 2016 1 commit
    • Axel Lin's avatar
      pinctrl: tegra: Fix build dependency · 19b5a917
      Axel Lin authored
      I got below build error:
      ERROR: "tegra_xusb_padctl_legacy_probe"
       [drivers/phy/tegra/phy-tegra-xusb.ko] undefined!
      with below build configuration:
      The problem is below line in drivers/pinctrl/Makefile
      obj-$(CONFIG_PINCTRL_TEGRA)     += tegra/
      So even CONFIG_PINCTRL_TEGRA_XUSB=y is set, kbuild still does not compile
      the code in drivers/pinctrl/tegra folder if !CONFIG_PINCTRL_TEGRA.
      phy-tegra-xusb.c does not use any symbol from pinctrl-tegra.c,
      so build pinctrl-tegra.c only when CONFIG_PINCTRL_TEGRA is set.
      Signed-off-by: default avatarAxel Lin <axel.lin@ingics.com>
      Acked-by: default avatarJon Hunter <jonathanh@nvidia.com>
      Signed-off-by: Linus Walleij's avatarLinus Walleij <linus.walleij@linaro.org>
  2. 13 Feb, 2016 1 commit
  3. 09 Feb, 2016 1 commit
  4. 05 Feb, 2016 2 commits
  5. 28 Jan, 2016 2 commits
  6. 27 Jan, 2016 1 commit
  7. 10 Dec, 2015 1 commit
  8. 01 Dec, 2015 3 commits
  9. 31 Oct, 2015 1 commit
  10. 21 Sep, 2015 1 commit
  11. 27 Jul, 2015 1 commit
    • Baruch Siach's avatar
      pinctrl: driver for Conexant Digicolor CX92755 pin mapping · 38b0e507
      Baruch Siach authored
      This adds pinctrl and gpio driver to the CX92755 SoC "General
      Purpose Pin Mapping" hardware block. The CX92755 is one SoC
      from the Conexant Digicolor series. Pin mapping hardware supports
      configuring pins as either GPIO, or up to 3 other "client select"
      functions. This driver adds support for pin muxing using the
      generic device tree binding, and a basic gpiolib driver for
      the GPIO functionality.
      This driver does not currently support GPIO interrupts, and
      pad configuration.
      * Address review comments for Linus Walleij:
        - Add a pointer to pinctrl_desc in struct dc_pinmap
        - Drop the now redundant pinctrl_pin_desc field
        - Adapt dc_get_group_{name,pins} to these changes, and
          add a comment explaining the 1-to-1 pin-groups relation
      * Staticise dc_pmxops
      * Protect the GP_CLIENTSEL clct parameter with parenthesis
      Signed-off-by: default avatarBaruch Siach <baruch@tkos.co.il>
      Signed-off-by: Linus Walleij's avatarLinus Walleij <linus.walleij@linaro.org>
  12. 16 Jul, 2015 2 commits
  13. 12 May, 2015 1 commit
  14. 06 May, 2015 1 commit
  15. 18 Mar, 2015 3 commits
  16. 09 Mar, 2015 1 commit
  17. 26 Jan, 2015 1 commit
  18. 11 Jan, 2015 1 commit
    • Soren Brinkmann's avatar
      pinctrl: Add driver for Zynq · add958ce
      Soren Brinkmann authored
      This adds a pin-control driver for Zynq.
      Changes since v2:
      - driver-specific DT properties are passed to the core in two arrays,
        one for the actual DT parsing one for the debugfs representation.
        Issue a compiler warning when the number of entries is not the same
        for both arrays.
      Changes since v1:
       - fix EMIO_SD1_CD pin name
       - add USB to pinmux options
      changes since RFCv2:
       - let Zynq select PINCTRL_ZYNQ. Boot hangs when pinctrl information is
         present in DT but no driver available.
       - add #defines to get rid of magical constants
       - add commas at end of initializers
       - separate changes in mach-zynq in separate patch
       - add driver specific io-standard DT property
       - refactored pinconf set function to not require arguments for
         argument-less properties
       - squash other patches in
         - support for IO-standard property
         - support for low-power mode property
         - migration to pinconf_generic_dt_node_to_map_all()
       - use newly created infrastructure to add pass driver-specific DT
         params to pinconf-generic
      changes since RFC:
       - use syscon/regmap to access registers in SLCR space
       - rebase to 3.18: rename enable -> set_mux
       - add kernel-doc
       - support pinconf
         - supported attributes
           - pin-bias: pull up, tristate, disable
           - slew-rate: 0 == slow, 1 == fast; generic pinconf does not display
      Signed-off-by: default avatarSoren Brinkmann <soren.brinkmann@xilinx.com>
      Tested-by: default avatarAndreas Färber <afaerber@suse.de>
      Signed-off-by: Linus Walleij's avatarLinus Walleij <linus.walleij@linaro.org>
  19. 10 Jan, 2015 1 commit
  20. 29 Oct, 2014 1 commit
  21. 04 Sep, 2014 1 commit
  22. 02 Sep, 2014 1 commit
  23. 29 Aug, 2014 1 commit
  24. 28 Aug, 2014 1 commit
  25. 11 Jul, 2014 6 commits
  26. 27 May, 2014 1 commit
  27. 22 May, 2014 1 commit
    • Antoine Tenart's avatar
      pinctrl: berlin: add the core pinctrl driver for Marvell Berlin SoCs · 3de68d33
      Antoine Tenart authored
      The Marvell Berlin boards have a group based pinmuxing mechanism. This
      adds the core driver support. We actually do not need any information
      about the pins here and only have the definition of the groups.
      Let's take the example of the uart0 pinmuxing on the BG2Q. Balls BK4 and
      BH6 are muxed to respectively UART0 RX and TX if the group GSM12 is set
      to mode 0:
      Group	Modes	Offset Base	Offset	LSB	Bit Width
      GSM12	3	sm_base		0x40	0x10	0x2
      Ball	Group	Mode 0		Mode 1		Mode 2
      BH6	GSM12	UART0_TX	IrDA0_TX	GPIO10
      So in order to configure BK4 -> UART0_TX and BH6 -> UART0_RX, we need
      to set (sm_base + 0x40 + 0x10) &= ff3fffff.
      As pin control registers are part of either chip control or system
      control registers, that deal with a bunch of other functions we rely
      on a regmap instead of exclusively remapping any resources.
      Signed-off-by: default avatarAntoine Tenart <antoine.tenart@free-electrons.com>
      Acked-by: default avatarSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
      Signed-off-by: Linus Walleij's avatarLinus Walleij <linus.walleij@linaro.org>
  28. 04 May, 2014 1 commit