Commit e9a03add authored by Sonic Zhang's avatar Sonic Zhang Committed by Linus Walleij

pinctrl: ADI PIN control driver for the GPIO controller on bf54x and bf60x.

The new ADI GPIO2 controller was introduced since the BF548 and BF60x
processors. It differs a lot from the old one on BF5xx processors. So,
create a pinctrl driver under the pinctrl framework.

- Define gpio ports and pin interrupt controllers as individual platform
  devices.
- Register a pinctrl driver for the whole GPIO ports and pin interrupt
  devices.
- Probe pint devices before port devices. Put device instances into
  the global gpio and pint lists.
- Define peripheral, irq and gpio reservation bit masks for each gpio
  port as runtime resources.
- Save and restore gpio port and pint status MMRs in syscore PM functions.
- Create the plug-in subdrivers to hold the pinctrl soc data for bf54x
  and bf60x. Add soc data into struct adi_pinctrl. Initialize the soc data
  in pin controller probe function. Get the pin groups and functions via
  the soc data reference.
- Call gpiochip_add_pin_range() in gpio device probe function to register
  range cross reference between gpio device and pin control device.
- Get range by pinctrl_find_gpio_range_from_pin(), find gpio_port object
  by container_of() and find adi_pinctrl by pin control device name.
- Handle peripheral and gpio requests in pinctrl operation functions.
- Demux gpio IRQs via the irq_domain created by each GPIO port.

v2-changes:
- Remove unlinke() directive.

v3-changes:
- Rename struct adi_pmx to adi_pinctrl.
- Fix the comments of struct gpio_pint.
- Remove unused pin_base in struct gpio_port.
- Change pint_assign into bool type.
- Add comments about the relationship between pint device and port device
to the driver header.
- Use BIT macro to shift bit.
- Remove all bitmap reservation help functions. Inline reservation functions
into the actual code.
- Remove gpio and offset mutual reference help functions.
- Remove all help functions to find gpio_port and adi_pinctrl structs. Get
range by pinctrl_find_gpio_range_from_pin(), find gpio_port object by
container_of() and find adi_pinctrl by pin control device name.
- Pass bool type usage variable to port_setup help function.
- Separate long bit operations into several lines and add comments.
- Use debugfs to output all GPIO request information.
- Avoid to set drvdata to NULL
- Add explanation to function adi_gpio_init_int()
- Call gpiochip_add_pin_range() in gpio device probe function to register
range cross reference between gpio device and pin control device.
- Remove the reference to pin control device from the gpio_port struct.
Remove the reference list to gpio device from the adi_pinctrl struct.
Replace the global adi_pinctrl list with adi_gpio_port_list. Walk through
the gpio list to do power suspend and resume operations.
- Remove the global GPIO base from struct adi_pinctrl, define pin base in
the platform data for each GPIO port device.
- Initialize adi_pinctrl_setup in arch_initcall().
- print the status of triggers, whether it is in GPIO mode, if it is
flagged to be used as IRQ, etc in adi_pin_dbg_show().
- Create the plug-in subdrivers to hold the pinctrl soc data for bf54x
and bf60x. Add soc data into struct adi_pinctrl. Initialize the soc data
in pin controller probe function. Get the pin groups and functions via
the soc data reference.

v4-changes:
- remove useless system_state checking.
- replace dev_err with dev_warn in both irq and gpio pin cases.
- comment on relationship between irq type and invert operation.
- It is not necessary to check the reservation mode of the requested
pin in IRQ chip operation. Remove the reservation map.
- Use existing gpio/pinctrl subsystem debugfs files. Remove pinctrl-adi2
driver specific debugfs output.
- Add linkport group and function information for bf60x.
- Separate uart and ctsrts pins into 2 groups.
- Separate APAPI and alternative ATAPI pins into 2 groups.
Signed-off-by: default avatarSonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Linus Walleij's avatarLinus Walleij <linus.walleij@linaro.org>
parent 272b98c6
...@@ -49,6 +49,23 @@ config PINCTRL_AB8505 ...@@ -49,6 +49,23 @@ config PINCTRL_AB8505
bool "AB8505 pin controller driver" bool "AB8505 pin controller driver"
depends on PINCTRL_ABX500 && ARCH_U8500 depends on PINCTRL_ABX500 && ARCH_U8500
config PINCTRL_ADI2
bool "ADI pin controller driver"
select PINMUX
select IRQ_DOMAIN
help
This is the pin controller and gpio driver for ADI BF54x, BF60x and
future processors. This option is selected automatically when specific
machine and arch are selected to build.
config PINCTRL_BF54x
def_bool y if BF54x
select PINCTRL_ADI2
config PINCTRL_BF60x
def_bool y if BF60x
select PINCTRL_ADI2
config PINCTRL_AT91 config PINCTRL_AT91
bool "AT91 pinctrl driver" bool "AT91 pinctrl driver"
depends on OF depends on OF
......
...@@ -14,6 +14,9 @@ obj-$(CONFIG_PINCTRL_AB8500) += pinctrl-ab8500.o ...@@ -14,6 +14,9 @@ obj-$(CONFIG_PINCTRL_AB8500) += pinctrl-ab8500.o
obj-$(CONFIG_PINCTRL_AB8540) += pinctrl-ab8540.o obj-$(CONFIG_PINCTRL_AB8540) += pinctrl-ab8540.o
obj-$(CONFIG_PINCTRL_AB9540) += pinctrl-ab9540.o obj-$(CONFIG_PINCTRL_AB9540) += pinctrl-ab9540.o
obj-$(CONFIG_PINCTRL_AB8505) += pinctrl-ab8505.o obj-$(CONFIG_PINCTRL_AB8505) += pinctrl-ab8505.o
obj-$(CONFIG_PINCTRL_ADI2) += pinctrl-adi2.o
obj-$(CONFIG_PINCTRL_BF54x) += pinctrl-adi2-bf54x.o
obj-$(CONFIG_PINCTRL_BF60x) += pinctrl-adi2-bf60x.o
obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o
obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o
obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o
......
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/*
* Pinctrl Driver for ADI GPIO2 controller
*
* Copyright 2007-2013 Analog Devices Inc.
*
* Licensed under the GPLv2 or later
*/
#ifndef PINCTRL_PINCTRL_ADI2_H
#define PINCTRL_PINCTRL_ADI2_H
#include <linux/pinctrl/pinctrl.h>
/**
* struct adi_pin_group - describes a pin group
* @name: the name of this pin group
* @pins: an array of pins
* @num: the number of pins in this array
*/
struct adi_pin_group {
const char *name;
const unsigned *pins;
const unsigned num;
};
#define ADI_PIN_GROUP(n, p) \
{ \
.name = n, \
.pins = p, \
.num = ARRAY_SIZE(p), \
}
/**
* struct adi_pmx_func - describes function mux setting of pin groups
* @name: the name of this function mux setting
* @groups: an array of pin groups
* @num_groups: the number of pin groups in this array
* @mux: the function mux setting array, end by zero
*/
struct adi_pmx_func {
const char *name;
const char * const *groups;
const unsigned num_groups;
const unsigned short *mux;
};
#define ADI_PMX_FUNCTION(n, g, m) \
{ \
.name = n, \
.groups = g, \
.num_groups = ARRAY_SIZE(g), \
.mux = m, \
}
/**
* struct adi_pinctrl_soc_data - ADI pin controller per-SoC configuration
* @functions: The functions supported on this SoC.
* @nfunction: The number of entries in @functions.
* @groups: An array describing all pin groups the pin SoC supports.
* @ngroups: The number of entries in @groups.
* @pins: An array describing all pins the pin controller affects.
* @npins: The number of entries in @pins.
*/
struct adi_pinctrl_soc_data {
const struct adi_pmx_func *functions;
int nfunctions;
const struct adi_pin_group *groups;
int ngroups;
const struct pinctrl_pin_desc *pins;
int npins;
};
void adi_pinctrl_soc_init(const struct adi_pinctrl_soc_data **soc);
#endif /* PINCTRL_PINCTRL_ADI2_H */
/*
* Pinctrl Driver for ADI GPIO2 controller
*
* Copyright 2007-2013 Analog Devices Inc.
*
* Licensed under the GPLv2 or later
*/
#ifndef PINCTRL_ADI2_H
#define PINCTRL_ADI2_H
#include <linux/io.h>
#include <linux/platform_device.h>
/**
* struct adi_pinctrl_gpio_platform_data - Pinctrl gpio platform data
* for ADI GPIO2 device.
*
* @port_gpio_base: Optional global GPIO index of the GPIO bank.
* 0 means driver decides.
* @port_pin_base: Pin index of the pin controller device.
* @port_width: PIN number of the GPIO bank device
* @pint_id: GPIO PINT device id that this GPIO bank should map to.
* @pint_assign: The 32-bit GPIO PINT registers can be divided into 2 parts. A
* GPIO bank can be mapped into either low 16 bits[0] or high 16
* bits[1] of each PINT register.
* @pint_map: GIOP bank mapping code in PINT device
*/
struct adi_pinctrl_gpio_platform_data {
unsigned int port_gpio_base;
unsigned int port_pin_base;
unsigned int port_width;
u8 pinctrl_id;
u8 pint_id;
bool pint_assign;
u8 pint_map;
};
#endif
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