Commit d5025f9f authored by James Hogan's avatar James Hogan Committed by Linus Walleij

pinctrl-tz1090: add TZ1090 pinctrl driver

Add a pin control driver for the main pins on the TZ1090 SoC. This
doesn't include the low-power pins as they're controlled separately via
the Powerdown Controller (PDC) registers.
Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Rob Landley <rob@landley.net>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-doc@vger.kernel.org
Cc: devicetree-discuss@lists.ozlabs.org
Signed-off-by: Linus Walleij's avatarLinus Walleij <linus.walleij@linaro.org>
parent b9408975
ImgTec TZ1090 pin controller
Required properties:
- compatible: "img,tz1090-pinctrl"
- reg: Should contain the register physical address and length of the pad
configuration registers (CR_PADS_* and CR_IF_CTL0).
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
TZ1090's pin configuration nodes act as a container for an abitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function. For this reason, even seemingly boolean
values are actually tristates in this binding: unspecified, off, or on.
Unspecified is represented as an absent property, and off/on are represented as
integer values 0 and 1.
Required subnode-properties:
- tz1090,pins : An array of strings. Each string contains the name of a pin or
group. Valid values for these names are listed below.
Optional subnode-properties:
- tz1090,function: A string containing the name of the function to mux to the
pin or group. Valid values for function names are listed below, including
which pingroups can be muxed to them.
- supported generic pinconfig properties (for further details see
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt):
- bias-disable
- bias-high-impedance
- bias-bus-hold
- bias-pull-up
- bias-pull-down
- input-schmitt-enable
- input-schmitt-disable
- slew-rate: Integer, control slew rate of pins.
0: slow (half frequency)
1: fast
- drive-strength: Integer, control drive strength of pins in mA.
2: 2mA
4: 4mA
8: 8mA
12: 12mA
Note that many of these properties are only valid for certain specific pins
or groups. See the TZ1090 TRM for complete details regarding which groups
support which functionality. The Linux pinctrl driver may also be a useful
reference.
Valid values for pin and group names are:
gpio pins:
These all support bias-high-impediance, bias-pull-up, bias-pull-down, and
bias-bus-hold (which can also be provided to any of the groups below to set
it for all pins in that group).
They also all support the some form of muxing. Any pins which are contained
in one of the mux groups (see below) can be muxed only to the functions
supported by the mux group. All other pins can be muxed to the "perip"
function which which enables them with their intended peripheral.
Different pins in the same mux group cannot be muxed to different functions,
however it is possible to mux only a subset of the pins in a mux group to a
particular function and leave the remaining pins unmuxed. This is useful if
the board connects certain pins in a group to other devices to be controlled
by GPIO, and you don't want the usual peripheral to have any control of the
pin.
ant_sel0, ant_sel1, gain0, gain1, gain2, gain3, gain4, gain5, gain6, gain7,
i2s_bclk_out, i2s_din, i2s_dout0, i2s_dout1, i2s_dout2, i2s_lrclk_out,
i2s_mclk, pa_on, pdm_a, pdm_b, pdm_c, pdm_d, pll_on, rx_hp, rx_on,
scb0_sclk, scb0_sdat, scb1_sclk, scb1_sdat, scb2_sclk, scb2_sdat, sdh_cd,
sdh_clk_in, sdh_wp, sdio_clk, sdio_cmd, sdio_d0, sdio_d1, sdio_d2, sdio_d3,
spi0_cs0, spi0_cs1, spi0_cs2, spi0_din, spi0_dout, spi0_mclk, spi1_cs0,
spi1_cs1, spi1_cs2, spi1_din, spi1_dout, spi1_mclk, tft_blank_ls, tft_blue0,
tft_blue1, tft_blue2, tft_blue3, tft_blue4, tft_blue5, tft_blue6, tft_blue7,
tft_green0, tft_green1, tft_green2, tft_green3, tft_green4, tft_green5,
tft_green6, tft_green7, tft_hsync_nr, tft_panelclk, tft_pwrsave, tft_red0,
tft_red1, tft_red2, tft_red3, tft_red4, tft_red5, tft_red6, tft_red7,
tft_vd12acb, tft_vdden_gd, tft_vsync_ns, tx_on, uart0_cts, uart0_rts,
uart0_rxd, uart0_txd, uart1_rxd, uart1_txd.
bias-high-impediance: supported.
bias-pull-up: supported.
bias-pull-down: supported.
bias-bus-hold: supported.
function: perip or those supported by pin's mux group.
other pins:
These other pins are part of various pin groups below, but can't be
controlled as GPIOs. They do however support bias-high-impediance,
bias-pull-up, bias-pull-down, and bias-bus-hold (which can also be provided
to any of the groups below to set it for all pins in that group).
clk_out0, clk_out1, tck, tdi, tdo, tms, trst.
bias-high-impediance: supported.
bias-pull-up: supported.
bias-pull-down: supported.
bias-bus-hold: supported.
mux groups:
These all support function, and some support drive configs.
afe
pins: tx_on, rx_on, pll_on, pa_on, rx_hp, ant_sel0,
ant_sel1, gain0, gain1, gain2, gain3, gain4,
gain5, gain6, gain7.
function: afe, ts_out_0.
input-schmitt-enable: supported.
input-schmitt-disable: supported.
slew-rate: supported.
drive-strength: supported.
pdm_d
pins: pdm_d.
function: pdm_dac, usb_vbus.
sdh
pins: sdh_cd, sdh_wp, sdh_clk_in.
function: sdh, sdio.
sdio
pins: sdio_clk, sdio_cmd, sdio_d0, sdio_d1, sdio_d2,
sdio_d3.
function: sdio, sdh.
spi1_cs2
pins: spi1_cs2.
function: spi1_cs2, usb_vbus.
tft
pins: tft_red0, tft_red1, tft_red2, tft_red3,
tft_red4, tft_red5, tft_red6, tft_red7,
tft_green0, tft_green1, tft_green2, tft_green3,
tft_green4, tft_green5, tft_green6, tft_green7,
tft_blue0, tft_blue1, tft_blue2, tft_blue3,
tft_blue4, tft_blue5, tft_blue6, tft_blue7,
tft_vdden_gd, tft_panelclk, tft_blank_ls,
tft_vsync_ns, tft_hsync_nr, tft_vd12acb,
tft_pwrsave.
function: tft, ext_dac, not_iqadc_stb, iqdac_stb, ts_out_1,
lcd_trace, phy_ringosc.
input-schmitt-enable: supported.
input-schmitt-disable: supported.
slew-rate: supported.
drive-strength: supported.
drive groups:
These all support input-schmitt-enable, input-schmitt-disable, slew-rate,
and drive-strength.
jtag
pins: tck, trst, tdi, tdo, tms.
scb1
pins: scb1_sdat, scb1_sclk.
scb2
pins: scb2_sdat, scb2_sclk.
spi0
pins: spi0_mclk, spi0_cs0, spi0_cs1, spi0_cs2, spi0_dout, spi0_din.
spi1
pins: spi1_mclk, spi1_cs0, spi1_cs1, spi1_cs2, spi1_dout, spi1_din.
uart
pins: uart0_txd, uart0_rxd, uart0_rts, uart0_cts,
uart1_txd, uart1_rxd.
drive_i2s
pins: clk_out1, i2s_din, i2s_dout0, i2s_dout1, i2s_dout2,
i2s_lrclk_out, i2s_bclk_out, i2s_mclk.
drive_pdm
pins: clk_out0, pdm_b, pdm_a.
drive_scb0
pins: scb0_sclk, scb0_sdat, pdm_d, pdm_c.
drive_sdio
pins: sdio_clk, sdio_cmd, sdio_d0, sdio_d1, sdio_d2, sdio_d3,
sdh_wp, sdh_cd, sdh_clk_in.
convenience groups:
These are just convenient groupings of pins and don't support any drive
configs.
uart0
pins: uart0_cts, uart0_rts, uart0_rxd, uart0_txd.
uart1
pins: uart1_rxd, uart1_txd.
scb0
pins: scb0_sclk, scb0_sdat.
i2s
pins: i2s_bclk_out, i2s_din, i2s_dout0, i2s_dout1, i2s_dout2,
i2s_lrclk_out, i2s_mclk.
Example:
pinctrl: pinctrl@02005800 {
#gpio-range-cells = <3>;
compatible = "img,tz1090-pinctrl";
reg = <0x02005800 0xe4>;
};
Example board file extract:
&pinctrl {
uart0_default: uart0 {
uart0_cfg {
tz1090,pins = "uart0_rxd",
"uart0_txd";
tz1090,function = "perip";
};
};
tft_default: tft {
tft_cfg {
tz1090,pins = "tft";
tz1090,function = "tft";
};
};
};
uart@02004b00 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_default>;
};
......@@ -212,6 +212,12 @@ config PINCTRL_TEGRA114
bool
select PINCTRL_TEGRA
config PINCTRL_TZ1090
bool "Toumaz Xenif TZ1090 pin control driver"
depends on SOC_TZ1090
select PINMUX
select GENERIC_PINCONF
config PINCTRL_U300
bool "U300 pin controller driver"
depends on ARCH_U300
......
......@@ -40,6 +40,7 @@ obj-$(CONFIG_PINCTRL_TEGRA) += pinctrl-tegra.o
obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o
obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o
obj-$(CONFIG_PINCTRL_TEGRA114) += pinctrl-tegra114.o
obj-$(CONFIG_PINCTRL_TZ1090) += pinctrl-tz1090.o
obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o
obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o
obj-$(CONFIG_PINCTRL_SAMSUNG) += pinctrl-samsung.o
......
/*
* Pinctrl driver for the Toumaz Xenif TZ1090 SoC
*
* Copyright (c) 2013, Imagination Technologies Ltd.
*
* Derived from Tegra code:
* Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
*
* Derived from code:
* Copyright (C) 2010 Google, Inc.
* Copyright (C) 2010 NVIDIA Corporation
* Copyright (C) 2009-2011 ST-Ericsson AB
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#include <linux/bitops.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
/*
* The registers may be shared with other threads/cores, so we need to use the
* metag global lock2 for atomicity.
*/
#include <asm/global_lock.h>
#include "core.h"
#include "pinconf.h"
/* Register offsets from bank base address */
#define REG_PINCTRL_SELECT 0x10
#define REG_PINCTRL_SCHMITT 0x90
#define REG_PINCTRL_PU_PD 0xa0
#define REG_PINCTRL_SR 0xc0
#define REG_PINCTRL_DR 0xd0
#define REG_PINCTRL_IF_CTL 0xe0
/* REG_PINCTRL_PU_PD field values */
#define REG_PU_PD_TRISTATE 0
#define REG_PU_PD_UP 1
#define REG_PU_PD_DOWN 2
#define REG_PU_PD_REPEATER 3
/* REG_PINCTRL_DR field values */
#define REG_DR_2mA 0
#define REG_DR_4mA 1
#define REG_DR_8mA 2
#define REG_DR_12mA 3
/**
* struct tz1090_function - TZ1090 pinctrl mux function
* @name: The name of the function, exported to pinctrl core.
* @groups: An array of pin groups that may select this function.
* @ngroups: The number of entries in @groups.
*/
struct tz1090_function {
const char *name;
const char * const *groups;
unsigned int ngroups;
};
/**
* struct tz1090_muxdesc - TZ1090 individual mux description
* @funcs: Function for each mux value.
* @reg: Mux register offset. 0 if unsupported.
* @bit: Mux register bit. 0 if unsupported.
* @width: Mux field width. 0 if unsupported.
*
* A representation of a group of signals (possibly just one signal) in the
* TZ1090 which can be muxed to a set of functions or sub muxes.
*/
struct tz1090_muxdesc {
int funcs[5];
u16 reg;
u8 bit;
u8 width;
};
/**
* struct tz1090_pingroup - TZ1090 pin group
* @name: Name of pin group.
* @pins: Array of pin numbers in this pin group.
* @npins: Number of pins in this pin group.
* @mux: Top level mux.
* @drv: Drive control supported, 0 if unsupported.
* This means Schmitt, Slew, and Drive strength.
* @slw_bit: Slew register bit. 0 if unsupported.
* The same bit is used for Schmitt, and Drive (*2).
* @func: Currently muxed function.
* @func_count: Number of pins using current mux function.
*
* A representation of a group of pins (possibly just one pin) in the TZ1090
* pin controller. Each group allows some parameter or parameters to be
* configured. The most common is mux function selection.
*/
struct tz1090_pingroup {
const char *name;
const unsigned int *pins;
unsigned int npins;
struct tz1090_muxdesc mux;
bool drv;
u8 slw_bit;
int func;
unsigned int func_count;
};
/*
* Most pins affected by the pinmux can also be GPIOs. Define these first.
* These must match how the GPIO driver names/numbers its pins.
*/
enum tz1090_pin {
/* GPIO pins */
TZ1090_PIN_SDIO_CLK,
TZ1090_PIN_SDIO_CMD,
TZ1090_PIN_SDIO_D0,
TZ1090_PIN_SDIO_D1,
TZ1090_PIN_SDIO_D2,
TZ1090_PIN_SDIO_D3,
TZ1090_PIN_SDH_CD,
TZ1090_PIN_SDH_WP,
TZ1090_PIN_SPI0_MCLK,
TZ1090_PIN_SPI0_CS0,
TZ1090_PIN_SPI0_CS1,
TZ1090_PIN_SPI0_CS2,
TZ1090_PIN_SPI0_DOUT,
TZ1090_PIN_SPI0_DIN,
TZ1090_PIN_SPI1_MCLK,
TZ1090_PIN_SPI1_CS0,
TZ1090_PIN_SPI1_CS1,
TZ1090_PIN_SPI1_CS2,
TZ1090_PIN_SPI1_DOUT,
TZ1090_PIN_SPI1_DIN,
TZ1090_PIN_UART0_RXD,
TZ1090_PIN_UART0_TXD,
TZ1090_PIN_UART0_CTS,
TZ1090_PIN_UART0_RTS,
TZ1090_PIN_UART1_RXD,
TZ1090_PIN_UART1_TXD,
TZ1090_PIN_SCB0_SDAT,
TZ1090_PIN_SCB0_SCLK,
TZ1090_PIN_SCB1_SDAT,
TZ1090_PIN_SCB1_SCLK,
TZ1090_PIN_SCB2_SDAT,
TZ1090_PIN_SCB2_SCLK,
TZ1090_PIN_I2S_MCLK,
TZ1090_PIN_I2S_BCLK_OUT,
TZ1090_PIN_I2S_LRCLK_OUT,
TZ1090_PIN_I2S_DOUT0,
TZ1090_PIN_I2S_DOUT1,
TZ1090_PIN_I2S_DOUT2,
TZ1090_PIN_I2S_DIN,
TZ1090_PIN_PDM_A,
TZ1090_PIN_PDM_B,
TZ1090_PIN_PDM_C,
TZ1090_PIN_PDM_D,
TZ1090_PIN_TFT_RED0,
TZ1090_PIN_TFT_RED1,
TZ1090_PIN_TFT_RED2,
TZ1090_PIN_TFT_RED3,
TZ1090_PIN_TFT_RED4,
TZ1090_PIN_TFT_RED5,
TZ1090_PIN_TFT_RED6,
TZ1090_PIN_TFT_RED7,
TZ1090_PIN_TFT_GREEN0,
TZ1090_PIN_TFT_GREEN1,
TZ1090_PIN_TFT_GREEN2,
TZ1090_PIN_TFT_GREEN3,
TZ1090_PIN_TFT_GREEN4,
TZ1090_PIN_TFT_GREEN5,
TZ1090_PIN_TFT_GREEN6,
TZ1090_PIN_TFT_GREEN7,
TZ1090_PIN_TFT_BLUE0,
TZ1090_PIN_TFT_BLUE1,
TZ1090_PIN_TFT_BLUE2,
TZ1090_PIN_TFT_BLUE3,
TZ1090_PIN_TFT_BLUE4,
TZ1090_PIN_TFT_BLUE5,
TZ1090_PIN_TFT_BLUE6,
TZ1090_PIN_TFT_BLUE7,
TZ1090_PIN_TFT_VDDEN_GD,
TZ1090_PIN_TFT_PANELCLK,
TZ1090_PIN_TFT_BLANK_LS,
TZ1090_PIN_TFT_VSYNC_NS,
TZ1090_PIN_TFT_HSYNC_NR,
TZ1090_PIN_TFT_VD12ACB,
TZ1090_PIN_TFT_PWRSAVE,
TZ1090_PIN_TX_ON,
TZ1090_PIN_RX_ON,
TZ1090_PIN_PLL_ON,
TZ1090_PIN_PA_ON,
TZ1090_PIN_RX_HP,
TZ1090_PIN_GAIN0,
TZ1090_PIN_GAIN1,
TZ1090_PIN_GAIN2,
TZ1090_PIN_GAIN3,
TZ1090_PIN_GAIN4,
TZ1090_PIN_GAIN5,
TZ1090_PIN_GAIN6,
TZ1090_PIN_GAIN7,
TZ1090_PIN_ANT_SEL0,
TZ1090_PIN_ANT_SEL1,
TZ1090_PIN_SDH_CLK_IN,
/* Non-GPIO pins */
TZ1090_PIN_TCK,
TZ1090_PIN_TRST,
TZ1090_PIN_TDI,
TZ1090_PIN_TDO,
TZ1090_PIN_TMS,
TZ1090_PIN_CLK_OUT0,
TZ1090_PIN_CLK_OUT1,
NUM_GPIOS = TZ1090_PIN_TCK,
};
/* Pin names */
static const struct pinctrl_pin_desc tz1090_pins[] = {
/* GPIO pins */
PINCTRL_PIN(TZ1090_PIN_SDIO_CLK, "sdio_clk"),
PINCTRL_PIN(TZ1090_PIN_SDIO_CMD, "sdio_cmd"),
PINCTRL_PIN(TZ1090_PIN_SDIO_D0, "sdio_d0"),
PINCTRL_PIN(TZ1090_PIN_SDIO_D1, "sdio_d1"),
PINCTRL_PIN(TZ1090_PIN_SDIO_D2, "sdio_d2"),
PINCTRL_PIN(TZ1090_PIN_SDIO_D3, "sdio_d3"),
PINCTRL_PIN(TZ1090_PIN_SDH_CD, "sdh_cd"),
PINCTRL_PIN(TZ1090_PIN_SDH_WP, "sdh_wp"),
PINCTRL_PIN(TZ1090_PIN_SPI0_MCLK, "spi0_mclk"),
PINCTRL_PIN(TZ1090_PIN_SPI0_CS0, "spi0_cs0"),
PINCTRL_PIN(TZ1090_PIN_SPI0_CS1, "spi0_cs1"),
PINCTRL_PIN(TZ1090_PIN_SPI0_CS2, "spi0_cs2"),
PINCTRL_PIN(TZ1090_PIN_SPI0_DOUT, "spi0_dout"),
PINCTRL_PIN(TZ1090_PIN_SPI0_DIN, "spi0_din"),
PINCTRL_PIN(TZ1090_PIN_SPI1_MCLK, "spi1_mclk"),
PINCTRL_PIN(TZ1090_PIN_SPI1_CS0, "spi1_cs0"),
PINCTRL_PIN(TZ1090_PIN_SPI1_CS1, "spi1_cs1"),
PINCTRL_PIN(TZ1090_PIN_SPI1_CS2, "spi1_cs2"),
PINCTRL_PIN(TZ1090_PIN_SPI1_DOUT, "spi1_dout"),
PINCTRL_PIN(TZ1090_PIN_SPI1_DIN, "spi1_din"),
PINCTRL_PIN(TZ1090_PIN_UART0_RXD, "uart0_rxd"),
PINCTRL_PIN(TZ1090_PIN_UART0_TXD, "uart0_txd"),
PINCTRL_PIN(TZ1090_PIN_UART0_CTS, "uart0_cts"),
PINCTRL_PIN(TZ1090_PIN_UART0_RTS, "uart0_rts"),
PINCTRL_PIN(TZ1090_PIN_UART1_RXD, "uart1_rxd"),
PINCTRL_PIN(TZ1090_PIN_UART1_TXD, "uart1_txd"),
PINCTRL_PIN(TZ1090_PIN_SCB0_SDAT, "scb0_sdat"),
PINCTRL_PIN(TZ1090_PIN_SCB0_SCLK, "scb0_sclk"),
PINCTRL_PIN(TZ1090_PIN_SCB1_SDAT, "scb1_sdat"),
PINCTRL_PIN(TZ1090_PIN_SCB1_SCLK, "scb1_sclk"),
PINCTRL_PIN(TZ1090_PIN_SCB2_SDAT, "scb2_sdat"),
PINCTRL_PIN(TZ1090_PIN_SCB2_SCLK, "scb2_sclk"),
PINCTRL_PIN(TZ1090_PIN_I2S_MCLK, "i2s_mclk"),
PINCTRL_PIN(TZ1090_PIN_I2S_BCLK_OUT, "i2s_bclk_out"),
PINCTRL_PIN(TZ1090_PIN_I2S_LRCLK_OUT, "i2s_lrclk_out"),
PINCTRL_PIN(TZ1090_PIN_I2S_DOUT0, "i2s_dout0"),
PINCTRL_PIN(TZ1090_PIN_I2S_DOUT1, "i2s_dout1"),
PINCTRL_PIN(TZ1090_PIN_I2S_DOUT2, "i2s_dout2"),
PINCTRL_PIN(TZ1090_PIN_I2S_DIN, "i2s_din"),
PINCTRL_PIN(TZ1090_PIN_PDM_A, "pdm_a"),
PINCTRL_PIN(TZ1090_PIN_PDM_B, "pdm_b"),
PINCTRL_PIN(TZ1090_PIN_PDM_C, "pdm_c"),
PINCTRL_PIN(TZ1090_PIN_PDM_D, "pdm_d"),
PINCTRL_PIN(TZ1090_PIN_TFT_RED0, "tft_red0"),
PINCTRL_PIN(TZ1090_PIN_TFT_RED1, "tft_red1"),
PINCTRL_PIN(TZ1090_PIN_TFT_RED2, "tft_red2"),
PINCTRL_PIN(TZ1090_PIN_TFT_RED3, "tft_red3"),
PINCTRL_PIN(TZ1090_PIN_TFT_RED4, "tft_red4"),
PINCTRL_PIN(TZ1090_PIN_TFT_RED5, "tft_red5"),
PINCTRL_PIN(TZ1090_PIN_TFT_RED6, "tft_red6"),
PINCTRL_PIN(TZ1090_PIN_TFT_RED7, "tft_red7"),
PINCTRL_PIN(TZ1090_PIN_TFT_GREEN0, "tft_green0"),
PINCTRL_PIN(TZ1090_PIN_TFT_GREEN1, "tft_green1"),
PINCTRL_PIN(TZ1090_PIN_TFT_GREEN2, "tft_green2"),
PINCTRL_PIN(TZ1090_PIN_TFT_GREEN3, "tft_green3"),
PINCTRL_PIN(TZ1090_PIN_TFT_GREEN4, "tft_green4"),
PINCTRL_PIN(TZ1090_PIN_TFT_GREEN5, "tft_green5"),
PINCTRL_PIN(TZ1090_PIN_TFT_GREEN6, "tft_green6"),
PINCTRL_PIN(TZ1090_PIN_TFT_GREEN7, "tft_green7"),
PINCTRL_PIN(TZ1090_PIN_TFT_BLUE0, "tft_blue0"),
PINCTRL_PIN(TZ1090_PIN_TFT_BLUE1, "tft_blue1"),
PINCTRL_PIN(TZ1090_PIN_TFT_BLUE2, "tft_blue2"),
PINCTRL_PIN(TZ1090_PIN_TFT_BLUE3, "tft_blue3"),
PINCTRL_PIN(TZ1090_PIN_TFT_BLUE4, "tft_blue4"),
PINCTRL_PIN(TZ1090_PIN_TFT_BLUE5, "tft_blue5"),
PINCTRL_PIN(TZ1090_PIN_TFT_BLUE6, "tft_blue6"),
PINCTRL_PIN(TZ1090_PIN_TFT_BLUE7, "tft_blue7"),
PINCTRL_PIN(TZ1090_PIN_TFT_VDDEN_GD, "tft_vdden_gd"),
PINCTRL_PIN(TZ1090_PIN_TFT_PANELCLK, "tft_panelclk"),
PINCTRL_PIN(TZ1090_PIN_TFT_BLANK_LS, "tft_blank_ls"),
PINCTRL_PIN(TZ1090_PIN_TFT_VSYNC_NS, "tft_vsync_ns"),
PINCTRL_PIN(TZ1090_PIN_TFT_HSYNC_NR, "tft_hsync_nr"),
PINCTRL_PIN(TZ1090_PIN_TFT_VD12ACB, "tft_vd12acb"),
PINCTRL_PIN(TZ1090_PIN_TFT_PWRSAVE, "tft_pwrsave"),
PINCTRL_PIN(TZ1090_PIN_TX_ON, "tx_on"),
PINCTRL_PIN(TZ1090_PIN_RX_ON, "rx_on"),
PINCTRL_PIN(TZ1090_PIN_PLL_ON, "pll_on"),
PINCTRL_PIN(TZ1090_PIN_PA_ON, "pa_on"),
PINCTRL_PIN(TZ1090_PIN_RX_HP, "rx_hp"),
PINCTRL_PIN(TZ1090_PIN_GAIN0, "gain0"),
PINCTRL_PIN(TZ1090_PIN_GAIN1, "gain1"),
PINCTRL_PIN(TZ1090_PIN_GAIN2, "gain2"),
PINCTRL_PIN(TZ1090_PIN_GAIN3, "gain3"),
PINCTRL_PIN(TZ1090_PIN_GAIN4, "gain4"),
PINCTRL_PIN(TZ1090_PIN_GAIN5, "gain5"),
PINCTRL_PIN(TZ1090_PIN_GAIN6, "gain6"),
PINCTRL_PIN(TZ1090_PIN_GAIN7, "gain7"),
PINCTRL_PIN(TZ1090_PIN_ANT_SEL0, "ant_sel0"),
PINCTRL_PIN(TZ1090_PIN_ANT_SEL1, "ant_sel1"),
PINCTRL_PIN(TZ1090_PIN_SDH_CLK_IN, "sdh_clk_in"),
/* Non-GPIO pins */
PINCTRL_PIN(TZ1090_PIN_TCK, "tck"),
PINCTRL_PIN(TZ1090_PIN_TRST, "trst"),
PINCTRL_PIN(TZ1090_PIN_TDI, "tdi"),
PINCTRL_PIN(TZ1090_PIN_TDO, "tdo"),
PINCTRL_PIN(TZ1090_PIN_TMS, "tms"),
PINCTRL_PIN(TZ1090_PIN_CLK_OUT0, "clk_out0"),
PINCTRL_PIN(TZ1090_PIN_CLK_OUT1, "clk_out1"),
};
/* Pins in each pin group */
static const unsigned int spi1_cs2_pins[] = {
TZ1090_PIN_SPI1_CS2,
};
static const unsigned int pdm_d_pins[] = {
TZ1090_PIN_PDM_D,
};
static const unsigned int tft_pins[] = {
TZ1090_PIN_TFT_RED0,
TZ1090_PIN_TFT_RED1,
TZ1090_PIN_TFT_RED2,
TZ1090_PIN_TFT_RED3,
TZ1090_PIN_TFT_RED4,
TZ1090_PIN_TFT_RED5,
TZ1090_PIN_TFT_RED6,
TZ1090_PIN_TFT_RED7,
TZ1090_PIN_TFT_GREEN0,
TZ1090_PIN_TFT_GREEN1,
TZ1090_PIN_TFT_GREEN2,
TZ1090_PIN_TFT_GREEN3,
TZ1090_PIN_TFT_GREEN4,
TZ1090_PIN_TFT_GREEN5,
TZ1090_PIN_TFT_GREEN6,
TZ1090_PIN_TFT_GREEN7,
TZ1090_PIN_TFT_BLUE0,
TZ1090_PIN_TFT_BLUE1,
TZ1090_PIN_TFT_BLUE2,
TZ1090_PIN_TFT_BLUE3,
TZ1090_PIN_TFT_BLUE4,
TZ1090_PIN_TFT_BLUE5,
TZ1090_PIN_TFT_BLUE6,
TZ1090_PIN_TFT_BLUE7,
TZ1090_PIN_TFT_VDDEN_GD,
TZ1090_PIN_TFT_PANELCLK,
TZ1090_PIN_TFT_BLANK_LS,
TZ1090_PIN_TFT_VSYNC_NS,
TZ1090_PIN_TFT_HSYNC_NR,
TZ1090_PIN_TFT_VD12ACB,
TZ1090_PIN_TFT_PWRSAVE,
};
static const unsigned int afe_pins[] = {
TZ1090_PIN_TX_ON,
TZ1090_PIN_RX_ON,
TZ1090_PIN_PLL_ON,
TZ1090_PIN_PA_ON,
TZ1090_PIN_RX_HP,
TZ1090_PIN_ANT_SEL0,
TZ1090_PIN_ANT_SEL1,
TZ1090_PIN_GAIN0,
TZ1090_PIN_GAIN1,
TZ1090_PIN_GAIN2,
TZ1090_PIN_GAIN3,
TZ1090_PIN_GAIN4,