Commit c19b6d24 authored by Zhao Qiang's avatar Zhao Qiang Committed by David S. Miller
Browse files

drivers/net: support hdlc function for QE-UCC



The driver add hdlc support for Freescale QUICC Engine.
It support NMSI and TSA mode.
Signed-off-by: default avatarZhao Qiang <qiang.zhao@nxp.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 35ef1c20
......@@ -4870,6 +4870,13 @@ F: drivers/net/ethernet/freescale/gianfar*
X: drivers/net/ethernet/freescale/gianfar_ptp.c
F: Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
FREESCALE QUICC ENGINE UCC HDLC DRIVER
M: Zhao Qiang <qiang.zhao@nxp.com>
L: netdev@vger.kernel.org
L: linuxppc-dev@lists.ozlabs.org
S: Maintained
F: drivers/net/wan/fsl_ucc_hdlc*
FREESCALE QUICC ENGINE UCC UART DRIVER
M: Timur Tabi <timur@tabi.org>
L: linuxppc-dev@lists.ozlabs.org
......
......@@ -280,6 +280,17 @@ config DSCC4
To compile this driver as a module, choose M here: the
module will be called dscc4.
config FSL_UCC_HDLC
tristate "Freescale QUICC Engine HDLC support"
depends on HDLC
depends on QUICC_ENGINE
help
Driver for Freescale QUICC Engine HDLC controller. The driver
supports HDLC in NMSI and TDM mode.
To compile this driver as a module, choose M here: the
module will be called fsl_ucc_hdlc.
config DSCC4_PCISYNC
bool "Etinc PCISYNC features"
depends on DSCC4
......
......@@ -32,6 +32,7 @@ obj-$(CONFIG_WANXL) += wanxl.o
obj-$(CONFIG_PCI200SYN) += pci200syn.o
obj-$(CONFIG_PC300TOO) += pc300too.o
obj-$(CONFIG_IXP4XX_HSS) += ixp4xx_hss.o
obj-$(CONFIG_FSL_UCC_HDLC) += fsl_ucc_hdlc.o
clean-files := wanxlfw.inc
$(obj)/wanxl.o: $(obj)/wanxlfw.inc
......
This diff is collapsed.
/* Freescale QUICC Engine HDLC Device Driver
*
* Copyright 2014 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef CONFIG_UCC_HDLC_H
#define CONFIG_UCC_HDLC_H
#include <linux/kernel.h>
#include <linux/list.h>
#include <soc/fsl/qe/immap_qe.h>
#include <soc/fsl/qe/qe.h>
#include <soc/fsl/qe/ucc.h>
#include <soc/fsl/qe/ucc_fast.h>
/* UCC HDLC event register */
#define UCCE_HDLC_RX_EVENTS \
(UCC_HDLC_UCCE_RXF | UCC_HDLC_UCCE_RXB | UCC_HDLC_UCCE_BSY)
#define UCCE_HDLC_TX_EVENTS (UCC_HDLC_UCCE_TXB | UCC_HDLC_UCCE_TXE)
struct ucc_hdlc_param {
__be16 riptr;
__be16 tiptr;
__be16 res0;
__be16 mrblr;
__be32 rstate;
__be32 rbase;
__be16 rbdstat;
__be16 rbdlen;
__be32 rdptr;
__be32 tstate;
__be32 tbase;
__be16 tbdstat;
__be16 tbdlen;
__be32 tdptr;
__be32 rbptr;
__be32 tbptr;
__be32 rcrc;
__be32 res1;
__be32 tcrc;
__be32 res2;
__be32 res3;
__be32 c_mask;
__be32 c_pres;
__be16 disfc;
__be16 crcec;
__be16 abtsc;
__be16 nmarc;
__be32 max_cnt;
__be16 mflr;
__be16 rfthr;
__be16 rfcnt;
__be16 hmask;
__be16 haddr1;
__be16 haddr2;
__be16 haddr3;
__be16 haddr4;
__be16 ts_tmp;
__be16 tmp_mb;
};
struct ucc_hdlc_private {
struct ucc_tdm *utdm;
struct ucc_tdm_info *ut_info;
struct ucc_fast_private *uccf;
struct device *dev;
struct net_device *ndev;
struct napi_struct napi;
struct ucc_fast __iomem *uf_regs; /* UCC Fast registers */
struct ucc_hdlc_param __iomem *ucc_pram;
u16 tsa;
bool hdlc_busy;
bool loopback;
u8 *tx_buffer;
u8 *rx_buffer;
dma_addr_t dma_tx_addr;
dma_addr_t dma_rx_addr;
struct qe_bd *tx_bd_base;
struct qe_bd *rx_bd_base;
dma_addr_t dma_tx_bd;
dma_addr_t dma_rx_bd;
struct qe_bd *curtx_bd;
struct qe_bd *currx_bd;
struct qe_bd *dirty_tx;
u16 currx_bdnum;
struct sk_buff **tx_skbuff;
struct sk_buff **rx_skbuff;
u16 skb_curtx;
u16 skb_currx;
unsigned short skb_dirtytx;
unsigned short tx_ring_size;
unsigned short rx_ring_size;
u32 ucc_pram_offset;
unsigned short encoding;
unsigned short parity;
u32 clocking;
spinlock_t lock; /* lock for Tx BD and Tx buffer */
#ifdef CONFIG_PM
struct ucc_hdlc_param *ucc_pram_bak;
u32 gumr;
u8 guemr;
u32 cmxsi1cr_l, cmxsi1cr_h;
u32 cmxsi1syr;
u32 cmxucr[4];
#endif
};
#define TX_BD_RING_LEN 0x10
#define RX_BD_RING_LEN 0x20
#define RX_CLEAN_MAX 0x10
#define NUM_OF_BUF 4
#define MAX_RX_BUF_LENGTH (48 * 0x20)
#define MAX_FRAME_LENGTH (MAX_RX_BUF_LENGTH + 8)
#define ALIGNMENT_OF_UCC_HDLC_PRAM 64
#define SI_BANK_SIZE 128
#define MAX_HDLC_NUM 4
#define HDLC_HEAD_LEN 2
#define HDLC_CRC_SIZE 2
#define TX_RING_MOD_MASK(size) (size - 1)
#define RX_RING_MOD_MASK(size) (size - 1)
#define HDLC_HEAD_MASK 0x0000
#define DEFAULT_HDLC_HEAD 0xff44
#define DEFAULT_ADDR_MASK 0x00ff
#define DEFAULT_HDLC_ADDR 0x00ff
#define BMR_GBL 0x20000000
#define BMR_BIG_ENDIAN 0x10000000
#define CRC_16BIT_MASK 0x0000F0B8
#define CRC_16BIT_PRES 0x0000FFFF
#define DEFAULT_RFTHR 1
#define DEFAULT_PPP_HEAD 0xff03
#endif
......@@ -657,6 +657,7 @@ struct ucc_slow_pram {
#define UCC_SLOW_GUMR_L_MODE_QMC 0x00000002
/* General UCC FAST Mode Register */
#define UCC_FAST_GUMR_LOOPBACK 0x40000000
#define UCC_FAST_GUMR_TCI 0x20000000
#define UCC_FAST_GUMR_TRX 0x10000000
#define UCC_FAST_GUMR_TTX 0x08000000
......
......@@ -21,19 +21,37 @@
#include <soc/fsl/qe/ucc.h>
/* Receive BD's status */
/* Receive BD's status and length*/
#define R_E 0x80000000 /* buffer empty */
#define R_W 0x20000000 /* wrap bit */
#define R_I 0x10000000 /* interrupt on reception */
#define R_L 0x08000000 /* last */
#define R_F 0x04000000 /* first */
/* transmit BD's status */
/* transmit BD's status and length*/
#define T_R 0x80000000 /* ready bit */
#define T_W 0x20000000 /* wrap bit */
#define T_I 0x10000000 /* interrupt on completion */
#define T_L 0x08000000 /* last */
/* Receive BD's status */
#define R_E_S 0x8000 /* buffer empty */
#define R_W_S 0x2000 /* wrap bit */
#define R_I_S 0x1000 /* interrupt on reception */
#define R_L_S 0x0800 /* last */
#define R_F_S 0x0400 /* first */
#define R_CM_S 0x0200 /* continuous mode */
#define R_CR_S 0x0004 /* crc */
#define R_OV_S 0x0002 /* crc */
/* transmit BD's status */
#define T_R_S 0x8000 /* ready bit */
#define T_W_S 0x2000 /* wrap bit */
#define T_I_S 0x1000 /* interrupt on completion */
#define T_L_S 0x0800 /* last */
#define T_TC_S 0x0400 /* crc */
#define T_TM_S 0x0200 /* continuous mode */
/* Rx Data buffer must be 4 bytes aligned in most cases */
#define UCC_FAST_RX_ALIGN 4
#define UCC_FAST_MRBLR_ALIGNMENT 4
......
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