Commit b8de08da authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'devicetree-for-linus' of git://

Pull devicetree bug fixes and documentation updates from Grant Likely:
 "A few bugfixes for the new DT overlay feature, documentation updates,
  spelling corrections, and changes to MAINTAINERS.  Nothing earth
  shattering here"

* tag 'devicetree-for-linus' of git://
  of/unittest: Overlays with sub-devices tests
  of/platform: Handle of_populate drivers in notifier
  of/overlay: Do not generate duplicate nodes
  devicetree: document the "qemu" and "virtio" vendor prefixes
  devicetree: document ARM bindings for QEMU's Firmware Config interface
  Documentation: of: fix typo in graph bindings
  dma-mapping: fix debug print to display correct dma_pfn_offset
  of: replace Asahi Kasei Corp vendor prefix
  ARM: dt: GIC: Spelling s/specific/specifier/, s/flaggs/flags/
  dt/bindings: arm-boards: Spelling s/pointong/pointing/
  MAINTAINERS: Update DT website and git repository
  MAINTAINERS: drop DT regex matching on of_get_property and of_match_table
parents 2e3810da 6b1271de
......@@ -23,7 +23,7 @@ Required nodes:
range of 0x200 bytes.
- syscon: the root node of the Integrator platforms must have a
system controller node pointong to the control registers,
system controller node pointing to the control registers,
with the compatible string
* QEMU Firmware Configuration bindings for ARM
QEMU's arm-softmmu and aarch64-softmmu emulation / virtualization targets
provide the following Firmware Configuration interface on the "virt" machine
- A write-only, 16-bit wide selector (or control) register,
- a read-write, 64-bit wide data register.
QEMU exposes the control and data register to ARM guests as memory mapped
registers; their location is communicated to the guest's UEFI firmware in the
DTB that QEMU places at the bottom of the guest's DRAM.
The guest writes a selector value (a key) to the selector register, and then
can read the corresponding data (produced by QEMU) via the data register. If
the selected entry is writable, the guest can rewrite it through the data
The selector register takes keys in big endian byte order.
The data register allows accesses with 8, 16, 32 and 64-bit width (only at
offset 0 of the register). Accesses larger than a byte are interpreted as
arrays, bundled together only for better performance. The bytes constituting
such a word, in increasing address order, correspond to the bytes that would
have been transferred by byte-wide accesses in chronological order.
The interface allows guest firmware to download various parameters and blobs
that affect how the firmware works and what tables it installs for the guest
OS. For example, boot order of devices, ACPI tables, SMBIOS tables, kernel and
initrd images for direct kernel booting, virtual machine UUID, SMP information,
virtual NUMA topology, and so on.
The authoritative registry of the valid selector values and their meanings is
the QEMU source code; the structure of the data blobs corresponding to the
individual key values is also defined in the QEMU source code.
The presence of the registers can be verified by selecting the "signature" blob
with key 0x0000, and reading four bytes from the data register. The returned
signature is "QEMU".
The outermost protocol (involving the write / read sequences of the control and
data registers) is expected to be versioned, and/or described by feature bits.
The interface revision / feature bitmap can be retrieved with key 0x0001. The
blob to be read from the data register has size 4, and it is to be interpreted
as a uint32_t value in little endian byte order. The current value
(corresponding to the above outer protocol) is zero.
The guest kernel is not expected to use these registers (although it is
certainly allowed to); the device tree bindings are documented here because
this is where device tree bindings reside in general.
Required properties:
- compatible: "qemu,fw-cfg-mmio".
- reg: the MMIO region used by the device.
* Bytes 0x0 to 0x7 cover the data register.
* Bytes 0x8 to 0x9 cover the selector register.
* Further registers may be appended to the region in case of future interface
revisions / feature bits.
/ {
#size-cells = <0x2>;
#address-cells = <0x2>;
fw-cfg@9020000 {
compatible = "qemu,fw-cfg-mmio";
reg = <0x0 0x9020000 0x0 0xa>;
......@@ -19,7 +19,7 @@ type of the connections, they just map their existence. Specific properties
may be described by specialized bindings depending on the type of connection.
To see how this binding applies to video pipelines, for example, see
Here the ports describe data interfaces, and the links between them are
the connecting data buses. A single port with multiple connections can
correspond to multiple devices being connected to the same physical bus.
......@@ -9,7 +9,6 @@ ad Avionic Design GmbH
adapteva Adapteva, Inc.
adi Analog Devices, Inc.
aeroflexgaisler Aeroflex Gaisler AB
ak Asahi Kasei Corp.
allwinner Allwinner Technology Co., Ltd.
altr Altera Corp.
amcc Applied Micro Circuits Corporation (APM, formally AMCC)
......@@ -20,6 +19,7 @@ amstaos AMS-Taos Inc.
apm Applied Micro Circuits Corporation (APM)
arm ARM Ltd.
armadeus ARMadeus Systems SARL
asahi-kasei Asahi Kasei Corp.
atmel Atmel Corporation
auo AU Optronics Corporation
avago Avago Technologies
......@@ -127,6 +127,7 @@ pixcir PIXCIR MICROELECTRONICS Co., Ltd
powervr PowerVR (deprecated, use img)
qca Qualcomm Atheros, Inc.
qcom Qualcomm Technologies, Inc
qemu QEMU, a generic and open source machine emulator and virtualizer
qnap QNAP Systems, Inc.
radxa Radxa
raidsonic RaidSonic Technology GmbH
......@@ -168,6 +169,7 @@ usi Universal Scientific Industrial Co., Ltd.
v3 V3 Semiconductor
variscite Variscite Ltd.
via VIA Technologies, Inc.
virtio Virtual I/O Device Specification, developed by the OASIS consortium
voipac Voipac Technologies s.r.o.
winbond Winbond Electronics corp.
wlf Wolfson Microelectronics
......@@ -696,7 +696,7 @@ L: (moderated for non-subscribers)
S: Supported
F: sound/soc/blackfin/*
M: Lars-Peter Clausen <>
M: Michael Hennerich <>
......@@ -7024,14 +7024,12 @@ OPEN FIRMWARE AND FLATTENED DEVICE TREE
M: Grant Likely <>
M: Rob Herring <>
T: git git://
T: git git://
S: Maintained
F: drivers/of/
F: include/linux/of*.h
F: scripts/dtc/
K: of_get_property
K: of_match_table
M: Rob Herring <>
......@@ -406,7 +406,7 @@
clock-frequency = <400000>;
magnetometer@c {
compatible = "ak,ak8975";
compatible = "asahi-kasei,ak8975";
reg = <0xc>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_LEVEL_HIGH>;
......@@ -114,17 +114,6 @@ static int of_overlay_apply_single_device_node(struct of_overlay *ov,
ret = of_overlay_apply_one(ov, tchild, child);
if (ret)
return ret;
/* The properties are already copied, now do the child nodes */
for_each_child_of_node(child, grandchild) {
ret = of_overlay_apply_single_device_node(ov, tchild, grandchild);
if (ret) {
pr_err("%s: Failed to apply single node @%s/%s\n",
__func__, tchild->full_name,
return ret;
return ret;
......@@ -188,7 +188,7 @@ static void of_dma_configure(struct device *dev)
size = dev->coherent_dma_mask;
} else {
offset = PFN_DOWN(paddr - dma_addr);
dev_dbg(dev, "dma_pfn_offset(%#08lx)\n", dev->dma_pfn_offset);
dev_dbg(dev, "dma_pfn_offset(%#08lx)\n", offset);
dev->dma_pfn_offset = offset;
......@@ -566,6 +566,10 @@ static int of_platform_notify(struct notifier_block *nb,
if (!of_node_check_flag(rd->dn->parent, OF_POPULATED_BUS))
return NOTIFY_OK; /* not for us */
/* already populated? (driver using of_populate manually) */
if (of_node_check_flag(rd->dn, OF_POPULATED))
return NOTIFY_OK;
/* pdev_parent may be NULL when no bus platform device */
pdev_parent = of_find_device_by_node(rd->dn->parent);
pdev = of_platform_device_create(rd->dn, NULL,
......@@ -581,6 +585,11 @@ static int of_platform_notify(struct notifier_block *nb,
/* already depopulated? */
if (!of_node_check_flag(rd->dn, OF_POPULATED))
return NOTIFY_OK;
/* find our device by node */
pdev = of_find_device_by_node(rd->dn);
if (pdev == NULL)
......@@ -176,5 +176,60 @@
overlay10 {
fragment@0 {
target-path = "/testcase-data/overlay-node/test-bus";
__overlay__ {
/* suppress DTC warning */
#address-cells = <1>;
#size-cells = <0>;
test-selftest10 {
compatible = "selftest";
status = "okay";
reg = <10>;
#address-cells = <1>;
#size-cells = <0>;
test-selftest101 {
compatible = "selftest";
status = "okay";
reg = <1>;
overlay11 {
fragment@0 {
target-path = "/testcase-data/overlay-node/test-bus";
__overlay__ {
/* suppress DTC warning */
#address-cells = <1>;
#size-cells = <0>;
test-selftest11 {
compatible = "selftest";
status = "okay";
reg = <11>;
#address-cells = <1>;
#size-cells = <0>;
test-selftest111 {
compatible = "selftest";
status = "okay";
reg = <1>;
......@@ -978,6 +978,9 @@ static int selftest_probe(struct platform_device *pdev)
dev_dbg(dev, "%s for node @%s\n", __func__, np->full_name);
of_platform_populate(np, NULL, NULL, &pdev->dev);
return 0;
......@@ -1385,6 +1388,39 @@ static void of_selftest_overlay_8(void)
selftest(1, "overlay test %d passed\n", 8);
/* test insertion of a bus with parent devices */
static void of_selftest_overlay_10(void)
int ret;
char *child_path;
/* device should disable */
ret = of_selftest_apply_overlay_check(10, 10, 0, 1);
if (selftest(ret == 0, "overlay test %d failed; overlay application\n", 10))
child_path = kasprintf(GFP_KERNEL, "%s/test-selftest101",
if (selftest(child_path, "overlay test %d failed; kasprintf\n", 10))
ret = of_path_platform_device_exists(child_path);
if (selftest(ret, "overlay test %d failed; no child device\n", 10))
/* test insertion of a bus with parent devices (and revert) */
static void of_selftest_overlay_11(void)
int ret;
/* device should disable */
ret = of_selftest_apply_revert_overlay_check(11, 11, 0, 1);
if (selftest(ret == 0, "overlay test %d failed; overlay application\n", 11))
static void __init of_selftest_overlay(void)
struct device_node *bus_np = NULL;
......@@ -1433,6 +1469,9 @@ static void __init of_selftest_overlay(void)
......@@ -7,14 +7,14 @@
#include <dt-bindings/interrupt-controller/irq.h>
/* interrupt specific cell 0 */
/* interrupt specifier cell 0 */
#define GIC_SPI 0
#define GIC_PPI 1
* Interrupt specifier cell 2.
* The flaggs in irq.h are valid, plus those below.
* The flags in irq.h are valid, plus those below.
#define GIC_CPU_MASK_RAW(x) ((x) << 8)
#define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1)
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