Commit a8492e88 authored by Jacopo Mondi's avatar Jacopo Mondi Committed by Laurent Pinchart
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drm: rcar-du: Write ESCR and OTAR as CRTC registers

The ESCR and OTAR registers exist in each DU channel, but at different
offsets for odd and even channels. This led to usage of the group
register access API to write them, with offsets macros named ESCR/OTAR
and ESCR2/OTAR2 for the first and second ESCR/OTAR register in the group

The names are confusing as it suggests that the ESCR/OTAR registers for
DU0 and DU2 are taken into account, especially with writes performed to
the group register access API.

Rename the offsets to ESCR/OTAR02 and ESCR/OTAR13, and use the CRTC
register access API to clarify the code. The offsets values are updated

Cosmetic patch, no functional changes intended.
Signed-off-by: default avatarJacopo Mondi <>
Reviewed-by: default avatarLaurent Pinchart <>
[Squashed ESCR and OTAR changes in a single commit]
Signed-off-by: default avatarLaurent Pinchart <>
parent 9fe50e64
......@@ -313,9 +313,8 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
dev_dbg(rcrtc->group->dev->dev, "%s: ESCR 0x%08x\n", __func__, escr);
rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? ESCR2 : ESCR,
rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? OTAR2 : OTAR, 0);
rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? ESCR13 : ESCR02, escr);
rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? OTAR13 : OTAR02, 0);
/* Signal polarities */
dsmr = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? DSMR_VSL : 0)
......@@ -489,8 +489,8 @@
* External Synchronization Control Registers
#define ESCR 0x10000
#define ESCR2 0x31000
#define ESCR02 0x10000
#define ESCR13 0x01000
#define ESCR_DCLKOINV (1 << 25)
#define ESCR_DCLKSEL_DCLKIN (0 << 20)
#define ESCR_DCLKSEL_CLKS (1 << 20)
......@@ -501,8 +501,8 @@
#define ESCR_SYNCSEL_EXHSYNC (3 << 8)
#define ESCR_FRQSEL_MASK (0x3f << 0)
#define OTAR 0x10004
#define OTAR2 0x31004
#define OTAR02 0x10004
#define OTAR13 0x01004
/* -----------------------------------------------------------------------------
* Dual Display Output Control Registers
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