Commit 96bed4b9 authored by Yuval Mintz's avatar Yuval Mintz Committed by David S. Miller

bnx2x,cnic: use FW 7.8.2

This patch moves the bnx2x and cnic drivers into using FW 7.8.2
which was recently submitted into the linux-firmware tree.

A short summary of minor bugs fixed by this FW:
 1. In switch dependent mode, fix several issues regarding inner vlan
    vs. DCB priorities.
 2. iSCSI - not all packets were completed on a forward channel.
 3. DCB - fixed for 4-port devices.
 4. Fixed false parity reported in CAM memories when operating near -5%
    on the 1.0V core supply.
 5. ETS default settings are set to fairness between traffic classes
    (rather than strict priority), and uses the same chip receive buffer
    configuration for both PFC and pause.

For a complete list of fixes made by this FW, see commit 236367db
in the linux-firmware git repository.
Signed-off-by: default avatarYuval Mintz <yuvalmin@broadcom.com>
Signed-off-by: default avatarDmitry Kravkov <dmitry@broadcom.com>
Signed-off-by: default avatarAriel Elior <ariele@broadcom.com>
Signed-off-by: default avatarEilon Greenstein <eilong@broadcom.com>
Signed-off-by: default avatarMichael Chan <mchan@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 2f6a0260
......@@ -3026,8 +3026,9 @@ netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
first_bd = tx_start_bd;
tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
SET_FLAG(tx_start_bd->general_data, ETH_TX_START_BD_ETH_ADDR_TYPE,
mac_type);
SET_FLAG(tx_start_bd->general_data,
ETH_TX_START_BD_PARSE_NBDS,
0);
/* header nbd */
SET_FLAG(tx_start_bd->general_data, ETH_TX_START_BD_HDR_NBDS, 1);
......@@ -3077,13 +3078,20 @@ netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
&pbd_e2->dst_mac_addr_lo,
eth->h_dest);
}
SET_FLAG(pbd_e2_parsing_data,
ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, mac_type);
} else {
u16 global_data = 0;
pbd_e1x = &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
/* Set PBD in checksum offload case */
if (xmit_type & XMIT_CSUM)
hlen = bnx2x_set_pbd_csum(bp, skb, pbd_e1x, xmit_type);
SET_FLAG(global_data,
ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, mac_type);
pbd_e1x->global_data |= cpu_to_le16(global_data);
}
/* Setup the data pointer of the first BD of the packet */
......
......@@ -91,25 +91,21 @@ static void bnx2x_pfc_set(struct bnx2x *bp)
/*
* Rx COS configuration
* Changing PFC RX configuration .
* In RX COS0 will always be configured to lossy and COS1 to lossless
* In RX COS0 will always be configured to lossless and COS1 to lossy
*/
for (i = 0 ; i < MAX_PFC_PRIORITIES ; i++) {
pri_bit = 1 << i;
if (pri_bit & DCBX_PFC_PRI_PAUSE_MASK(bp))
if (!(pri_bit & DCBX_PFC_PRI_PAUSE_MASK(bp)))
val |= 1 << (i * 4);
}
pfc_params.pkt_priority_to_cos = val;
/* RX COS0 */
pfc_params.llfc_low_priority_classes = 0;
pfc_params.llfc_low_priority_classes = DCBX_PFC_PRI_PAUSE_MASK(bp);
/* RX COS1 */
pfc_params.llfc_high_priority_classes = DCBX_PFC_PRI_PAUSE_MASK(bp);
/* BRB configuration */
pfc_params.cos0_pauseable = false;
pfc_params.cos1_pauseable = true;
pfc_params.llfc_high_priority_classes = 0;
bnx2x_acquire_phy_lock(bp);
bp->link_params.feature_config_flags |= FEATURE_CONFIG_PFC_ENABLED;
......
......@@ -2040,8 +2040,6 @@ static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
u16 pkt_prod, bd_prod;
struct sw_tx_bd *tx_buf;
struct eth_tx_start_bd *tx_start_bd;
struct eth_tx_parse_bd_e1x *pbd_e1x = NULL;
struct eth_tx_parse_bd_e2 *pbd_e2 = NULL;
dma_addr_t mapping;
union eth_rx_cqe *cqe;
u8 cqe_fp_flags, cqe_fp_type;
......@@ -2132,22 +2130,33 @@ static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
SET_FLAG(tx_start_bd->general_data,
ETH_TX_START_BD_ETH_ADDR_TYPE,
UNICAST_ADDRESS);
SET_FLAG(tx_start_bd->general_data,
ETH_TX_START_BD_HDR_NBDS,
1);
SET_FLAG(tx_start_bd->general_data,
ETH_TX_START_BD_PARSE_NBDS,
0);
/* turn on parsing and get a BD */
bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
pbd_e1x = &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
pbd_e2 = &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
if (CHIP_IS_E1x(bp)) {
u16 global_data = 0;
struct eth_tx_parse_bd_e1x *pbd_e1x =
&txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
SET_FLAG(global_data,
ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, UNICAST_ADDRESS);
pbd_e1x->global_data = cpu_to_le16(global_data);
} else {
u32 parsing_data = 0;
struct eth_tx_parse_bd_e2 *pbd_e2 =
&txdata->tx_desc_ring[bd_prod].parse_bd_e2;
memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
SET_FLAG(parsing_data,
ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, UNICAST_ADDRESS);
pbd_e2->parsing_data = cpu_to_le32(parsing_data);
}
wmb();
txdata->tx_db.data.prod += 2;
......
......@@ -88,9 +88,6 @@
#define TSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[102].base)
#define TSTORM_ASSERT_LIST_OFFSET(assertListEntry) \
(IRO[101].base + ((assertListEntry) * IRO[101].m1))
#define TSTORM_COMMON_SAFC_WORKAROUND_ENABLE_OFFSET (IRO[107].base)
#define TSTORM_COMMON_SAFC_WORKAROUND_TIMEOUT_10USEC_OFFSET \
(IRO[108].base)
#define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(pfId) \
(IRO[201].base + ((pfId) * IRO[201].m1))
#define TSTORM_FUNC_EN_OFFSET(funcId) \
......
......@@ -2789,8 +2789,8 @@ struct afex_stats {
};
#define BCM_5710_FW_MAJOR_VERSION 7
#define BCM_5710_FW_MINOR_VERSION 2
#define BCM_5710_FW_REVISION_VERSION 51
#define BCM_5710_FW_MINOR_VERSION 8
#define BCM_5710_FW_REVISION_VERSION 2
#define BCM_5710_FW_ENGINEERING_VERSION 0
#define BCM_5710_FW_COMPILE_FLAGS 1
......@@ -3912,10 +3912,8 @@ struct eth_rss_update_ramrod_data {
#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 4
#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<5)
#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 5
#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<6)
#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 6
#define __ETH_RSS_UPDATE_RAMROD_DATA_RESERVED0 (0x1<<7)
#define __ETH_RSS_UPDATE_RAMROD_DATA_RESERVED0_SHIFT 7
#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<7)
#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 7
u8 rss_result_mask;
u8 rss_mode;
__le32 __reserved2;
......@@ -4131,27 +4129,29 @@ struct eth_tx_start_bd {
#define ETH_TX_START_BD_HDR_NBDS_SHIFT 0
#define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4)
#define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4
#define ETH_TX_START_BD_RESREVED (0x1<<5)
#define ETH_TX_START_BD_RESREVED_SHIFT 5
#define ETH_TX_START_BD_ETH_ADDR_TYPE (0x3<<6)
#define ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT 6
#define ETH_TX_START_BD_PARSE_NBDS (0x3<<5)
#define ETH_TX_START_BD_PARSE_NBDS_SHIFT 5
#define ETH_TX_START_BD_RESREVED (0x1<<7)
#define ETH_TX_START_BD_RESREVED_SHIFT 7
};
/*
* Tx parsing BD structure for ETH E1/E1h
*/
struct eth_tx_parse_bd_e1x {
u8 global_data;
__le16 global_data;
#define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0)
#define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0
#define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x1<<4)
#define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 4
#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<5)
#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 5
#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<6)
#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 6
#define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<7)
#define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 7
#define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE (0x3<<4)
#define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE_SHIFT 4
#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<6)
#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 6
#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<7)
#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 7
#define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<8)
#define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 8
#define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x7F<<9)
#define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 9
u8 tcp_flags;
#define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0)
#define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0
......@@ -4170,7 +4170,6 @@ struct eth_tx_parse_bd_e1x {
#define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7)
#define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7
u8 ip_hlen_w;
s8 reserved;
__le16 total_hlen_w;
__le16 tcp_pseudo_csum;
__le16 lso_mss;
......@@ -4189,14 +4188,16 @@ struct eth_tx_parse_bd_e2 {
__le16 src_mac_addr_mid;
__le16 src_mac_addr_hi;
__le32 parsing_data;
#define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W (0x1FFF<<0)
#define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W (0x7FF<<0)
#define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W_SHIFT 0
#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<13)
#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 13
#define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<17)
#define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 17
#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<31)
#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 31
#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<11)
#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 11
#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<15)
#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 15
#define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<16)
#define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 16
#define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE (0x3<<30)
#define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT 30
};
/*
......@@ -4964,7 +4965,8 @@ struct flow_control_configuration {
*
*/
struct function_start_data {
__le16 function_mode;
u8 function_mode;
u8 reserved;
__le16 sd_vlan_tag;
__le16 vif_id;
u8 path_id;
......
......@@ -566,7 +566,7 @@ static const struct {
u32 e2; /* 57712 */
u32 e3; /* 578xx */
} reg_mask; /* Register mask (all valid bits) */
char name[7]; /* Block's longest name is 6 characters long
char name[8]; /* Block's longest name is 7 characters long
* (name + suffix)
*/
} bnx2x_blocks_parity_data[] = {
......
......@@ -161,120 +161,6 @@
#define EDC_MODE_LIMITING 0x0044
#define EDC_MODE_PASSIVE_DAC 0x0055
/* BRB default for class 0 E2 */
#define DEFAULT0_E2_BRB_MAC_PAUSE_XOFF_THR 170
#define DEFAULT0_E2_BRB_MAC_PAUSE_XON_THR 250
#define DEFAULT0_E2_BRB_MAC_FULL_XOFF_THR 10
#define DEFAULT0_E2_BRB_MAC_FULL_XON_THR 50
/* BRB thresholds for E2*/
#define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE 170
#define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
#define PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE 250
#define PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
#define PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE 10
#define PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 90
#define PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE 50
#define PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE 250
/* BRB default for class 0 E3A0 */
#define DEFAULT0_E3A0_BRB_MAC_PAUSE_XOFF_THR 290
#define DEFAULT0_E3A0_BRB_MAC_PAUSE_XON_THR 410
#define DEFAULT0_E3A0_BRB_MAC_FULL_XOFF_THR 10
#define DEFAULT0_E3A0_BRB_MAC_FULL_XON_THR 50
/* BRB thresholds for E3A0 */
#define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE 290
#define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
#define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE 410
#define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
#define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE 10
#define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 170
#define PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE 50
#define PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE 410
/* BRB default for E3B0 */
#define DEFAULT0_E3B0_BRB_MAC_PAUSE_XOFF_THR 330
#define DEFAULT0_E3B0_BRB_MAC_PAUSE_XON_THR 490
#define DEFAULT0_E3B0_BRB_MAC_FULL_XOFF_THR 15
#define DEFAULT0_E3B0_BRB_MAC_FULL_XON_THR 55
/* BRB thresholds for E3B0 2 port mode*/
#define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE 1025
#define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
#define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE 1025
#define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
#define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE 10
#define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 1025
#define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE 50
#define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE 1025
/* only for E3B0*/
#define PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR 1025
#define PFC_E3B0_2P_BRB_FULL_LB_XON_THR 1025
/* Lossy +Lossless GUARANTIED == GUART */
#define PFC_E3B0_2P_MIX_PAUSE_LB_GUART 284
/* Lossless +Lossless*/
#define PFC_E3B0_2P_PAUSE_LB_GUART 236
/* Lossy +Lossy*/
#define PFC_E3B0_2P_NON_PAUSE_LB_GUART 342
/* Lossy +Lossless*/
#define PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART 284
/* Lossless +Lossless*/
#define PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART 236
/* Lossy +Lossy*/
#define PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART 336
#define PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST 80
#define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART 0
#define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST 0
/* BRB thresholds for E3B0 4 port mode */
#define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE 304
#define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
#define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE 384
#define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
#define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE 10
#define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 304
#define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE 50
#define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE 384
/* only for E3B0*/
#define PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR 304
#define PFC_E3B0_4P_BRB_FULL_LB_XON_THR 384
#define PFC_E3B0_4P_LB_GUART 120
#define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART 120
#define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST 80
#define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART 80
#define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST 120
/* Pause defines*/
#define DEFAULT_E3B0_BRB_FULL_LB_XOFF_THR 330
#define DEFAULT_E3B0_BRB_FULL_LB_XON_THR 490
#define DEFAULT_E3B0_LB_GUART 40
#define DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART 40
#define DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART_HYST 0
#define DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART 40
#define DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART_HYST 0
/* ETS defines*/
#define DCBX_INVALID_COS (0xFF)
......@@ -2144,391 +2030,6 @@ static void bnx2x_update_pfc_bmac2(struct link_params *params,
REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
}
/* PFC BRB internal port configuration params */
struct bnx2x_pfc_brb_threshold_val {
u32 pause_xoff;
u32 pause_xon;
u32 full_xoff;
u32 full_xon;
};
struct bnx2x_pfc_brb_e3b0_val {
u32 per_class_guaranty_mode;
u32 lb_guarantied_hyst;
u32 full_lb_xoff_th;
u32 full_lb_xon_threshold;
u32 lb_guarantied;
u32 mac_0_class_t_guarantied;
u32 mac_0_class_t_guarantied_hyst;
u32 mac_1_class_t_guarantied;
u32 mac_1_class_t_guarantied_hyst;
};
struct bnx2x_pfc_brb_th_val {
struct bnx2x_pfc_brb_threshold_val pauseable_th;
struct bnx2x_pfc_brb_threshold_val non_pauseable_th;
struct bnx2x_pfc_brb_threshold_val default_class0;
struct bnx2x_pfc_brb_threshold_val default_class1;
};
static int bnx2x_pfc_brb_get_config_params(
struct link_params *params,
struct bnx2x_pfc_brb_th_val *config_val)
{
struct bnx2x *bp = params->bp;
DP(NETIF_MSG_LINK, "Setting PFC BRB configuration\n");
config_val->default_class1.pause_xoff = 0;
config_val->default_class1.pause_xon = 0;
config_val->default_class1.full_xoff = 0;
config_val->default_class1.full_xon = 0;
if (CHIP_IS_E2(bp)) {
/* Class0 defaults */
config_val->default_class0.pause_xoff =
DEFAULT0_E2_BRB_MAC_PAUSE_XOFF_THR;
config_val->default_class0.pause_xon =
DEFAULT0_E2_BRB_MAC_PAUSE_XON_THR;
config_val->default_class0.full_xoff =
DEFAULT0_E2_BRB_MAC_FULL_XOFF_THR;
config_val->default_class0.full_xon =
DEFAULT0_E2_BRB_MAC_FULL_XON_THR;
/* Pause able*/
config_val->pauseable_th.pause_xoff =
PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
config_val->pauseable_th.pause_xon =
PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE;
config_val->pauseable_th.full_xoff =
PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE;
config_val->pauseable_th.full_xon =
PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE;
/* Non pause able*/
config_val->non_pauseable_th.pause_xoff =
PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
config_val->non_pauseable_th.pause_xon =
PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
config_val->non_pauseable_th.full_xoff =
PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
config_val->non_pauseable_th.full_xon =
PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE;
} else if (CHIP_IS_E3A0(bp)) {
/* Class0 defaults */
config_val->default_class0.pause_xoff =
DEFAULT0_E3A0_BRB_MAC_PAUSE_XOFF_THR;
config_val->default_class0.pause_xon =
DEFAULT0_E3A0_BRB_MAC_PAUSE_XON_THR;
config_val->default_class0.full_xoff =
DEFAULT0_E3A0_BRB_MAC_FULL_XOFF_THR;
config_val->default_class0.full_xon =
DEFAULT0_E3A0_BRB_MAC_FULL_XON_THR;
/* Pause able */
config_val->pauseable_th.pause_xoff =
PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
config_val->pauseable_th.pause_xon =
PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE;
config_val->pauseable_th.full_xoff =
PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE;
config_val->pauseable_th.full_xon =
PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE;
/* Non pause able*/
config_val->non_pauseable_th.pause_xoff =
PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
config_val->non_pauseable_th.pause_xon =
PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
config_val->non_pauseable_th.full_xoff =
PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
config_val->non_pauseable_th.full_xon =
PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE;
} else if (CHIP_IS_E3B0(bp)) {
/* Class0 defaults */
config_val->default_class0.pause_xoff =
DEFAULT0_E3B0_BRB_MAC_PAUSE_XOFF_THR;
config_val->default_class0.pause_xon =
DEFAULT0_E3B0_BRB_MAC_PAUSE_XON_THR;
config_val->default_class0.full_xoff =
DEFAULT0_E3B0_BRB_MAC_FULL_XOFF_THR;
config_val->default_class0.full_xon =
DEFAULT0_E3B0_BRB_MAC_FULL_XON_THR;
if (params->phy[INT_PHY].flags &
FLAGS_4_PORT_MODE) {
config_val->pauseable_th.pause_xoff =
PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
config_val->pauseable_th.pause_xon =
PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE;
config_val->pauseable_th.full_xoff =
PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE;
config_val->pauseable_th.full_xon =
PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE;
/* Non pause able*/
config_val->non_pauseable_th.pause_xoff =
PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
config_val->non_pauseable_th.pause_xon =
PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
config_val->non_pauseable_th.full_xoff =
PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
config_val->non_pauseable_th.full_xon =
PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
} else {
config_val->pauseable_th.pause_xoff =
PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
config_val->pauseable_th.pause_xon =
PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE;
config_val->pauseable_th.full_xoff =
PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE;
config_val->pauseable_th.full_xon =
PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE;
/* Non pause able*/
config_val->non_pauseable_th.pause_xoff =
PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
config_val->non_pauseable_th.pause_xon =
PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
config_val->non_pauseable_th.full_xoff =
PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
config_val->non_pauseable_th.full_xon =
PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
}
} else
return -EINVAL;
return 0;
}
static void bnx2x_pfc_brb_get_e3b0_config_params(
struct link_params *params,
struct bnx2x_pfc_brb_e3b0_val
*e3b0_val,
struct bnx2x_nig_brb_pfc_port_params *pfc_params,
const u8 pfc_enabled)
{
if (pfc_enabled && pfc_params) {
e3b0_val->per_class_guaranty_mode = 1;
e3b0_val->lb_guarantied_hyst = 80;
if (params->phy[INT_PHY].flags &
FLAGS_4_PORT_MODE) {
e3b0_val->full_lb_xoff_th =
PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR;
e3b0_val->full_lb_xon_threshold =
PFC_E3B0_4P_BRB_FULL_LB_XON_THR;
e3b0_val->lb_guarantied =
PFC_E3B0_4P_LB_GUART;
e3b0_val->mac_0_class_t_guarantied =
PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART;
e3b0_val->mac_0_class_t_guarantied_hyst =
PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST;
e3b0_val->mac_1_class_t_guarantied =
PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART;
e3b0_val->mac_1_class_t_guarantied_hyst =
PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST;
} else {
e3b0_val->full_lb_xoff_th =
PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR;
e3b0_val->full_lb_xon_threshold =
PFC_E3B0_2P_BRB_FULL_LB_XON_THR;
e3b0_val->mac_0_class_t_guarantied_hyst =
PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST;
e3b0_val->mac_1_class_t_guarantied =
PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART;
e3b0_val->mac_1_class_t_guarantied_hyst =
PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST;
if (pfc_params->cos0_pauseable !=
pfc_params->cos1_pauseable) {
/* Nonpauseable= Lossy + pauseable = Lossless*/
e3b0_val->lb_guarantied =
PFC_E3B0_2P_MIX_PAUSE_LB_GUART;
e3b0_val->mac_0_class_t_guarantied =
PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART;
} else if (pfc_params->cos0_pauseable) {
/* Lossless +Lossless*/
e3b0_val->lb_guarantied =
PFC_E3B0_2P_PAUSE_LB_GUART;
e3b0_val->mac_0_class_t_guarantied =
PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART;
} else {
/* Lossy +Lossy*/
e3b0_val->lb_guarantied =
PFC_E3B0_2P_NON_PAUSE_LB_GUART;
e3b0_val->mac_0_class_t_guarantied =
PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART;
}
}
} else {
e3b0_val->per_class_guaranty_mode = 0;
e3b0_val->lb_guarantied_hyst = 0;
e3b0_val->full_lb_xoff_th =
DEFAULT_E3B0_BRB_FULL_LB_XOFF_THR;
e3b0_val->full_lb_xon_threshold =
DEFAULT_E3B0_BRB_FULL_LB_XON_THR;
e3b0_val->lb_guarantied =
DEFAULT_E3B0_LB_GUART;
e3b0_val->mac_0_class_t_guarantied =
DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART;
e3b0_val->mac_0_class_t_guarantied_hyst =
DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART_HYST;
e3b0_val->mac_1_class_t_guarantied =
DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART;
e3b0_val->mac_1_class_t_guarantied_hyst =
DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART_HYST;
}
}
static int bnx2x_update_pfc_brb(struct link_params *params,
struct link_vars *vars,
struct bnx2x_nig_brb_pfc_port_params
*pfc_params)
{
struct bnx2x *bp = params->bp;
struct bnx2x_pfc_brb_th_val config_val = { {0} };
struct bnx2x_pfc_brb_threshold_val *reg_th_config =
&config_val.pauseable_th;
struct bnx2x_pfc_brb_e3b0_val e3b0_val = {0};
const int set_pfc = params->feature_config_flags &
FEATURE_CONFIG_PFC_ENABLED;
const u8 pfc_enabled = (set_pfc && pfc_params);
int bnx2x_status = 0;
u8 port = params->port;
/* default - pause configuration */
reg_th_config = &config_val.pauseable_th;
bnx2x_status = bnx2x_pfc_brb_get_config_params(params, &config_val);
if (bnx2x_status)
return bnx2x_status;
if (pfc_enabled) {
/* First COS */
if (pfc_params->cos0_pauseable)
reg_th_config = &config_val.pauseable_th;
else
reg_th_config = &config_val.non_pauseable_th;
} else