Commit 7e8d9415 authored by Sebastian Hesselbarth's avatar Sebastian Hesselbarth Committed by Jason Cooper

pinctrl: mvebu: pinctrl driver core

This patch adds a pinctrl driver core for Marvell SoCs plus DT
binding documentation. This core driver will be used by SoC family
specific drivers, i.e. Armada XP, Armada 370, Dove, Kirkwood, aso.
Signed-off-by: default avatarSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: default avatarThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: default avatarThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: default avatarThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: default avatarStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: default avatarJason Cooper <jason@lakedaemon.net>

Conflicts:

	arch/arm/Kconfig
parent 5b40baee
* Marvell SoC pinctrl core driver for mpp
The pinctrl driver enables Marvell SoCs to configure the multi-purpose pins
(mpp) to a specific function. For each SoC family there is a SoC specific
driver using this core driver.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
A Marvell SoC pin configuration node is a node of a group of pins which can
be used for a specific device or function. Each node requires one or more
mpp pins or group of pins and a mpp function common to all pins.
Required properties for pinctrl driver:
- compatible: "marvell,<soc>-pinctrl"
Please refer to each marvell,<soc>-pinctrl.txt binding doc for supported SoCs.
Required properties for pin configuration node:
- marvell,pins: string array of mpp pins or group of pins to be muxed.
- marvell,function: string representing a function to mux to for all
marvell,pins given in this pin configuration node. The function has to be
common for all marvell,pins. Please refer to marvell,<soc>-pinctrl.txt for
valid pin/pin group names and available function names for each SoC.
Examples:
uart1: serial@12100 {
compatible = "ns16550a";
reg = <0x12100 0x100>;
reg-shift = <2>;
interrupts = <7>;
pinctrl-0 = <&pmx_uart1_sw>;
pinctrl-names = "default";
};
pinctrl: pinctrl@d0200 {
compatible = "marvell,dove-pinctrl";
reg = <0xd0200 0x20>;
pmx_uart1_sw: pmx-uart1-sw {
marvell,pins = "mpp_uart1";
marvell,function = "uart1";
};
};
...@@ -568,6 +568,7 @@ config ARCH_MVEBU ...@@ -568,6 +568,7 @@ config ARCH_MVEBU
select IRQ_DOMAIN select IRQ_DOMAIN
select COMMON_CLK select COMMON_CLK
select PLAT_ORION select PLAT_ORION
select PINCTRL
help help
Support for the Marvell SoC Family with device tree support Support for the Marvell SoC Family with device tree support
......
...@@ -145,6 +145,12 @@ config PINCTRL_COH901 ...@@ -145,6 +145,12 @@ config PINCTRL_COH901
COH 901 335 and COH 901 571/3. They contain 3, 5 or 7 COH 901 335 and COH 901 571/3. They contain 3, 5 or 7
ports of 8 GPIO pins each. ports of 8 GPIO pins each.
config PINCTRL_MVEBU
bool
depends on ARCH_MVEBU
select PINMUX
select PINCONF
source "drivers/pinctrl/spear/Kconfig" source "drivers/pinctrl/spear/Kconfig"
endmenu endmenu
......
...@@ -29,5 +29,6 @@ obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o ...@@ -29,5 +29,6 @@ obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o
obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o
obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o
obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o
obj-$(CONFIG_PINCTRL_MVEBU) += pinctrl-mvebu.o
obj-$(CONFIG_PLAT_SPEAR) += spear/ obj-$(CONFIG_PLAT_SPEAR) += spear/
This diff is collapsed.
/*
* Marvell MVEBU pinctrl driver
*
* Authors: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __PINCTRL_MVEBU_H__
#define __PINCTRL_MVEBU_H__
/**
* struct mvebu_mpp_ctrl - describe a mpp control
* @name: name of the control group
* @pid: first pin id handled by this control
* @npins: number of pins controlled by this control
* @mpp_get: (optional) special function to get mpp setting
* @mpp_set: (optional) special function to set mpp setting
* @mpp_gpio_req: (optional) special function to request gpio
* @mpp_gpio_dir: (optional) special function to set gpio direction
*
* A mpp_ctrl describes a muxable unit, e.g. pin, group of pins, or
* internal function, inside the SoC. Each muxable unit can be switched
* between two or more different settings, e.g. assign mpp pin 13 to
* uart1 or sata.
*
* If optional mpp_get/_set functions are set these are used to get/set
* a specific mode. Otherwise it is assumed that the mpp control is based
* on 4-bit groups in subsequent registers. The optional mpp_gpio_req/_dir
* functions can be used to allow pin settings with varying gpio pins.
*/
struct mvebu_mpp_ctrl {
const char *name;
u8 pid;
u8 npins;
unsigned *pins;
int (*mpp_get)(struct mvebu_mpp_ctrl *ctrl, unsigned long *config);
int (*mpp_set)(struct mvebu_mpp_ctrl *ctrl, unsigned long config);
int (*mpp_gpio_req)(struct mvebu_mpp_ctrl *ctrl, u8 pid);
int (*mpp_gpio_dir)(struct mvebu_mpp_ctrl *ctrl, u8 pid, bool input);
};
/**
* struct mvebu_mpp_ctrl_setting - describe a mpp ctrl setting
* @val: ctrl setting value
* @name: ctrl setting name, e.g. uart2, spi0 - unique per mpp_mode
* @subname: (optional) additional ctrl setting name, e.g. rts, cts
* @variant: (optional) variant identifier mask
* @flags: (private) flags to store gpi/gpo/gpio capabilities
*
* A ctrl_setting describes a specific internal mux function that a mpp pin
* can be switched to. The value (val) will be written in the corresponding
* register for common mpp pin configuration registers on MVEBU. SoC specific
* mpp_get/_set function may use val to distinguish between different settings.
*
* The name will be used to switch to this setting in DT description, e.g.
* marvell,function = "uart2". subname is only for debugging purposes.
*
* If name is one of "gpi", "gpo", "gpio" gpio capabilities are
* parsed during initialization and stored in flags.
*
* The variant can be used to combine different revisions of one SoC to a
* common pinctrl driver. It is matched (AND) with variant of soc_info to
* determine if a setting is available on the current SoC revision.
*/
struct mvebu_mpp_ctrl_setting {
u8 val;
const char *name;
const char *subname;
u8 variant;
u8 flags;
#define MVEBU_SETTING_GPO (1 << 0)
#define MVEBU_SETTING_GPI (1 << 1)
};
/**
* struct mvebu_mpp_mode - link ctrl and settings
* @pid: first pin id handled by this mode
* @settings: list of settings available for this mode
*
* A mode connects all available settings with the corresponding mpp_ctrl
* given by pid.
*/
struct mvebu_mpp_mode {
u8 pid;
struct mvebu_mpp_ctrl_setting *settings;
};
/**
* struct mvebu_pinctrl_soc_info - SoC specific info passed to pinctrl-mvebu
* @variant: variant mask of soc_info
* @controls: list of available mvebu_mpp_ctrls
* @ncontrols: number of available mvebu_mpp_ctrls
* @modes: list of available mvebu_mpp_modes
* @nmodes: number of available mvebu_mpp_modes
* @gpioranges: list of pinctrl_gpio_ranges
* @ngpioranges: number of available pinctrl_gpio_ranges
*
* This struct describes all pinctrl related information for a specific SoC.
* If variant is unequal 0 it will be matched (AND) with variant of each
* setting and allows to distinguish between different revisions of one SoC.
*/
struct mvebu_pinctrl_soc_info {
u8 variant;
struct mvebu_mpp_ctrl *controls;
int ncontrols;
struct mvebu_mpp_mode *modes;
int nmodes;
struct pinctrl_gpio_range *gpioranges;
int ngpioranges;
};
#define MPP_REG_CTRL(_idl, _idh) \
{ \
.name = NULL, \
.pid = _idl, \
.npins = _idh - _idl + 1, \
.pins = (unsigned[_idh - _idl + 1]) { }, \
.mpp_get = NULL, \
.mpp_set = NULL, \
.mpp_gpio_req = NULL, \
.mpp_gpio_dir = NULL, \
}
#define MPP_FUNC_CTRL(_idl, _idh, _name, _func) \
{ \
.name = _name, \
.pid = _idl, \
.npins = _idh - _idl + 1, \
.pins = (unsigned[_idh - _idl + 1]) { }, \
.mpp_get = _func ## _get, \
.mpp_set = _func ## _set, \
.mpp_gpio_req = NULL, \
.mpp_gpio_dir = NULL, \
}
#define MPP_FUNC_GPIO_CTRL(_idl, _idh, _name, _func) \
{ \
.name = _name, \
.pid = _idl, \
.npins = _idh - _idl + 1, \
.pins = (unsigned[_idh - _idl + 1]) { }, \
.mpp_get = _func ## _get, \
.mpp_set = _func ## _set, \
.mpp_gpio_req = _func ## _gpio_req, \
.mpp_gpio_dir = _func ## _gpio_dir, \
}
#define _MPP_VAR_FUNCTION(_val, _name, _subname, _mask) \
{ \
.val = _val, \
.name = _name, \
.subname = _subname, \
.variant = _mask, \
.flags = 0, \
}
#if defined(CONFIG_DEBUG_FS)
#define MPP_VAR_FUNCTION(_val, _name, _subname, _mask) \
_MPP_VAR_FUNCTION(_val, _name, _subname, _mask)
#else
#define MPP_VAR_FUNCTION(_val, _name, _subname, _mask) \
_MPP_VAR_FUNCTION(_val, _name, NULL, _mask)
#endif
#define MPP_FUNCTION(_val, _name, _subname) \
MPP_VAR_FUNCTION(_val, _name, _subname, (u8)-1)
#define MPP_MODE(_id, ...) \
{ \
.pid = _id, \
.settings = (struct mvebu_mpp_ctrl_setting[]){ \
__VA_ARGS__, { } }, \
}
#define MPP_GPIO_RANGE(_id, _pinbase, _gpiobase, _npins) \
{ \
.name = "mvebu-gpio", \
.id = _id, \
.pin_base = _pinbase, \
.base = _gpiobase, \
.npins = _npins, \
}
int mvebu_pinctrl_probe(struct platform_device *pdev);
int mvebu_pinctrl_remove(struct platform_device *pdev);
#endif
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