Commit 74d86f6b authored by hanetzer's avatar hanetzer

drm/panfrost: add gpu init code.

Signed-off-by: hanetzer's avatarMarty E. Plummer <hanetzer@startmail.com>
parent 08a35b45
......@@ -5,6 +5,7 @@
#include <linux/regulator/consumer.h>
#include "panfrost_device.h"
#include "panfrost_gpu.h"
struct panfrost_ip_desc {
char *name;
......
......@@ -28,6 +28,11 @@ struct panfrost_ip {
void __iomem *iomem;
int irq;
union {
/* gpu */
bool async_reset;
} data;
};
struct panfrost_device {
......@@ -47,13 +52,12 @@ struct panfrost_device {
int panfrost_device_init(struct panfrost_device *pfdev);
void panfrost_device_fini(struct panfrost_device *pfdev);
int panfrost_gpu_init(struct panfrost_ip *ip);
void panfrost_gpu_fini(struct panfrost_ip *ip);
int panfrost_job_init(struct panfrost_ip *ip);
void panfrost_job_fini(struct panfrost_ip *ip);
int panfrost_mmu_init(struct panfrost_ip *ip);
void panfrost_mmu_fini(struct panfrost_ip *ip);
const char *panfrost_ip_name(struct panfrost_ip *ip);
#endif
// SPDX-License-Identifier: GPL-2.0
/* Copyright 2018 Panfrost Team */
#include <linux/interrupt.h>
#include "panfrost_device.h"
#include "panfrost_gpu.h"
#include "panfrost_regs.h"
#define gpu_write(reg, data) writel(data, ip->iomem + PAN_GPU_##reg)
#define gpu_read(reg) readl(ip->iomem + PAN_GPU_##reg)
static irqreturn_t panfrost_gpu_irq_handler(int irq, void *data)
{
struct panfrost_ip *ip = data;
struct panfrost_device *pfdev = ip->pfdev;
u32 state = gpu_read(INT_STAT);
u32 status = gpu_read(STATUS);
bool done = false;
if (!state)
return IRQ_NONE;
if (state & PAN_GPU_IRQ_MASK_ERROR) {
dev_err(pfdev->dev, "gpu error irq state=%x status=%x\n",
state, status);
gpu_write(INT_MASK, 0);
done = true;
}
gpu_write(INT_CLEAR, state);
return IRQ_HANDLED;
}
static void panfrost_gpu_soft_reset_async(struct panfrost_ip *ip)
{
if (ip->data.async_reset)
return;
gpu_write(INT_MASK, 0);
gpu_write(INT_CLEAR, PAN_GPU_IRQ_RESET_COMPLETED);
gpu_write(CMD, PAN_GPU_CMD_SOFT_RESET);
ip->data.async_reset = true;
}
static int panfrost_gpu_soft_reset_async_wait(struct panfrost_ip *ip)
{
struct panfrost_device *pfdev = ip->pfdev;
int timeout;
if (!ip->data.async_reset)
return 0;
for (timeout = 500; timeout > 0; timeout--) {
if (gpu_read(INT_RAWSTAT) & PAN_GPU_IRQ_RESET_COMPLETED)
break;
}
if (!timeout) {
dev_err(pfdev->dev, "gpu soft reset timed out\n");
return -ETIMEDOUT;
}
gpu_write(INT_CLEAR, PAN_GPU_IRQ_MASK_ALL);
gpu_write(INT_MASK, PAN_GPU_IRQ_MASK_ALL);
ip->data.async_reset = false;
return 0;
}
static void panfrost_gpu_print_version(struct panfrost_ip *ip)
{
u32 version, major, minor;
char *name;
version = gpu_read(VERSION);
switch (version >> 16) {
case 0x750:
name = "mali-t760";
break;
default:
name = "unknown";
break;
}
dev_info(ip->pfdev->dev, "%s - %s version %x\n",
panfrost_ip_name(ip), name, version);
}
int panfrost_gpu_init(struct panfrost_ip *ip)
{
struct panfrost_device *pfdev = ip->pfdev;
int err;
panfrost_gpu_print_version(ip);
ip->data.async_reset = false;
panfrost_gpu_soft_reset_async(ip);
err = panfrost_gpu_soft_reset_async_wait(ip);
if (err)
return err;
err = devm_request_irq(pfdev->dev, ip->irq, panfrost_gpu_irq_handler,
IRQF_SHARED, panfrost_ip_name(ip), ip);
if (err) {
dev_err(pfdev->dev, "gpu %s failed to request irq\n",
panfrost_ip_name(ip));
return err;
}
return 0;
}
......
// SPDX-License-Identifier: GPL-2.0
/* Copyright 2018 Panfrost Team */
#ifndef __PANFROST_GPU_H__
#define __PANFROST_GPU_H__
struct panfrost_ip;
struct panfrost_device;
int panfrost_gpu_init(struct panfrost_ip *ip);
void panfrost_gpu_fini(struct panfrost_ip *ip);
int panfrost_gpu_pipe_init(struct panfrost_device *pfdev);
void panfrost_gpu_pipe_fini(struct panfrost_device *pfdev);
#endif
// SPDX-License-Identifier: GPL-2.0
/* Copyright 2011-2016 ARM Limited. All rights reserved.
* Copyright 2018 Panfrost Team
*/
#ifndef __PANFROST_REGS_H__
#define __PANFROST_REGS_H__
/* This file's register definition is collected from the
* official ARM Mali Midgard GPU kernel driver source code
*/
/* GPU regs */
#define PAN_GPU_VERSION 0x00
#define PAN_GPU_INT_RAWSTAT 0x20
#define PAN_GPU_INT_CLEAR 0x24
#define PAN_GPU_INT_MASK 0x28
#define PAN_GPU_INT_STAT 0x2c
#define PAN_GPU_IRQ_FAULT BIT(0)
#define PAN_GPU_IRQ_MULTIPLE_FAULT BIT(7)
#define PAN_GPU_IRQ_RESET_COMPLETED BIT(8)
#define PAN_GPU_IRQ_POWER_CHANGED BIT(9)
#define PAN_GPU_IRQ_POWER_CHANGED_ALL BIT(10)
#define PAN_GPU_IRQ_PERFCNT_SAMPLE_COMPLETED BIT(16)
#define PAN_GPU_IRQ_CLEAN_CACHES_COMPLETED BIT(17)
#define PAN_GPU_IRQ_MASK_ALL \
( \
PAN_GPU_IRQ_FAULT |\
PAN_GPU_IRQ_MULTIPLE_FAULT |\
PAN_GPU_IRQ_RESET_COMPLETED |\
PAN_GPU_IRQ_POWER_CHANGED |\
PAN_GPU_IRQ_POWER_CHANGED_ALL |\
PAN_GPU_IRQ_PERFCNT_SAMPLE_COMPLETED |\
PAN_GPU_IRQ_CLEAN_CACHES_COMPLETED )
#define PAN_GPU_IRQ_MASK_ERROR \
( \
PAN_GPU_IRQ_FAULT | \
PAN_GPU_IRQ_MULTIPLE_FAULT)
#define PAN_GPU_CMD 0x30
#define PAN_GPU_CMD_SOFT_RESET 0x01
#define PAN_GPU_STATUS 0x34
#endif
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