Commit 6a512726 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Olof Johansson:
 "Volume is a little higher than usual due to a set of gpio fixes for
  Davinci platforms that's been around a while, still seemed appropriate
  to not hold off until next merge window.

  Besides that it's the usual mix of minor fixes, mostly corrections of
  small stuff in device trees.

  Major stability-related one is the removal of a regulator from DT on
  Rock960, since DVFS caused undervoltage. I expect it'll be restored
  once they figure out the underlying issue"

* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (28 commits)
  MAINTAINERS: Remove unused Qualcomm SoC mailing list
  ARM: davinci: dm644x: set the GPIO base to 0
  ARM: davinci: da830: set the GPIO base to 0
  ARM: davinci: dm355: set the GPIO base to 0
  ARM: davinci: dm646x: set the GPIO base to 0
  ARM: davinci: dm365: set the GPIO base to 0
  ARM: davinci: da850: set the GPIO base to 0
  gpio: davinci: restore a way to manually specify the GPIO base
  ARM: davinci: dm644x: define gpio interrupts as separate resources
  ARM: davinci: dm355: define gpio interrupts as separate resources
  ARM: davinci: dm646x: define gpio interrupts as separate resources
  ARM: davinci: dm365: define gpio interrupts as separate resources
  ARM: davinci: da8xx: define gpio interrupts as separate resources
  ARM: dts: at91: sama5d2: use the divided clock for SMC
  ARM: dts: imx51-zii-rdu1: Remove EEPROM node
  ARM: dts: rockchip: Remove @0 from the veyron memory node
  arm64: dts: rockchip: Fix PCIe reset polarity for rk3399-puma-haikou.
  arm64: dts: qcom: msm8998: Reserve gpio ranges on MTP
  arm64: dts: sdm845-mtp: Reserve reserved gpios
  arm64: dts: ti: k3-am654: Fix wakeup_uart reg address
  ...
parents 292974c5 bfed4d73
......@@ -1923,7 +1923,6 @@ ARM/QUALCOMM SUPPORT
M: Andy Gross <andy.gross@linaro.org>
M: David Brown <david.brown@linaro.org>
L: linux-arm-msm@vger.kernel.org
L: linux-soc@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/soc/qcom/
F: arch/arm/boot/dts/qcom-*.dts
......@@ -2931,7 +2930,6 @@ F: arch/mips/include/asm/mach-bcm47xx/*
BROADCOM BCM5301X ARM ARCHITECTURE
M: Hauke Mehrtens <hauke@hauke-m.de>
M: Rafał Miłecki <zajec5@gmail.com>
M: Jon Mason <jonmason@broadcom.com>
M: bcm-kernel-feedback-list@broadcom.com
L: linux-arm-kernel@lists.infradead.org
S: Maintained
......@@ -3077,7 +3075,6 @@ F: drivers/net/ethernet/broadcom/genet/
BROADCOM IPROC ARM ARCHITECTURE
M: Ray Jui <rjui@broadcom.com>
M: Scott Branden <sbranden@broadcom.com>
M: Jon Mason <jonmason@broadcom.com>
M: bcm-kernel-feedback-list@broadcom.com
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
T: git git://github.com/broadcom/cygnus-linux.git
......
......@@ -228,7 +228,7 @@
vmmc-supply = <&vmmc_fixed>;
bus-width = <4>;
wp-gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; /* gpio_126 */
cd-gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>; /* gpio_127 */
cd-gpios = <&gpio4 31 GPIO_ACTIVE_LOW>; /* gpio_127 */
};
&mmc3 {
......
......@@ -163,7 +163,7 @@
compatible = "ti,wl1271";
reg = <2>;
interrupt-parent = <&gpio6>;
interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; /* gpio_170 */
interrupts = <10 IRQ_TYPE_EDGE_RISING>; /* gpio_170 */
ref-clock-frequency = <26000000>;
tcxo-clock-frequency = <26000000>;
};
......
......@@ -492,12 +492,6 @@
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
eeprom@50 {
compatible = "atmel,24c04";
pagesize = <16>;
reg = <0x50>;
};
hpa1: amp@60 {
compatible = "ti,tpa6130a2";
reg = <0x60>;
......
......@@ -129,7 +129,7 @@
};
&mmc3 {
interrupts-extended = <&intc 94 &omap3_pmx_core2 0x46>;
interrupts-extended = <&intc 94 &omap3_pmx_core 0x136>;
pinctrl-0 = <&mmc3_pins &wl127x_gpio>;
pinctrl-names = "default";
vmmc-supply = <&wl12xx_vmmc>;
......
......@@ -35,7 +35,7 @@
* jumpering combinations for the long run.
*/
&mmc3 {
interrupts-extended = <&intc 94 &omap3_pmx_core2 0x46>;
interrupts-extended = <&intc 94 &omap3_pmx_core 0x136>;
pinctrl-0 = <&mmc3_pins &mmc3_core2_pins>;
pinctrl-names = "default";
vmmc-supply = <&wl12xx_vmmc>;
......
......@@ -10,7 +10,11 @@
#include "rk3288.dtsi"
/ {
memory@0 {
/*
* The default coreboot on veyron devices ignores memory@0 nodes
* and would instead create another memory node.
*/
memory {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
......
......@@ -314,7 +314,7 @@
0x1 0x0 0x60000000 0x10000000
0x2 0x0 0x70000000 0x10000000
0x3 0x0 0x80000000 0x10000000>;
clocks = <&mck>;
clocks = <&h32ck>;
status = "disabled";
nand_controller: nand-controller {
......
......@@ -759,7 +759,9 @@ static struct davinci_id da830_ids[] = {
};
static struct davinci_gpio_platform_data da830_gpio_platform_data = {
.ngpio = 128,
.no_auto_base = true,
.base = 0,
.ngpio = 128,
};
int __init da830_register_gpio(void)
......
......@@ -719,7 +719,9 @@ int __init da850_register_vpif_capture(struct vpif_capture_config
}
static struct davinci_gpio_platform_data da850_gpio_platform_data = {
.ngpio = 144,
.no_auto_base = true,
.base = 0,
.ngpio = 144,
};
int __init da850_register_gpio(void)
......
......@@ -701,6 +701,46 @@ static struct resource da8xx_gpio_resources[] = {
},
{ /* interrupt */
.start = IRQ_DA8XX_GPIO0,
.end = IRQ_DA8XX_GPIO0,
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DA8XX_GPIO1,
.end = IRQ_DA8XX_GPIO1,
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DA8XX_GPIO2,
.end = IRQ_DA8XX_GPIO2,
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DA8XX_GPIO3,
.end = IRQ_DA8XX_GPIO3,
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DA8XX_GPIO4,
.end = IRQ_DA8XX_GPIO4,
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DA8XX_GPIO5,
.end = IRQ_DA8XX_GPIO5,
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DA8XX_GPIO6,
.end = IRQ_DA8XX_GPIO6,
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DA8XX_GPIO7,
.end = IRQ_DA8XX_GPIO7,
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DA8XX_GPIO8,
.end = IRQ_DA8XX_GPIO8,
.flags = IORESOURCE_IRQ,
},
......
......@@ -548,12 +548,44 @@ static struct resource dm355_gpio_resources[] = {
},
{ /* interrupt */
.start = IRQ_DM355_GPIOBNK0,
.end = IRQ_DM355_GPIOBNK0,
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DM355_GPIOBNK1,
.end = IRQ_DM355_GPIOBNK1,
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DM355_GPIOBNK2,
.end = IRQ_DM355_GPIOBNK2,
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DM355_GPIOBNK3,
.end = IRQ_DM355_GPIOBNK3,
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DM355_GPIOBNK4,
.end = IRQ_DM355_GPIOBNK4,
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DM355_GPIOBNK5,
.end = IRQ_DM355_GPIOBNK5,
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DM355_GPIOBNK6,
.end = IRQ_DM355_GPIOBNK6,
.flags = IORESOURCE_IRQ,
},
};
static struct davinci_gpio_platform_data dm355_gpio_platform_data = {
.no_auto_base = true,
.base = 0,
.ngpio = 104,
};
......
......@@ -267,12 +267,49 @@ static struct resource dm365_gpio_resources[] = {
},
{ /* interrupt */
.start = IRQ_DM365_GPIO0,
.end = IRQ_DM365_GPIO0,
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DM365_GPIO1,
.end = IRQ_DM365_GPIO1,
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DM365_GPIO2,
.end = IRQ_DM365_GPIO2,
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DM365_GPIO3,
.end = IRQ_DM365_GPIO3,
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DM365_GPIO4,
.end = IRQ_DM365_GPIO4,
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DM365_GPIO5,
.end = IRQ_DM365_GPIO5,
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DM365_GPIO6,
.end = IRQ_DM365_GPIO6,
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DM365_GPIO7,
.end = IRQ_DM365_GPIO7,
.flags = IORESOURCE_IRQ,
},
};
static struct davinci_gpio_platform_data dm365_gpio_platform_data = {
.no_auto_base = true,
.base = 0,
.ngpio = 104,
.gpio_unbanked = 8,
};
......
......@@ -492,12 +492,34 @@ static struct resource dm644_gpio_resources[] = {
},
{ /* interrupt */
.start = IRQ_GPIOBNK0,
.end = IRQ_GPIOBNK0,
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_GPIOBNK1,
.end = IRQ_GPIOBNK1,
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_GPIOBNK2,
.end = IRQ_GPIOBNK2,
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_GPIOBNK3,
.end = IRQ_GPIOBNK3,
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_GPIOBNK4,
.end = IRQ_GPIOBNK4,
.flags = IORESOURCE_IRQ,
},
};
static struct davinci_gpio_platform_data dm644_gpio_platform_data = {
.no_auto_base = true,
.base = 0,
.ngpio = 71,
};
......
......@@ -442,12 +442,24 @@ static struct resource dm646x_gpio_resources[] = {
},
{ /* interrupt */
.start = IRQ_DM646X_GPIOBNK0,
.end = IRQ_DM646X_GPIOBNK0,
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DM646X_GPIOBNK1,
.end = IRQ_DM646X_GPIOBNK1,
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DM646X_GPIOBNK2,
.end = IRQ_DM646X_GPIOBNK2,
.flags = IORESOURCE_IRQ,
},
};
static struct davinci_gpio_platform_data dm646x_gpio_platform_data = {
.no_auto_base = true,
.base = 0,
.ngpio = 43,
};
......
......@@ -750,6 +750,9 @@ static void modem_pm(struct uart_port *port, unsigned int state, unsigned old)
struct modem_private_data *priv = port->private_data;
int ret;
if (!priv)
return;
if (IS_ERR(priv->regulator))
return;
......
......@@ -351,7 +351,7 @@ static void omap44xx_prm_reconfigure_io_chain(void)
* to occur, WAKEUPENABLE bits must be set in the pad mux registers, and
* omap44xx_prm_reconfigure_io_chain() must be called. No return value.
*/
static void __init omap44xx_prm_enable_io_wakeup(void)
static void omap44xx_prm_enable_io_wakeup(void)
{
s32 inst = omap4_prmst_get_prm_dev_inst();
......
......@@ -241,3 +241,7 @@
};
};
};
&tlmm {
gpio-reserved-ranges = <0 4>, <81 4>;
};
......@@ -352,6 +352,10 @@
status = "okay";
};
&tlmm {
gpio-reserved-ranges = <0 4>, <81 4>;
};
&uart9 {
status = "okay";
};
......
......@@ -153,7 +153,7 @@
};
&pcie0 {
ep-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>;
ep-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
num-lanes = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_clkreqn_cpm>;
......
......@@ -57,18 +57,6 @@
regulator-always-on;
vin-supply = <&vcc_sys>;
};
vdd_log: vdd-log {
compatible = "pwm-regulator";
pwms = <&pwm2 0 25000 0>;
regulator-name = "vdd_log";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc_sys>;
};
};
&cpu_l0 {
......
......@@ -36,7 +36,7 @@
wkup_uart0: serial@42300000 {
compatible = "ti,am654-uart";
reg = <0x00 0x42300000 0x00 0x100>;
reg = <0x42300000 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
......
......@@ -258,7 +258,7 @@ static int davinci_gpio_probe(struct platform_device *pdev)
chips->chip.set = davinci_gpio_set;
chips->chip.ngpio = ngpio;
chips->chip.base = -1;
chips->chip.base = pdata->no_auto_base ? pdata->base : -1;
#ifdef CONFIG_OF_GPIO
chips->chip.of_gpio_n_cells = 2;
......
......@@ -17,6 +17,8 @@
#define __DAVINCI_GPIO_PLATFORM_H
struct davinci_gpio_platform_data {
bool no_auto_base;
u32 base;
u32 ngpio;
u32 gpio_unbanked;
};
......
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