Commit 4c4231ea authored by Thomas Gleixner's avatar Thomas Gleixner Committed by James Bottomley

[PARISC] Convert to new irq_chip functions

Convert all the parisc driver interrupt handlers (dino, eisa, gsc,
iosapic and superio) as well as the cpu interrupts.  Prepare
show_interrupts for GENERIC_HARDIRQS_NO_DEPRECATED and finally selects
that Kconfig option

[jejb: compile and testing fixes]
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Signed-off-by: default avatarJames Bottomley <James.Bottomley@suse.de>
parent 9804c9ea
......@@ -15,6 +15,7 @@ config PARISC
select HAVE_GENERIC_HARDIRQS
select GENERIC_IRQ_PROBE
select IRQ_PER_CPU
select GENERIC_HARDIRQS_NO_DEPRECATED
help
The PA-RISC microprocessor is designed by Hewlett-Packard and used
......
......@@ -32,15 +32,10 @@ static __inline__ int irq_canonicalize(int irq)
}
struct irq_chip;
struct irq_data;
/*
* Some useful "we don't have to do anything here" handlers. Should
* probably be provided by the generic code.
*/
void no_ack_irq(unsigned int irq);
void no_end_irq(unsigned int irq);
void cpu_ack_irq(unsigned int irq);
void cpu_eoi_irq(unsigned int irq);
void cpu_ack_irq(struct irq_data *d);
void cpu_eoi_irq(struct irq_data *d);
extern int txn_alloc_irq(unsigned int nbits);
extern int txn_claim_irq(int);
......@@ -49,7 +44,7 @@ extern unsigned long txn_alloc_addr(unsigned int);
extern unsigned long txn_affinity_addr(unsigned int irq, int cpu);
extern int cpu_claim_irq(unsigned int irq, struct irq_chip *, void *);
extern int cpu_check_affinity(unsigned int irq, const struct cpumask *dest);
extern int cpu_check_affinity(struct irq_data *d, const struct cpumask *dest);
/* soft power switch support (power.c) */
extern struct tasklet_struct power_tasklet;
......
......@@ -52,9 +52,9 @@ static volatile unsigned long cpu_eiem = 0;
*/
static DEFINE_PER_CPU(unsigned long, local_ack_eiem) = ~0UL;
static void cpu_mask_irq(unsigned int irq)
static void cpu_mask_irq(struct irq_data *d)
{
unsigned long eirr_bit = EIEM_MASK(irq);
unsigned long eirr_bit = EIEM_MASK(d->irq);
cpu_eiem &= ~eirr_bit;
/* Do nothing on the other CPUs. If they get this interrupt,
......@@ -63,7 +63,7 @@ static void cpu_mask_irq(unsigned int irq)
* then gets disabled */
}
static void cpu_unmask_irq(unsigned int irq)
static void __cpu_unmask_irq(unsigned int irq)
{
unsigned long eirr_bit = EIEM_MASK(irq);
......@@ -75,9 +75,14 @@ static void cpu_unmask_irq(unsigned int irq)
smp_send_all_nop();
}
void cpu_ack_irq(unsigned int irq)
static void cpu_unmask_irq(struct irq_data *d)
{
unsigned long mask = EIEM_MASK(irq);
__cpu_unmask_irq(d->irq);
}
void cpu_ack_irq(struct irq_data *d)
{
unsigned long mask = EIEM_MASK(d->irq);
int cpu = smp_processor_id();
/* Clear in EIEM so we can no longer process */
......@@ -90,9 +95,9 @@ void cpu_ack_irq(unsigned int irq)
mtctl(mask, 23);
}
void cpu_eoi_irq(unsigned int irq)
void cpu_eoi_irq(struct irq_data *d)
{
unsigned long mask = EIEM_MASK(irq);
unsigned long mask = EIEM_MASK(d->irq);
int cpu = smp_processor_id();
/* set it in the eiems---it's no longer in process */
......@@ -103,15 +108,16 @@ void cpu_eoi_irq(unsigned int irq)
}
#ifdef CONFIG_SMP
int cpu_check_affinity(unsigned int irq, const struct cpumask *dest)
int cpu_check_affinity(struct irq_data *d, const struct cpumask *dest)
{
int cpu_dest;
/* timer and ipi have to always be received on all CPUs */
if (CHECK_IRQ_PER_CPU(irq_to_desc(irq)->status)) {
if (CHECK_IRQ_PER_CPU(irq_to_desc(d->irq)->status)) {
/* Bad linux design decision. The mask has already
* been set; we must reset it */
cpumask_setall(irq_desc[irq].affinity);
* been set; we must reset it. Will fix - tglx
*/
cpumask_setall(d->affinity);
return -EINVAL;
}
......@@ -121,15 +127,16 @@ int cpu_check_affinity(unsigned int irq, const struct cpumask *dest)
return cpu_dest;
}
static int cpu_set_affinity_irq(unsigned int irq, const struct cpumask *dest)
static int cpu_set_affinity_irq(struct irq_data *d, const struct cpumask *dest,
bool force)
{
int cpu_dest;
cpu_dest = cpu_check_affinity(irq, dest);
cpu_dest = cpu_check_affinity(d, dest);
if (cpu_dest < 0)
return -1;
cpumask_copy(irq_desc[irq].affinity, dest);
cpumask_copy(d->affinity, dest);
return 0;
}
......@@ -137,17 +144,17 @@ static int cpu_set_affinity_irq(unsigned int irq, const struct cpumask *dest)
static struct irq_chip cpu_interrupt_type = {
.name = "CPU",
.mask = cpu_mask_irq,
.unmask = cpu_unmask_irq,
.ack = cpu_ack_irq,
.eoi = cpu_eoi_irq,
.irq_mask = cpu_mask_irq,
.irq_unmask = cpu_unmask_irq,
.irq_ack = cpu_ack_irq,
.irq_eoi = cpu_eoi_irq,
#ifdef CONFIG_SMP
.set_affinity = cpu_set_affinity_irq,
.irq_set_affinity = cpu_set_affinity_irq,
#endif
/* XXX: Needs to be written. We managed without it so far, but
* we really ought to write it.
*/
.retrigger = NULL,
.irq_retrigger = NULL,
};
int show_interrupts(struct seq_file *p, void *v)
......@@ -181,7 +188,7 @@ int show_interrupts(struct seq_file *p, void *v)
seq_printf(p, "%10u ", kstat_irqs(i));
#endif
seq_printf(p, " %14s", irq_desc[i].chip->name);
seq_printf(p, " %14s", irq_desc[i].irq_data.chip->name);
#ifndef PARISC_IRQ_CR16_COUNTS
seq_printf(p, " %s", action->name);
......@@ -233,14 +240,14 @@ int cpu_claim_irq(unsigned int irq, struct irq_chip *type, void *data)
{
if (irq_desc[irq].action)
return -EBUSY;
if (irq_desc[irq].chip != &cpu_interrupt_type)
if (get_irq_chip(irq) != &cpu_interrupt_type)
return -EBUSY;
/* for iosapic interrupts */
if (type) {
set_irq_chip_and_handler(irq, type, handle_percpu_irq);
set_irq_chip_data(irq, data);
cpu_unmask_irq(irq);
__cpu_unmask_irq(irq);
}
return 0;
}
......@@ -289,7 +296,8 @@ int txn_alloc_irq(unsigned int bits_wide)
unsigned long txn_affinity_addr(unsigned int irq, int cpu)
{
#ifdef CONFIG_SMP
cpumask_copy(irq_desc[irq].affinity, cpumask_of(cpu));
struct irq_data *d = irq_get_irq_data(irq);
cpumask_copy(d->affinity, cpumask_of(cpu));
#endif
return per_cpu(cpu_data, cpu).txn_addr;
......@@ -333,6 +341,7 @@ void do_cpu_irq_mask(struct pt_regs *regs)
unsigned long eirr_val;
int irq, cpu = smp_processor_id();
#ifdef CONFIG_SMP
struct irq_desc *desc;
cpumask_t dest;
#endif
......@@ -346,8 +355,9 @@ void do_cpu_irq_mask(struct pt_regs *regs)
irq = eirr_to_irq(eirr_val);
#ifdef CONFIG_SMP
cpumask_copy(&dest, irq_desc[irq].affinity);
if (CHECK_IRQ_PER_CPU(irq_desc[irq].status) &&
desc = irq_to_desc(irq);
cpumask_copy(&dest, desc->irq_data.affinity);
if (CHECK_IRQ_PER_CPU(desc->status) &&
!cpu_isset(smp_processor_id(), dest)) {
int cpu = first_cpu(dest);
......
......@@ -296,25 +296,25 @@ static struct pci_port_ops dino_port_ops = {
.outl = dino_out32
};
static void dino_mask_irq(unsigned int irq)
static void dino_mask_irq(struct irq_data *d)
{
struct dino_device *dino_dev = get_irq_chip_data(irq);
int local_irq = gsc_find_local_irq(irq, dino_dev->global_irq, DINO_LOCAL_IRQS);
struct dino_device *dino_dev = irq_data_get_irq_chip_data(d);
int local_irq = gsc_find_local_irq(d->irq, dino_dev->global_irq, DINO_LOCAL_IRQS);
DBG(KERN_WARNING "%s(0x%p, %d)\n", __func__, dino_dev, irq);
DBG(KERN_WARNING "%s(0x%p, %d)\n", __func__, dino_dev, d->irq);
/* Clear the matching bit in the IMR register */
dino_dev->imr &= ~(DINO_MASK_IRQ(local_irq));
__raw_writel(dino_dev->imr, dino_dev->hba.base_addr+DINO_IMR);
}
static void dino_unmask_irq(unsigned int irq)
static void dino_unmask_irq(struct irq_data *d)
{
struct dino_device *dino_dev = get_irq_chip_data(irq);
int local_irq = gsc_find_local_irq(irq, dino_dev->global_irq, DINO_LOCAL_IRQS);
struct dino_device *dino_dev = irq_data_get_irq_chip_data(d);
int local_irq = gsc_find_local_irq(d->irq, dino_dev->global_irq, DINO_LOCAL_IRQS);
u32 tmp;
DBG(KERN_WARNING "%s(0x%p, %d)\n", __func__, dino_dev, irq);
DBG(KERN_WARNING "%s(0x%p, %d)\n", __func__, dino_dev, d->irq);
/*
** clear pending IRQ bits
......@@ -347,8 +347,8 @@ static void dino_unmask_irq(unsigned int irq)
static struct irq_chip dino_interrupt_type = {
.name = "GSC-PCI",
.unmask = dino_unmask_irq,
.mask = dino_mask_irq,
.irq_unmask = dino_unmask_irq,
.irq_mask = dino_mask_irq,
};
......
......@@ -144,8 +144,9 @@ static unsigned int eisa_irq_level __read_mostly; /* default to edge triggered *
/* called by free irq */
static void eisa_mask_irq(unsigned int irq)
static void eisa_mask_irq(struct irq_data *d)
{
unsigned int irq = d->irq;
unsigned long flags;
EISA_DBG("disable irq %d\n", irq);
......@@ -164,8 +165,9 @@ static void eisa_mask_irq(unsigned int irq)
}
/* called by request irq */
static void eisa_unmask_irq(unsigned int irq)
static void eisa_unmask_irq(struct irq_data *d)
{
unsigned int irq = d->irq;
unsigned long flags;
EISA_DBG("enable irq %d\n", irq);
......@@ -184,8 +186,8 @@ static void eisa_unmask_irq(unsigned int irq)
static struct irq_chip eisa_interrupt_type = {
.name = "EISA",
.unmask = eisa_unmask_irq,
.mask = eisa_mask_irq,
.irq_unmask = eisa_unmask_irq,
.irq_mask = eisa_mask_irq,
};
static irqreturn_t eisa_irq(int wax_irq, void *intr_dev)
......
......@@ -105,13 +105,13 @@ int gsc_find_local_irq(unsigned int irq, int *global_irqs, int limit)
return NO_IRQ;
}
static void gsc_asic_mask_irq(unsigned int irq)
static void gsc_asic_mask_irq(struct irq_data *d)
{
struct gsc_asic *irq_dev = get_irq_chip_data(irq);
int local_irq = gsc_find_local_irq(irq, irq_dev->global_irq, 32);
struct gsc_asic *irq_dev = irq_data_get_irq_chip_data(d);
int local_irq = gsc_find_local_irq(d->irq, irq_dev->global_irq, 32);
u32 imr;
DEBPRINTK(KERN_DEBUG "%s(%d) %s: IMR 0x%x\n", __func__, irq,
DEBPRINTK(KERN_DEBUG "%s(%d) %s: IMR 0x%x\n", __func__, d->irq,
irq_dev->name, imr);
/* Disable the IRQ line by clearing the bit in the IMR */
......@@ -120,13 +120,13 @@ static void gsc_asic_mask_irq(unsigned int irq)
gsc_writel(imr, irq_dev->hpa + OFFSET_IMR);
}
static void gsc_asic_unmask_irq(unsigned int irq)
static void gsc_asic_unmask_irq(struct irq_data *d)
{
struct gsc_asic *irq_dev = get_irq_chip_data(irq);
int local_irq = gsc_find_local_irq(irq, irq_dev->global_irq, 32);
struct gsc_asic *irq_dev = irq_data_get_irq_chip_data(d);
int local_irq = gsc_find_local_irq(d->irq, irq_dev->global_irq, 32);
u32 imr;
DEBPRINTK(KERN_DEBUG "%s(%d) %s: IMR 0x%x\n", __func__, irq,
DEBPRINTK(KERN_DEBUG "%s(%d) %s: IMR 0x%x\n", __func__, d->irq,
irq_dev->name, imr);
/* Enable the IRQ line by setting the bit in the IMR */
......@@ -141,8 +141,8 @@ static void gsc_asic_unmask_irq(unsigned int irq)
static struct irq_chip gsc_asic_interrupt_type = {
.name = "GSC-ASIC",
.unmask = gsc_asic_unmask_irq,
.mask = gsc_asic_mask_irq,
.irq_unmask = gsc_asic_unmask_irq,
.irq_mask = gsc_asic_mask_irq,
};
int gsc_assign_irq(struct irq_chip *type, void *data)
......
......@@ -615,10 +615,10 @@ iosapic_set_irt_data( struct vector_info *vi, u32 *dp0, u32 *dp1)
}
static void iosapic_mask_irq(unsigned int irq)
static void iosapic_mask_irq(struct irq_data *d)
{
unsigned long flags;
struct vector_info *vi = get_irq_chip_data(irq);
struct vector_info *vi = irq_data_get_irq_chip_data(d);
u32 d0, d1;
spin_lock_irqsave(&iosapic_lock, flags);
......@@ -628,9 +628,9 @@ static void iosapic_mask_irq(unsigned int irq)
spin_unlock_irqrestore(&iosapic_lock, flags);
}
static void iosapic_unmask_irq(unsigned int irq)
static void iosapic_unmask_irq(struct irq_data *d)
{
struct vector_info *vi = get_irq_chip_data(irq);
struct vector_info *vi = irq_data_get_irq_chip_data(d);
u32 d0, d1;
/* data is initialized by fixup_irq */
......@@ -666,34 +666,34 @@ printk("\n");
* enables their IRQ. It can lead to "interesting" race conditions
* in the driver initialization sequence.
*/
DBG(KERN_DEBUG "enable_irq(%d): eoi(%p, 0x%x)\n", irq,
DBG(KERN_DEBUG "enable_irq(%d): eoi(%p, 0x%x)\n", d->irq,
vi->eoi_addr, vi->eoi_data);
iosapic_eoi(vi->eoi_addr, vi->eoi_data);
}
static void iosapic_eoi_irq(unsigned int irq)
static void iosapic_eoi_irq(struct irq_data *d)
{
struct vector_info *vi = get_irq_chip_data(irq);
struct vector_info *vi = irq_data_get_irq_chip_data(d);
iosapic_eoi(vi->eoi_addr, vi->eoi_data);
cpu_eoi_irq(irq);
cpu_eoi_irq(d);
}
#ifdef CONFIG_SMP
static int iosapic_set_affinity_irq(unsigned int irq,
const struct cpumask *dest)
static int iosapic_set_affinity_irq(struct irq_data *d,
const struct cpumask *dest, bool force)
{
struct vector_info *vi = get_irq_chip_data(irq);
struct vector_info *vi = irq_data_get_irq_chip_data(d);
u32 d0, d1, dummy_d0;
unsigned long flags;
int dest_cpu;
dest_cpu = cpu_check_affinity(irq, dest);
dest_cpu = cpu_check_affinity(d, dest);
if (dest_cpu < 0)
return -1;
cpumask_copy(irq_desc[irq].affinity, cpumask_of(dest_cpu));
vi->txn_addr = txn_affinity_addr(irq, dest_cpu);
cpumask_copy(d->affinity, cpumask_of(dest_cpu));
vi->txn_addr = txn_affinity_addr(d->irq, dest_cpu);
spin_lock_irqsave(&iosapic_lock, flags);
/* d1 contains the destination CPU, so only want to set that
......@@ -709,12 +709,12 @@ static int iosapic_set_affinity_irq(unsigned int irq,
static struct irq_chip iosapic_interrupt_type = {
.name = "IO-SAPIC-level",
.unmask = iosapic_unmask_irq,
.mask = iosapic_mask_irq,
.ack = cpu_ack_irq,
.eoi = iosapic_eoi_irq,
.irq_unmask = iosapic_unmask_irq,
.irq_mask = iosapic_mask_irq,
.irq_ack = cpu_ack_irq,
.irq_eoi = iosapic_eoi_irq,
#ifdef CONFIG_SMP
.set_affinity = iosapic_set_affinity_irq,
.irq_set_affinity = iosapic_set_affinity_irq,
#endif
};
......
......@@ -286,8 +286,9 @@ superio_init(struct pci_dev *pcidev)
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_87560_LIO, superio_init);
static void superio_mask_irq(unsigned int irq)
static void superio_mask_irq(struct irq_data *d)
{
unsigned int irq = d->irq;
u8 r8;
if ((irq < 1) || (irq == 2) || (irq > 7)) {
......@@ -303,8 +304,9 @@ static void superio_mask_irq(unsigned int irq)
outb (r8,IC_PIC1+1);
}
static void superio_unmask_irq(unsigned int irq)
static void superio_unmask_irq(struct irq_data *d)
{
unsigned int irq = d->irq;
u8 r8;
if ((irq < 1) || (irq == 2) || (irq > 7)) {
......@@ -321,8 +323,8 @@ static void superio_unmask_irq(unsigned int irq)
static struct irq_chip superio_interrupt_type = {
.name = SUPERIO,
.unmask = superio_unmask_irq,
.mask = superio_mask_irq,
.irq_unmask = superio_unmask_irq,
.irq_mask = superio_mask_irq,
};
#ifdef DEBUG_SUPERIO_INIT
......
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