Commit 241771ef authored by Ingo Molnar's avatar Ingo Molnar

performance counters: x86 support

Implement performance counters for x86 Intel CPUs.

It's simplified right now: the PERFMON CPU feature is assumed,
which is available in Core2 and later Intel CPUs.

The design is flexible to be extended to more CPU types as well.
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent e7bc62b6
......@@ -643,6 +643,7 @@ config X86_UP_IOAPIC
config X86_LOCAL_APIC
def_bool y
depends on X86_64 || (X86_32 && (X86_UP_APIC || (SMP && !X86_VOYAGER) || X86_GENERICARCH))
select HAVE_PERF_COUNTERS
config X86_IO_APIC
def_bool y
......
......@@ -823,7 +823,8 @@ ia32_sys_call_table:
.quad compat_sys_signalfd4
.quad sys_eventfd2
.quad sys_epoll_create1
.quad sys_dup3 /* 330 */
.quad sys_dup3 /* 330 */
.quad sys_pipe2
.quad sys_inotify_init1
.quad sys_perf_counter_open
ia32_syscall_end:
......@@ -9,6 +9,7 @@ typedef struct {
unsigned long idle_timestamp;
unsigned int __nmi_count; /* arch dependent */
unsigned int apic_timer_irqs; /* arch dependent */
unsigned int apic_perf_irqs; /* arch dependent */
unsigned int irq0_irqs;
unsigned int irq_resched_count;
unsigned int irq_call_count;
......
......@@ -30,6 +30,8 @@
/* Interrupt handlers registered during init_IRQ */
extern void apic_timer_interrupt(void);
extern void error_interrupt(void);
extern void perf_counter_interrupt(void);
extern void spurious_interrupt(void);
extern void thermal_interrupt(void);
extern void reschedule_interrupt(void);
......
#ifndef _ASM_X86_INTEL_ARCH_PERFMON_H
#define _ASM_X86_INTEL_ARCH_PERFMON_H
#define MSR_ARCH_PERFMON_PERFCTR0 0xc1
#define MSR_ARCH_PERFMON_PERFCTR1 0xc2
#define MSR_ARCH_PERFMON_PERFCTR0 0xc1
#define MSR_ARCH_PERFMON_PERFCTR1 0xc2
#define MSR_ARCH_PERFMON_EVENTSEL0 0x186
#define MSR_ARCH_PERFMON_EVENTSEL1 0x187
#define MSR_ARCH_PERFMON_EVENTSEL0 0x186
#define MSR_ARCH_PERFMON_EVENTSEL1 0x187
#define ARCH_PERFMON_EVENTSEL0_ENABLE (1 << 22)
#define ARCH_PERFMON_EVENTSEL_INT (1 << 20)
#define ARCH_PERFMON_EVENTSEL_OS (1 << 17)
#define ARCH_PERFMON_EVENTSEL_USR (1 << 16)
#define ARCH_PERFMON_EVENTSEL0_ENABLE (1 << 22)
#define ARCH_PERFMON_EVENTSEL_INT (1 << 20)
#define ARCH_PERFMON_EVENTSEL_OS (1 << 17)
#define ARCH_PERFMON_EVENTSEL_USR (1 << 16)
#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL (0x3c)
#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK (0x00 << 8)
#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX (0)
#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL 0x3c
#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK (0x00 << 8)
#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX 0
#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT \
(1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX))
(1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX))
#define ARCH_PERFMON_BRANCH_MISSES_RETIRED 6
union cpuid10_eax {
struct {
......@@ -28,4 +30,12 @@ union cpuid10_eax {
unsigned int full;
};
#ifdef CONFIG_PERF_COUNTERS
extern void init_hw_perf_counters(void);
extern void perf_counters_lapic_init(int nmi);
#else
static inline void init_hw_perf_counters(void) { }
static inline void perf_counters_lapic_init(int nmi) { }
#endif
#endif /* _ASM_X86_INTEL_ARCH_PERFMON_H */
......@@ -86,6 +86,11 @@
*/
#define LOCAL_TIMER_VECTOR 0xef
/*
* Performance monitoring interrupt vector:
*/
#define LOCAL_PERF_VECTOR 0xee
/*
* First APIC vector available to drivers: (vectors 0x30-0xee) we
* start at 0x31(0x41) to spread out vectors evenly between priority
......
......@@ -25,10 +25,15 @@ BUILD_INTERRUPT(irq_move_cleanup_interrupt,IRQ_MOVE_CLEANUP_VECTOR)
* a much simpler SMP time architecture:
*/
#ifdef CONFIG_X86_LOCAL_APIC
BUILD_INTERRUPT(apic_timer_interrupt,LOCAL_TIMER_VECTOR)
BUILD_INTERRUPT(error_interrupt,ERROR_APIC_VECTOR)
BUILD_INTERRUPT(spurious_interrupt,SPURIOUS_APIC_VECTOR)
#ifdef CONFIG_PERF_COUNTERS
BUILD_INTERRUPT(perf_counter_interrupt, LOCAL_PERF_VECTOR)
#endif
#ifdef CONFIG_X86_MCE_P4THERMAL
BUILD_INTERRUPT(thermal_interrupt,THERMAL_APIC_VECTOR)
#endif
......
......@@ -30,6 +30,7 @@ struct x8664_pda {
short isidle;
struct mm_struct *active_mm;
unsigned apic_timer_irqs;
unsigned apic_perf_irqs;
unsigned irq0_irqs;
unsigned irq_resched_count;
unsigned irq_call_count;
......
......@@ -80,6 +80,7 @@ struct thread_info {
#define TIF_SYSCALL_AUDIT 7 /* syscall auditing active */
#define TIF_SECCOMP 8 /* secure computing */
#define TIF_MCE_NOTIFY 10 /* notify userspace of an MCE */
#define TIF_PERF_COUNTERS 11 /* notify perf counter work */
#define TIF_NOTSC 16 /* TSC is not accessible in userland */
#define TIF_IA32 17 /* 32bit process */
#define TIF_FORK 18 /* ret_from_fork */
......@@ -103,6 +104,7 @@ struct thread_info {
#define _TIF_SYSCALL_AUDIT (1 << TIF_SYSCALL_AUDIT)
#define _TIF_SECCOMP (1 << TIF_SECCOMP)
#define _TIF_MCE_NOTIFY (1 << TIF_MCE_NOTIFY)
#define _TIF_PERF_COUNTERS (1 << TIF_PERF_COUNTERS)
#define _TIF_NOTSC (1 << TIF_NOTSC)
#define _TIF_IA32 (1 << TIF_IA32)
#define _TIF_FORK (1 << TIF_FORK)
......@@ -135,7 +137,7 @@ struct thread_info {
/* Only used for 64 bit */
#define _TIF_DO_NOTIFY_MASK \
(_TIF_SIGPENDING|_TIF_MCE_NOTIFY|_TIF_NOTIFY_RESUME)
(_TIF_SIGPENDING|_TIF_MCE_NOTIFY|_TIF_PERF_COUNTERS|_TIF_NOTIFY_RESUME)
/* flags to check in __switch_to() */
#define _TIF_WORK_CTXSW \
......
......@@ -338,6 +338,7 @@
#define __NR_dup3 330
#define __NR_pipe2 331
#define __NR_inotify_init1 332
#define __NR_perf_counter_open 333
#ifdef __KERNEL__
......
......@@ -653,7 +653,8 @@ __SYSCALL(__NR_dup3, sys_dup3)
__SYSCALL(__NR_pipe2, sys_pipe2)
#define __NR_inotify_init1 294
__SYSCALL(__NR_inotify_init1, sys_inotify_init1)
#define __NR_perf_counter_open 295
__SYSCALL(__NR_perf_counter_open, sys_perf_counter_open)
#ifndef __NO_STUBS
#define __ARCH_WANT_OLD_READDIR
......
......@@ -31,6 +31,7 @@
#include <linux/dmi.h>
#include <linux/dmar.h>
#include <asm/intel_arch_perfmon.h>
#include <asm/atomic.h>
#include <asm/smp.h>
#include <asm/mtrr.h>
......@@ -1147,6 +1148,7 @@ void __cpuinit setup_local_APIC(void)
apic_write(APIC_ESR, 0);
}
#endif
perf_counters_lapic_init(0);
preempt_disable();
......
#
# Makefile for x86-compatible CPU details and quirks
# Makefile for x86-compatible CPU details, features and quirks
#
obj-y := intel_cacheinfo.o addon_cpuid_features.o
......@@ -16,11 +16,13 @@ obj-$(CONFIG_CPU_SUP_CENTAUR_64) += centaur_64.o
obj-$(CONFIG_CPU_SUP_TRANSMETA_32) += transmeta.o
obj-$(CONFIG_CPU_SUP_UMC_32) += umc.o
obj-$(CONFIG_X86_MCE) += mcheck/
obj-$(CONFIG_MTRR) += mtrr/
obj-$(CONFIG_CPU_FREQ) += cpufreq/
obj-$(CONFIG_PERF_COUNTERS) += perf_counter.o
obj-$(CONFIG_X86_LOCAL_APIC) += perfctr-watchdog.o
obj-$(CONFIG_X86_MCE) += mcheck/
obj-$(CONFIG_MTRR) += mtrr/
obj-$(CONFIG_CPU_FREQ) += cpufreq/
obj-$(CONFIG_X86_LOCAL_APIC) += perfctr-watchdog.o
quiet_cmd_mkcapflags = MKCAP $@
cmd_mkcapflags = $(PERL) $(srctree)/$(src)/mkcapflags.pl $< $@
......
......@@ -17,6 +17,7 @@
#include <asm/mmu_context.h>
#include <asm/mtrr.h>
#include <asm/mce.h>
#include <asm/intel_arch_perfmon.h>
#include <asm/pat.h>
#include <asm/asm.h>
#include <asm/numa.h>
......@@ -750,6 +751,7 @@ void __init identify_boot_cpu(void)
#else
vgetcpu_set_mode();
#endif
init_hw_perf_counters();
}
void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
......
/*
* Performance counter x86 architecture code
*
* Copyright(C) 2008 Thomas Gleixner <tglx@linutronix.de>
* Copyright(C) 2008 Red Hat, Inc., Ingo Molnar
*
* For licencing details see kernel-base/COPYING
*/
#include <linux/perf_counter.h>
#include <linux/capability.h>
#include <linux/notifier.h>
#include <linux/hardirq.h>
#include <linux/kprobes.h>
#include <linux/kdebug.h>
#include <linux/sched.h>
#include <asm/intel_arch_perfmon.h>
#include <asm/apic.h>
static bool perf_counters_initialized __read_mostly;
/*
* Number of (generic) HW counters:
*/
static int nr_hw_counters __read_mostly;
static u32 perf_counter_mask __read_mostly;
/* No support for fixed function counters yet */
#define MAX_HW_COUNTERS 8
struct cpu_hw_counters {
struct perf_counter *counters[MAX_HW_COUNTERS];
unsigned long used[BITS_TO_LONGS(MAX_HW_COUNTERS)];
int enable_all;
};
/*
* Intel PerfMon v3. Used on Core2 and later.
*/
static DEFINE_PER_CPU(struct cpu_hw_counters, cpu_hw_counters);
const int intel_perfmon_event_map[] =
{
[PERF_COUNT_CYCLES] = 0x003c,
[PERF_COUNT_INSTRUCTIONS] = 0x00c0,
[PERF_COUNT_CACHE_REFERENCES] = 0x4f2e,
[PERF_COUNT_CACHE_MISSES] = 0x412e,
[PERF_COUNT_BRANCH_INSTRUCTIONS] = 0x00c4,
[PERF_COUNT_BRANCH_MISSES] = 0x00c5,
};
const int max_intel_perfmon_events = ARRAY_SIZE(intel_perfmon_event_map);
/*
* Setup the hardware configuration for a given hw_event_type
*/
int hw_perf_counter_init(struct perf_counter *counter, s32 hw_event_type)
{
struct hw_perf_counter *hwc = &counter->hw;
if (unlikely(!perf_counters_initialized))
return -EINVAL;
/*
* Count user events, and generate PMC IRQs:
* (keep 'enabled' bit clear for now)
*/
hwc->config = ARCH_PERFMON_EVENTSEL_USR | ARCH_PERFMON_EVENTSEL_INT;
/*
* If privileged enough, count OS events too, and allow
* NMI events as well:
*/
hwc->nmi = 0;
if (capable(CAP_SYS_ADMIN)) {
hwc->config |= ARCH_PERFMON_EVENTSEL_OS;
if (hw_event_type & PERF_COUNT_NMI)
hwc->nmi = 1;
}
hwc->config_base = MSR_ARCH_PERFMON_EVENTSEL0;
hwc->counter_base = MSR_ARCH_PERFMON_PERFCTR0;
hwc->irq_period = counter->__irq_period;
/*
* Intel PMCs cannot be accessed sanely above 32 bit width,
* so we install an artificial 1<<31 period regardless of
* the generic counter period:
*/
if (!hwc->irq_period)
hwc->irq_period = 0x7FFFFFFF;
hwc->next_count = -((s32) hwc->irq_period);
/*
* Negative event types mean raw encoded event+umask values:
*/
if (hw_event_type < 0) {
counter->hw_event_type = -hw_event_type;
counter->hw_event_type &= ~PERF_COUNT_NMI;
} else {
hw_event_type &= ~PERF_COUNT_NMI;
if (hw_event_type >= max_intel_perfmon_events)
return -EINVAL;
/*
* The generic map:
*/
counter->hw_event_type = intel_perfmon_event_map[hw_event_type];
}
hwc->config |= counter->hw_event_type;
counter->wakeup_pending = 0;
return 0;
}
static void __hw_perf_enable_all(void)
{
wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, perf_counter_mask, 0);
}
void hw_perf_enable_all(void)
{
struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
cpuc->enable_all = 1;
__hw_perf_enable_all();
}
void hw_perf_disable_all(void)
{
struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
cpuc->enable_all = 0;
wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0, 0);
}
static DEFINE_PER_CPU(u64, prev_next_count[MAX_HW_COUNTERS]);
static void __hw_perf_counter_enable(struct hw_perf_counter *hwc, int idx)
{
per_cpu(prev_next_count[idx], smp_processor_id()) = hwc->next_count;
wrmsr(hwc->counter_base + idx, hwc->next_count, 0);
wrmsr(hwc->config_base + idx, hwc->config, 0);
}
void hw_perf_counter_enable(struct perf_counter *counter)
{
struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
struct hw_perf_counter *hwc = &counter->hw;
int idx = hwc->idx;
/* Try to get the previous counter again */
if (test_and_set_bit(idx, cpuc->used)) {
idx = find_first_zero_bit(cpuc->used, nr_hw_counters);
set_bit(idx, cpuc->used);
hwc->idx = idx;
}
perf_counters_lapic_init(hwc->nmi);
wrmsr(hwc->config_base + idx,
hwc->config & ~ARCH_PERFMON_EVENTSEL0_ENABLE, 0);
cpuc->counters[idx] = counter;
counter->hw.config |= ARCH_PERFMON_EVENTSEL0_ENABLE;
__hw_perf_counter_enable(hwc, idx);
}
#ifdef CONFIG_X86_64
static inline void atomic64_counter_set(struct perf_counter *counter, u64 val)
{
atomic64_set(&counter->count, val);
}
static inline u64 atomic64_counter_read(struct perf_counter *counter)
{
return atomic64_read(&counter->count);
}
#else
/*
* Todo: add proper atomic64_t support to 32-bit x86:
*/
static inline void atomic64_counter_set(struct perf_counter *counter, u64 val64)
{
u32 *val32 = (void *)&val64;
atomic_set(counter->count32 + 0, *(val32 + 0));
atomic_set(counter->count32 + 1, *(val32 + 1));
}
static inline u64 atomic64_counter_read(struct perf_counter *counter)
{
return atomic_read(counter->count32 + 0) |
(u64) atomic_read(counter->count32 + 1) << 32;
}
#endif
static void __hw_perf_save_counter(struct perf_counter *counter,
struct hw_perf_counter *hwc, int idx)
{
s64 raw = -1;
s64 delta;
int err;
/*
* Get the raw hw counter value:
*/
err = rdmsrl_safe(hwc->counter_base + idx, &raw);
WARN_ON_ONCE(err);
/*
* Rebase it to zero (it started counting at -irq_period),
* to see the delta since ->prev_count:
*/
delta = (s64)hwc->irq_period + (s64)(s32)raw;
atomic64_counter_set(counter, hwc->prev_count + delta);
/*
* Adjust the ->prev_count offset - if we went beyond
* irq_period of units, then we got an IRQ and the counter
* was set back to -irq_period:
*/
while (delta >= (s64)hwc->irq_period) {
hwc->prev_count += hwc->irq_period;
delta -= (s64)hwc->irq_period;
}
/*
* Calculate the next raw counter value we'll write into
* the counter at the next sched-in time:
*/
delta -= (s64)hwc->irq_period;
hwc->next_count = (s32)delta;
}
void perf_counter_print_debug(void)
{
u64 ctrl, status, overflow, pmc_ctrl, pmc_count, next_count;
int cpu, err, idx;
local_irq_disable();
cpu = smp_processor_id();
err = rdmsrl_safe(MSR_CORE_PERF_GLOBAL_CTRL, &ctrl);
WARN_ON_ONCE(err);
err = rdmsrl_safe(MSR_CORE_PERF_GLOBAL_STATUS, &status);
WARN_ON_ONCE(err);
err = rdmsrl_safe(MSR_CORE_PERF_GLOBAL_OVF_CTRL, &overflow);
WARN_ON_ONCE(err);
printk(KERN_INFO "\n");
printk(KERN_INFO "CPU#%d: ctrl: %016llx\n", cpu, ctrl);
printk(KERN_INFO "CPU#%d: status: %016llx\n", cpu, status);
printk(KERN_INFO "CPU#%d: overflow: %016llx\n", cpu, overflow);
for (idx = 0; idx < nr_hw_counters; idx++) {
err = rdmsrl_safe(MSR_ARCH_PERFMON_EVENTSEL0 + idx, &pmc_ctrl);
WARN_ON_ONCE(err);
err = rdmsrl_safe(MSR_ARCH_PERFMON_PERFCTR0 + idx, &pmc_count);
WARN_ON_ONCE(err);
next_count = per_cpu(prev_next_count[idx], cpu);
printk(KERN_INFO "CPU#%d: PMC%d ctrl: %016llx\n",
cpu, idx, pmc_ctrl);
printk(KERN_INFO "CPU#%d: PMC%d count: %016llx\n",
cpu, idx, pmc_count);
printk(KERN_INFO "CPU#%d: PMC%d next: %016llx\n",
cpu, idx, next_count);
}
local_irq_enable();
}
void hw_perf_counter_disable(struct perf_counter *counter)
{
struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
struct hw_perf_counter *hwc = &counter->hw;
unsigned int idx = hwc->idx;
counter->hw.config &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
wrmsr(hwc->config_base + idx, hwc->config, 0);
clear_bit(idx, cpuc->used);
cpuc->counters[idx] = NULL;
__hw_perf_save_counter(counter, hwc, idx);
}
void hw_perf_counter_read(struct perf_counter *counter)
{
struct hw_perf_counter *hwc = &counter->hw;
unsigned long addr = hwc->counter_base + hwc->idx;
s64 offs, val = -1LL;
s32 val32;
int err;
/* Careful: NMI might modify the counter offset */
do {
offs = hwc->prev_count;
err = rdmsrl_safe(addr, &val);
WARN_ON_ONCE(err);
} while (offs != hwc->prev_count);
val32 = (s32) val;
val = (s64)hwc->irq_period + (s64)val32;
atomic64_counter_set(counter, hwc->prev_count + val);
}
static void perf_store_irq_data(struct perf_counter *counter, u64 data)
{
struct perf_data *irqdata = counter->irqdata;
if (irqdata->len > PERF_DATA_BUFLEN - sizeof(u64)) {
irqdata->overrun++;
} else {
u64 *p = (u64 *) &irqdata->data[irqdata->len];
*p = data;
irqdata->len += sizeof(u64);
}
}
static void perf_save_and_restart(struct perf_counter *counter)
{
struct hw_perf_counter *hwc = &counter->hw;
int idx = hwc->idx;
wrmsr(hwc->config_base + idx,
hwc->config & ~ARCH_PERFMON_EVENTSEL0_ENABLE, 0);
if (hwc->config & ARCH_PERFMON_EVENTSEL0_ENABLE) {
__hw_perf_save_counter(counter, hwc, idx);
__hw_perf_counter_enable(hwc, idx);
}
}
static void
perf_handle_group(struct perf_counter *leader, u64 *status, u64 *overflown)
{
struct perf_counter_context *ctx = leader->ctx;
struct perf_counter *counter;
int bit;
list_for_each_entry(counter, &ctx->counters, list) {
if (counter->record_type != PERF_RECORD_SIMPLE ||
counter == leader)
continue;
if (counter->active) {
/*
* When counter was not in the overflow mask, we have to
* read it from hardware. We read it as well, when it
* has not been read yet and clear the bit in the
* status mask.
*/
bit = counter->hw.idx;
if (!test_bit(bit, (unsigned long *) overflown) ||
test_bit(bit, (unsigned long *) status)) {
clear_bit(bit, (unsigned long *) status);
perf_save_and_restart(counter);
}
}
perf_store_irq_data(leader, counter->hw_event_type);
perf_store_irq_data(leader, atomic64_counter_read(counter));
}
}
/*
* This handler is triggered by the local APIC, so the APIC IRQ handling
* rules apply:
*/
static void __smp_perf_counter_interrupt(struct pt_regs *regs, int nmi)
{
int bit, cpu = smp_processor_id();
struct cpu_hw_counters *cpuc;
u64 ack, status;
rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
if (!status) {