Commit 1b7b938f authored by Alexander Shishkin's avatar Alexander Shishkin Committed by Ingo Molnar

perf/x86/intel: Fix PMI handling for Intel PT

Intel PT is a separate PMU and it is not using any of the x86_pmu
code paths, which means in particular that the active_events counter
remains intact when new PT events are created.

However, PT uses the generic x86_pmu PMI handler for its PMI handling needs.

The problem here is that the latter checks active_events and in case of it
being zero, exits without calling the actual x86_pmu.handle_nmi(), which
results in unknown NMI errors and massive data loss for PT.

The effect is not visible if there are other perf events in the system
at the same time that keep active_events counter non-zero, for instance
if the NMI watchdog is running, so one needs to disable it to reproduce
the problem.

At the same time, the active_events counter besides doing what the name
suggests also implicitly serves as a PMC hardware and DS area reference

This patch adds a separate reference counter for the PMC hardware, leaving
active_events for actually counting the events and makes sure it also
counts PT and BTS events.
Signed-off-by: default avatarAlexander Shishkin <>
Signed-off-by: default avatarPeter Zijlstra (Intel) <>
Cc: Andrew Morton <>
Cc: Andy Lutomirski <>
Cc: Borislav Petkov <>
Cc: Brian Gerst <>
Cc: Denys Vlasenko <>
Cc: H. Peter Anvin <>
Cc: Linus Torvalds <>
Cc: Oleg Nesterov <>
Cc: Peter Zijlstra <>
Cc: Thomas Gleixner <>
Link: Ingo Molnar's avatarIngo Molnar <>
parent 6b099d9b
......@@ -135,6 +135,7 @@ static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
static atomic_t active_events;
static atomic_t pmc_refcount;
static DEFINE_MUTEX(pmc_reserve_mutex);
......@@ -271,6 +272,7 @@ static bool check_hw_exists(void)
static void hw_perf_event_destroy(struct perf_event *event)
void hw_perf_lbr_event_destroy(struct perf_event *event)
......@@ -324,16 +326,16 @@ int x86_reserve_hardware(void)
int err = 0;
if (!atomic_inc_not_zero(&active_events)) {
if (!atomic_inc_not_zero(&pmc_refcount)) {
if (atomic_read(&active_events) == 0) {
if (atomic_read(&pmc_refcount) == 0) {
if (!reserve_pmc_hardware())
err = -EBUSY;
if (!err)
......@@ -342,7 +344,7 @@ int x86_reserve_hardware(void)
void x86_release_hardware(void)
if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
if (atomic_dec_and_mutex_lock(&pmc_refcount, &pmc_reserve_mutex)) {
......@@ -371,12 +373,24 @@ int x86_add_exclusive(unsigned int what)
* Assuming that all exclusive events will share the PMI handler
* (which checks active_events for whether there is work to do),
* we can bump active_events counter right here, except for
* x86_lbr_exclusive_lbr events that go through x86_pmu_event_init()
* path, which already bumps active_events for them.
if (!ret && what != x86_lbr_exclusive_lbr)
return ret;
void x86_del_exclusive(unsigned int what)
int x86_setup_perfctr(struct perf_event *event)
......@@ -557,6 +571,7 @@ static int __x86_pmu_event_init(struct perf_event *event)
if (err)
return err;
event->destroy = hw_perf_event_destroy;
event->hw.idx = -1;
......@@ -1429,6 +1444,10 @@ perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs)
u64 finish_clock;
int ret;
* All PMUs/events that share this PMI handler should make sure to
* increment active_events for their events.
if (!atomic_read(&active_events))
return NMI_DONE;
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