Commit 193c9d23 authored by Paul Walmsley's avatar Paul Walmsley Committed by Rob Herring

Documentation: DT bindings: add more Tegra chip compatible strings

Align compatible strings for several IP blocks present on Tegra chips
with the latest doctrine from the DT maintainers:

http://marc.info/?l=devicetree&m=142255654213019&w=2

The primary objective here is to avoid checkpatch warnings, per:

http://marc.info/?l=linux-tegra&m=142201349727836&w=2

DT binding text files have been updated for the following IP blocks:

- PCIe
- SOR
- SoC timers
- AHB "gizmo"
- APB_MISC
- pinmux control
- UART
- PWM
- I2C
- SPI
- RTC
- PMC
- eFuse
- AHCI
- HDA
- XUSB_PADCTRL
- SDHCI
- SOC_THERM
- AHUB
- I2S
- EHCI
- USB PHY

N.B. The nvidia,tegra20-timer compatible string is removed from the
nvidia,tegra30-timer.txt documentation file because it's already
mentioned in the nvidia,tegra20-timer.txt documentation file.

This second version takes into account the following requests from
Rob Herring <robherring2@gmail.com>:

- Per-IP block patches have been combined into a single patch

- Explicit documentation about which compatible strings are actually
  matched by the driver has been removed.  In its place is implicit
  documentation that loosely follows Rob's prescribed format:

  "Must contain '"nvidia,<chip>-pcie", "nvidia,tegra20-pcie"' where
   <chip> is tegra30, tegra132, ..." [...]  "You should attempt to
   document known values of <chip> if you use it"
Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: Dylan Reid <dgreid@chromium.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Jingchang Lu <jingchang.lu@freescale.com>
Cc: John Crispin <blogic@openwrt.org>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mikko Perttunen <mperttunen@nvidia.com>
Cc: Murali Karicheri <m-karicheri2@ti.com>
Cc: Paul Walmsley <pwalmsley@nvidia.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Peter Hurley <peter@hurleysoftware.com>
Cc: Sean Paul <seanpaul@chromium.org>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Takashi Iwai <tiwai@suse.de>
Cc: Tejun Heo <tj@kernel.org>
Cc: "Terje Bergström" <tbergstrom@nvidia.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Cc: Wolfram Sang <wsa@the-dreams.de>
Cc: Zhang Rui <rui.zhang@intel.com>
Cc: dri-devel@lists.freedesktop.org
Cc: linux-i2c@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Cc: linux-pm@vger.kernel.org
Cc: linux-pwm@vger.kernel.org
Cc: linux-tegra@vger.kernel.org
Acked-by: default avatarEduardo Valentin <edubezval@gmail.com>
Signed-off-by: Rob Herring's avatarRob Herring <robh@kernel.org>
parent 2d4c0aef
NVIDIA Tegra AHB
Required properties:
- compatible : "nvidia,tegra20-ahb" or "nvidia,tegra30-ahb"
- compatible : For Tegra20, must contain "nvidia,tegra20-ahb". For
Tegra30, must contain "nvidia,tegra30-ahb". Otherwise, must contain
'"nvidia,<chip>-ahb", "nvidia,tegra30-ahb"' where <chip> is tegra124,
tegra132, or tegra210.
- reg : Should contain 1 register ranges(address and length)
Example:
......
......@@ -6,7 +6,11 @@ modes. It provides power-gating controllers for SoC and CPU power-islands.
Required properties:
- name : Should be pmc
- compatible : Should contain "nvidia,tegra<chip>-pmc".
- compatible : For Tegra20, must contain "nvidia,tegra20-pmc". For Tegra30,
must contain "nvidia,tegra30-pmc". For Tegra114, must contain
"nvidia,tegra114-pmc". For Tegra124, must contain "nvidia,tegra124-pmc".
Otherwise, must contain "nvidia,<chip>-pmc", plus at least one of the
above, where <chip> is tegra132.
- reg : Offset and length of the register set for the device
- clocks : Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
......
Tegra124 SoC SATA AHCI controller
Required properties :
- compatible : "nvidia,tegra124-ahci".
- compatible : For Tegra124, must contain "nvidia,tegra124-ahci". Otherwise,
must contain '"nvidia,<chip>-ahci", "nvidia,tegra124-ahci"', where <chip>
is tegra132.
- reg : Should contain 2 entries:
- AHCI register set (SATA BAR5)
- SATA register set
......
NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 fuse block.
Required properties:
- compatible : should be:
"nvidia,tegra20-efuse"
"nvidia,tegra30-efuse"
"nvidia,tegra114-efuse"
"nvidia,tegra124-efuse"
- compatible : For Tegra20, must contain "nvidia,tegra20-efuse". For Tegra30,
must contain "nvidia,tegra30-efuse". For Tegra114, must contain
"nvidia,tegra114-efuse". For Tegra124, must contain "nvidia,tegra124-efuse".
Otherwise, must contain "nvidia,<chip>-efuse", plus one of the above, where
<chip> is tegra132.
Details:
nvidia,tegra20-efuse: Tegra20 requires using APB DMA to read the fuse data
due to a hardware bug. Tegra20 also lacks certain information which is
......
......@@ -197,7 +197,9 @@ of the following host1x client modules:
- sor: serial output resource
Required properties:
- compatible: "nvidia,tegra124-sor"
- compatible: For Tegra124, must contain "nvidia,tegra124-sor". Otherwise,
must contain '"nvidia,<chip>-sor", "nvidia,tegra124-sor"', where <chip>
is tegra132.
- reg: Physical base address and length of the controller's registers.
- interrupts: The interrupt outputs from the controller.
- clocks: Must contain an entry for each entry in clock-names.
......@@ -222,7 +224,9 @@ of the following host1x client modules:
- nvidia,dpaux: phandle to a DispayPort AUX interface
- dpaux: DisplayPort AUX interface
- compatible: "nvidia,tegra124-dpaux"
- compatible: For Tegra124, must contain "nvidia,tegra124-dpaux". Otherwise,
must contain '"nvidia,<chip>-dpaux", "nvidia,tegra124-dpaux"', where
<chip> is tegra132.
- reg: Physical base address and length of the controller's registers.
- interrupts: The interrupt outputs from the controller.
- clocks: Must contain an entry for each entry in clock-names.
......
NVIDIA Tegra20/Tegra30/Tegra114 I2C controller driver.
Required properties:
- compatible : should be:
"nvidia,tegra114-i2c"
"nvidia,tegra30-i2c"
"nvidia,tegra20-i2c"
"nvidia,tegra20-i2c-dvc"
- compatible : For Tegra20, must be one of "nvidia,tegra20-i2c-dvc" or
"nvidia,tegra20-i2c". For Tegra30, must be "nvidia,tegra30-i2c".
For Tegra114, must be "nvidia,tegra114-i2c". Otherwise, must be
"nvidia,<chip>-i2c", plus at least one of the above, where <chip> is
tegra124, tegra132, or tegra210.
Details of compatible are as follows:
nvidia,tegra20-i2c-dvc: Tegra20 has specific I2C controller called as DVC I2C
controller. This only support master mode of I2C communication. Register
......
NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 apbmisc block
Required properties:
- compatible : should be:
"nvidia,tegra20-apbmisc"
"nvidia,tegra30-apbmisc"
"nvidia,tegra114-apbmisc"
"nvidia,tegra124-apbmisc"
- compatible : For Tegra20, must be "nvidia,tegra20-apbmisc". For Tegra30,
must be "nvidia,tegra30-apbmisc". Otherwise, must contain
"nvidia,<chip>-apbmisc", plus one of the above, where <chip> is tegra114,
tegra124, tegra132.
- reg: Should contain 2 entries: the first entry gives the physical address
and length of the registers which contain revision and debug features.
The second entry gives the physical address and length of the
......
......@@ -7,7 +7,11 @@ This file documents differences between the core properties described
by mmc.txt and the properties used by the sdhci-tegra driver.
Required properties:
- compatible : Should be "nvidia,<chip>-sdhci"
- compatible : For Tegra20, must contain "nvidia,tegra20-sdhci".
For Tegra30, must contain "nvidia,tegra30-sdhci". For Tegra114,
must contain "nvidia,tegra114-sdhci". For Tegra124, must contain
"nvidia,tegra124-sdhci". Otherwise, must contain "nvidia,<chip>-sdhci",
plus one of the above, where <chip> is tegra132 or tegra210.
- clocks : Must contain one entry, for the module clock.
See ../clocks/clock-bindings.txt for details.
- resets : Must contain an entry for each entry in reset-names.
......
NVIDIA Tegra PCIe controller
Required properties:
- compatible: Must be one of:
- "nvidia,tegra20-pcie"
- "nvidia,tegra30-pcie"
- "nvidia,tegra124-pcie"
- compatible: For Tegra20, must contain "nvidia,tegra20-pcie". For Tegra30,
"nvidia,tegra30-pcie". For Tegra124, must contain "nvidia,tegra124-pcie".
Otherwise, must contain "nvidia,<chip>-pcie", plus one of the above, where
<chip> is tegra132 or tegra210.
- device_type: Must be "pci"
- reg: A list of physical base address and length for each set of controller
registers. Must contain an entry for each entry in the reg-names property.
......
......@@ -6,7 +6,8 @@ nvidia,tegra30-pinmux.txt. In fact, this document assumes that binding as
a baseline, and only documents the differences between the two bindings.
Required properties:
- compatible: "nvidia,tegra124-pinmux"
- compatible: For Tegra124, must contain "nvidia,tegra124-pinmux". For
Tegra132, must contain '"nvidia,tegra132-pinmux", "nvidia-tegra124-pinmux"'.
- reg: Should contain a list of base address and size pairs for:
-- first entry - the drive strength and pad control registers.
-- second entry - the pinmux registers
......
......@@ -13,7 +13,9 @@ how to describe and reference PHYs in device trees.
Required properties:
--------------------
- compatible: should be "nvidia,tegra124-xusb-padctl"
- compatible: For Tegra124, must contain "nvidia,tegra124-xusb-padctl".
Otherwise, must contain '"nvidia,<chip>-xusb-padctl",
"nvidia-tegra124-xusb-padctl"', where <chip> is tegra132 or tegra210.
- reg: Physical base address and length of the controller's registers.
- resets: Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
......
Tegra SoC PWFM controller
Required properties:
- compatible: should be one of:
- "nvidia,tegra20-pwm"
- "nvidia,tegra30-pwm"
- compatible: For Tegra20, must contain "nvidia,tegra20-pwm". For Tegra30,
must contain "nvidia,tegra30-pwm". Otherwise, must contain
"nvidia,<chip>-pwm", plus one of the above, where <chip> is tegra114,
tegra124, tegra132, or tegra210.
- reg: physical base address and length of the controller's registers
- #pwm-cells: should be 2. See pwm.txt in this directory for a description of
the cells format.
......
......@@ -6,7 +6,9 @@ state.
Required properties:
- compatible : should be "nvidia,tegra20-rtc".
- compatible : For Tegra20, must contain "nvidia,tegra20-rtc". Otherwise,
must contain '"nvidia,<chip>-rtc", "nvidia,tegra20-rtc"', where <chip>
can be tegra30, tegra114, tegra124, or tegra132.
- reg : Specifies base physical address and size of the registers.
- interrupts : A single interrupt specifier.
- clocks : Must contain one entry, for the module clock.
......
......@@ -8,7 +8,10 @@ Required properties:
- "ns16550"
- "ns16750"
- "ns16850"
- "nvidia,tegra20-uart"
- For Tegra20, must contain "nvidia,tegra20-uart"
- For other Tegra, must contain '"nvidia,<chip>-uart",
"nvidia,tegra20-uart"' where <chip> is tegra30, tegra114, tegra124,
tegra132, or tegra210.
- "nxp,lpc3220-uart"
- "ralink,rt2880-uart"
- "ibm,qpace-nwp-serial"
......
NVIDIA Tegra30 AHUB (Audio Hub)
Required properties:
- compatible : "nvidia,tegra30-ahub", "nvidia,tegra114-ahub", etc.
- compatible : For Tegra30, must contain "nvidia,tegra30-ahub". For Tegra114,
must contain "nvidia,tegra114-ahub". For Tegra124, must contain
"nvidia,tegra124-ahub". Otherwise, must contain "nvidia,<chip>-ahub",
plus at least one of the above, where <chip> is tegra132.
- reg : Should contain the register physical address and length for each of
the AHUB's register blocks.
- Tegra30 requires 2 entries, for the APBIF and AHUB/AUDIO register blocks.
......
NVIDIA Tegra30 HDA controller
Required properties:
- compatible : "nvidia,tegra30-hda"
- compatible : For Tegra30, must contain "nvidia,tegra30-hda". Otherwise,
must contain '"nvidia,<chip>-hda", "nvidia,tegra30-hda"', where <chip> is
tegra114, tegra124, or tegra132.
- reg : Should contain the HDA registers location and length.
- interrupts : The interrupt from the HDA controller.
- clocks : Must contain an entry for each required entry in clock-names.
......
NVIDIA Tegra30 I2S controller
Required properties:
- compatible : "nvidia,tegra30-i2s"
- compatible : For Tegra30, must contain "nvidia,tegra30-i2s". For Tegra124,
must contain "nvidia,tegra124-i2s". Otherwise, must contain
"nvidia,<chip>-i2s" plus at least one of the above, where <chip> is
tegra114 or tegra132.
- reg : Should contain I2S registers location and length
- clocks : Must contain one entry, for the module clock.
See ../clocks/clock-bindings.txt for details.
......
NVIDIA Tegra114 SPI controller.
Required properties:
- compatible : should be "nvidia,tegra114-spi".
- compatible : For Tegra114, must contain "nvidia,tegra114-spi".
Otherwise, must contain '"nvidia,<chip>-spi", "nvidia,tegra114-spi"' where
<chip> is tegra124, tegra132, or tegra210.
- reg: Should contain SPI registers location and length.
- interrupts: Should contain SPI interrupts.
- clock-names : Must include the following entries:
......
......@@ -7,7 +7,9 @@ notifications. It is also used to manage emergency shutdown in an
overheating situation.
Required properties :
- compatible : "nvidia,tegra124-soctherm".
- compatible : For Tegra124, must contain "nvidia,tegra124-soctherm".
For Tegra132, must contain "nvidia,tegra132-soctherm".
For Tegra210, must contain "nvidia,tegra210-soctherm".
- reg : Should contain 1 entry:
- SOCTHERM register set
- interrupts : Defines the interrupt used by SOCTHERM
......
......@@ -6,7 +6,9 @@ trigger a legacy watchdog reset.
Required properties:
- compatible : should be "nvidia,tegra30-timer", "nvidia,tegra20-timer".
- compatible : For Tegra30, must contain "nvidia,tegra30-timer". Otherwise,
must contain '"nvidia,<chip>-timer", "nvidia,tegra30-timer"' where
<chip> is tegra124 or tegra132.
- reg : Specifies base physical address and size of the registers.
- interrupts : A list of 6 interrupts; one per each of timer channels 1
through 5, and one for the shared interrupt for the remaining channels.
......
......@@ -6,7 +6,10 @@ Practice : Universal Serial Bus" with the following modifications
and additions :
Required properties :
- compatible : Should be "nvidia,tegra20-ehci".
- compatible : For Tegra20, must contain "nvidia,tegra20-ehci".
For Tegra30, must contain "nvidia,tegra30-ehci". Otherwise, must contain
"nvidia,<chip>-ehci" plus at least one of the above, where <chip> is
tegra114, tegra124, tegra132, or tegra210.
- nvidia,phy : phandle of the PHY that the controller is connected to.
- clocks : Must contain one entry, for the module clock.
See ../clocks/clock-bindings.txt for details.
......
......@@ -3,7 +3,10 @@ Tegra SOC USB PHY
The device node for Tegra SOC USB PHY:
Required properties :
- compatible : Should be "nvidia,tegra<chip>-usb-phy".
- compatible : For Tegra20, must contain "nvidia,tegra20-usb-phy".
For Tegra30, must contain "nvidia,tegra30-usb-phy". Otherwise, must contain
"nvidia,<chip>-usb-phy" plus at least one of the above, where <chip> is
tegra114, tegra124, tegra132, or tegra210.
- reg : Defines the following set of registers, in the order listed:
- The PHY's own register set.
Always present.
......
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