Commit 173d6681 authored by Chris Zankel's avatar Chris Zankel Committed by Linus Torvalds

[PATCH] xtensa: remove extra header files

The Xtensa port contained many header files that were never needed.  This
rather lengthy patch removes all those files.  Unfortunately, there were
many dependencies that needed to be updated, so this patch touches quite a
few source files.
Signed-off-by: default avatarChris Zankel <chris@zankel.net>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent fd43fe19
......@@ -48,25 +48,10 @@ menu "Processor type and features"
choice
prompt "Xtensa Processor Configuration"
default XTENSA_CPU_LINUX_BE
default XTENSA_VARIANT_FSF
config XTENSA_CPU_LINUX_BE
bool "linux_be"
---help---
The linux_be processor configuration is the baseline Xtensa
configurations included in this kernel and also used by
binutils, gcc, and gdb. It contains no TIE, no coprocessors,
and the following configuration options:
Code Density Option 2 Misc Special Registers
NSA/NSAU Instructions 128-bit Data Bus Width
Processor ID 8K, 2-way I and D Caches
Zero-Overhead Loops 2 Inst Address Break Registers
Big Endian 2 Data Address Break Registers
64 General-Purpose Registers JTAG Interface and Trace Port
17 Interrupts MMU w/ TLBs and Autorefill
3 Interrupt Levels 8 Autorefill Ways (I/D TLBs)
3 Timers Unaligned Exceptions
config XTENSA_VARIANT_FSF
bool "fsf"
endchoice
config MMU
......
......@@ -11,13 +11,13 @@
# this architecture
# Core configuration.
# (Use CPU=<xtensa_config> to use another default compiler.)
# (Use VAR=<xtensa_config> to use another default compiler.)
cpu-$(CONFIG_XTENSA_CPU_LINUX_BE) := linux_be
cpu-$(CONFIG_XTENSA_CPU_LINUX_CUSTOM) := linux_custom
variant-$(CONFIG_XTENSA_VARIANT_FSF) := fsf
variant-$(CONFIG_XTENSA_VARIANT_LINUX_CUSTOM) := custom
CPU = $(cpu-y)
export CPU
VARIANT = $(variant-y)
export VARIANT
# Platform configuration
......@@ -27,8 +27,6 @@ platform-$(CONFIG_XTENSA_PLATFORM_ISS) := iss
PLATFORM = $(platform-y)
export PLATFORM
CPPFLAGS += $(if $(KBUILD_SRC),-I$(srctree)/include/asm-xtensa/)
CPPFLAGS += -Iinclude/asm
CFLAGS += -pipe -mlongcalls
KBUILD_DEFCONFIG := iss_defconfig
......@@ -41,12 +39,12 @@ core-$(CONFIG_EMBEDDED_RAMDISK) += arch/xtensa/boot/ramdisk/
# Test for cross compiling
ifneq ($(CPU),)
ifneq ($(VARIANT),)
COMPILE_ARCH = $(shell uname -m)
ifneq ($(COMPILE_ARCH), xtensa)
ifndef CROSS_COMPILE
CROSS_COMPILE = xtensa_$(CPU)-
CROSS_COMPILE = xtensa_$(VARIANT)-
endif
endif
endif
......@@ -68,14 +66,13 @@ archinc := include/asm-xtensa
archprepare: $(archinc)/.platform
# Update machine cpu and platform symlinks if something which affects
# Update processor variant and platform symlinks if something which affects
# them changed.
$(archinc)/.platform: $(wildcard include/config/arch/*.h) include/config/auto.conf
@echo ' SYMLINK $(archinc)/xtensa/config -> $(archinc)/xtensa/config-$(CPU)'
@echo ' SYMLINK $(archinc)/variant -> $(archinc)/variant-$(VARIANT)'
$(Q)mkdir -p $(archinc)
$(Q)mkdir -p $(archinc)/xtensa
$(Q)ln -fsn $(srctree)/$(archinc)/xtensa/config-$(CPU) $(archinc)/xtensa/config
$(Q)ln -fsn $(srctree)/$(archinc)/variant-$(VARIANT) $(archinc)/variant
@echo ' SYMLINK $(archinc)/platform -> $(archinc)/platform-$(PLATFORM)'
$(Q)ln -fsn $(srctree)/$(archinc)/platform-$(PLATFORM) $(archinc)/platform
@touch $@
......@@ -89,7 +86,7 @@ zImage zImage.initrd: vmlinux
$(Q)$(MAKE) $(build)=$(boot) $@
CLEAN_FILES += arch/xtensa/vmlinux.lds \
$(archinc)/platform $(archinc)/xtensa/config \
$(archinc)/platform $(archinc)/variant \
$(archinc)/.platform
define archhelp
......
#include <xtensa/config/specreg.h>
#include <xtensa/config/core.h>
#include <asm/bootparam.h>
......
#define _ASMLANGUAGE
#include <xtensa/config/specreg.h>
#include <xtensa/config/core.h>
#include <xtensa/cacheasm.h>
#include <asm/variant/core.h>
#include <asm/regs.h>
#include <asm/asmmacro.h>
#include <asm/cacheasm.h>
/*
* RB-Data: RedBoot data/bss
* P: Boot-Parameters
......@@ -77,8 +75,14 @@ _start:
/* Note: The assembler cannot relax "addi a0, a0, ..." to an
l32r, so we load to a4 first. */
addi a4, a0, __start - __start_a0
mov a0, a4
# addi a4, a0, __start - __start_a0
# mov a0, a4
movi a4, __start
movi a5, __start_a0
add a4, a0, a4
sub a0, a4, a5
movi a4, __start
movi a5, __reloc_end
......@@ -106,9 +110,13 @@ _start:
/* We have to flush and invalidate the caches here before we jump. */
#if XCHAL_DCACHE_IS_WRITEBACK
dcache_writeback_all a5, a6
___flush_dcache_all a5 a6
#endif
icache_invalidate_all a5, a6
___invalidate_icache_all a5 a6
isync
movi a11, _reloc
jx a11
......@@ -209,9 +217,14 @@ _reloc:
/* jump to the kernel */
2:
#if XCHAL_DCACHE_IS_WRITEBACK
dcache_writeback_all a5, a6
___flush_dcache_all a5 a6
#endif
icache_invalidate_all a5, a6
___invalidate_icache_all a5 a6
isync
movi a5, __start
movi a3, boot_initrd_start
......
......@@ -53,11 +53,7 @@ CONFIG_CC_ALIGN_JUMPS=0
#
# Processor type and features
#
CONFIG_XTENSA_ARCH_LINUX_BE=y
# CONFIG_XTENSA_ARCH_LINUX_LE is not set
# CONFIG_XTENSA_ARCH_LINUX_TEST is not set
# CONFIG_XTENSA_ARCH_S5 is not set
# CONFIG_XTENSA_CUSTOM is not set
CONFIG_XTENSA_VARIANT_FSF=y
CONFIG_MMU=y
# CONFIG_XTENSA_UNALIGNED_USER is not set
# CONFIG_PREEMPT is not set
......
......@@ -16,14 +16,9 @@
*/
#include <linux/linkage.h>
#include <asm/ptrace.h>
#include <asm/ptrace.h>
#include <asm/current.h>
#include <asm/asm-offsets.h>
#include <asm/pgtable.h>
#include <asm/processor.h>
#include <asm/page.h>
#include <asm/thread_info.h>
#if XCHAL_UNALIGNED_LOAD_EXCEPTION || XCHAL_UNALIGNED_STORE_EXCEPTION
......@@ -216,7 +211,7 @@ ENTRY(fast_unaligned)
extui a5, a4, INSN_OP0, 4 # get insn.op0 nibble
#if XCHAL_HAVE_NARROW
#if XCHAL_HAVE_DENSITY
_beqi a5, OP0_L32I_N, .Lload # L32I.N, jump
addi a6, a5, -OP0_S32I_N
_beqz a6, .Lstore # S32I.N, do a store
......@@ -251,7 +246,7 @@ ENTRY(fast_unaligned)
#endif
__src_b a3, a5, a6 # a3 has the data word
#if XCHAL_HAVE_NARROW
#if XCHAL_HAVE_DENSITY
addi a7, a7, 2 # increment PC (assume 16-bit insn)
extui a5, a4, INSN_OP0, 4
......@@ -279,14 +274,14 @@ ENTRY(fast_unaligned)
1:
#if XCHAL_HAVE_LOOP
rsr a3, LEND # check if we reached LEND
bne a7, a3, 1f
rsr a3, LCOUNT # and LCOUNT != 0
beqz a3, 1f
addi a3, a3, -1 # decrement LCOUNT and set
#if XCHAL_HAVE_LOOPS
rsr a5, LEND # check if we reached LEND
bne a7, a5, 1f
rsr a5, LCOUNT # and LCOUNT != 0
beqz a5, 1f
addi a5, a5, -1 # decrement LCOUNT and set
rsr a7, LBEG # set PC to LBEGIN
wsr a3, LCOUNT
wsr a5, LCOUNT
#endif
1: wsr a7, EPC_1 # skip load instruction
......@@ -336,7 +331,7 @@ ENTRY(fast_unaligned)
movi a6, 0 # mask: ffffffff:00000000
#if XCHAL_HAVE_NARROW
#if XCHAL_HAVE_DENSITY
addi a7, a7, 2 # incr. PC,assume 16-bit instruction
extui a5, a4, INSN_OP0, 4 # extract OP0
......@@ -359,14 +354,14 @@ ENTRY(fast_unaligned)
/* Get memory address */
1:
#if XCHAL_HAVE_LOOP
rsr a3, LEND # check if we reached LEND
bne a7, a3, 1f
rsr a3, LCOUNT # and LCOUNT != 0
beqz a3, 1f
addi a3, a3, -1 # decrement LCOUNT and set
#if XCHAL_HAVE_LOOPS
rsr a4, LEND # check if we reached LEND
bne a7, a4, 1f
rsr a4, LCOUNT # and LCOUNT != 0
beqz a4, 1f
addi a4, a4, -1 # decrement LCOUNT and set
rsr a7, LBEG # set PC to LBEGIN
wsr a3, LCOUNT
wsr a4, LCOUNT
#endif
1: wsr a7, EPC_1 # skip store instruction
......@@ -416,6 +411,7 @@ ENTRY(fast_unaligned)
/* Restore working register */
l32i a8, a2, PT_AREG8
l32i a7, a2, PT_AREG7
l32i a6, a2, PT_AREG6
l32i a5, a2, PT_AREG5
......@@ -446,7 +442,7 @@ ENTRY(fast_unaligned)
mov a1, a2
rsr a0, PS
bbsi.l a2, PS_UM_SHIFT, 1f # jump if user mode
bbsi.l a2, PS_UM_BIT, 1f # jump if user mode
movi a0, _kernel_exception
jx a0
......
......@@ -90,7 +90,6 @@ ENTRY(enable_coprocessor)
rsync
retw
#endif
ENTRY(save_coprocessor_extra)
entry sp, 16
......@@ -197,4 +196,5 @@ _xtensa_reginfo_tables:
XCHAL_CP7_SA_CONTENTS_LIBDB
.word 0xFC000000 /* invalid register number,marks end of table*/
_xtensa_reginfo_table_end:
#endif
......@@ -24,7 +24,7 @@
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/signal.h>
#include <xtensa/coreasm.h>
#include <asm/tlbflush.h>
/* Unimplemented features. */
......@@ -364,7 +364,7 @@ common_exception:
movi a2, 1
extui a3, a3, 0, 1 # a3 = PS.INTLEVEL[0]
moveqz a3, a2, a0 # a3 = 1 iff interrupt exception
movi a2, PS_WOE_MASK
movi a2, 1 << PS_WOE_BIT
or a3, a3, a2
rsr a0, EXCCAUSE
xsr a3, PS
......@@ -399,7 +399,7 @@ common_exception_return:
/* Jump if we are returning from kernel exceptions. */
1: l32i a3, a1, PT_PS
_bbsi.l a3, PS_UM_SHIFT, 2f
_bbsi.l a3, PS_UM_BIT, 2f
j kernel_exception_exit
/* Specific to a user exception exit:
......@@ -422,7 +422,7 @@ common_exception_return:
* (Hint: There is only one user exception frame on stack)
*/
movi a3, PS_WOE_MASK
movi a3, 1 << PS_WOE_BIT
_bbsi.l a4, TIF_NEED_RESCHED, 3f
_bbci.l a4, TIF_SIGPENDING, 4f
......@@ -694,7 +694,7 @@ common_exception_exit:
ENTRY(debug_exception)
rsr a0, EPS + XCHAL_DEBUGLEVEL
bbsi.l a0, PS_EXCM_SHIFT, 1f # exception mode
bbsi.l a0, PS_EXCM_BIT, 1f # exception mode
/* Set EPC_1 and EXCCAUSE */
......@@ -707,7 +707,7 @@ ENTRY(debug_exception)
/* Restore PS to the value before the debug exc but with PS.EXCM set.*/
movi a2, 1 << PS_EXCM_SHIFT
movi a2, 1 << PS_EXCM_BIT
or a2, a0, a2
movi a0, debug_exception # restore a3, debug jump vector
wsr a2, PS
......@@ -715,7 +715,7 @@ ENTRY(debug_exception)
/* Switch to kernel/user stack, restore jump vector, and save a0 */
bbsi.l a2, PS_UM_SHIFT, 2f # jump if user mode
bbsi.l a2, PS_UM_BIT, 2f # jump if user mode
addi a2, a1, -16-PT_SIZE # assume kernel stack
s32i a0, a2, PT_AREG0
......@@ -778,7 +778,7 @@ ENTRY(unrecoverable_exception)
wsr a1, WINDOWBASE
rsync
movi a1, PS_WOE_MASK | 1
movi a1, (1 << PS_WOE_BIT) | 1
wsr a1, PS
rsync
......@@ -1491,7 +1491,7 @@ ENTRY(_spill_registers)
*/
rsr a0, PS
_bbci.l a0, PS_UM_SHIFT, 1f
_bbci.l a0, PS_UM_BIT, 1f
/* User space: Setup a dummy frame and kill application.
* Note: We assume EXC_TABLE_KSTK contains a valid stack pointer.
......@@ -1510,7 +1510,7 @@ ENTRY(_spill_registers)
l32i a1, a3, EXC_TABLE_KSTK
wsr a3, EXCSAVE_1
movi a4, PS_WOE_MASK | 1
movi a4, (1 << PS_WOE_BIT) | 1
wsr a4, PS
rsync
......@@ -1612,7 +1612,7 @@ ENTRY(fast_second_level_miss)
rsr a1, PTEVADDR
srli a1, a1, PAGE_SHIFT
slli a1, a1, PAGE_SHIFT # ptevaddr & PAGE_MASK
addi a1, a1, DTLB_WAY_PGTABLE # ... + way_number
addi a1, a1, DTLB_WAY_PGD # ... + way_number
wdtlb a0, a1
dsync
......@@ -1654,7 +1654,7 @@ ENTRY(fast_second_level_miss)
mov a1, a2
rsr a2, PS
bbsi.l a2, PS_UM_SHIFT, 1f
bbsi.l a2, PS_UM_BIT, 1f
j _kernel_exception
1: j _user_exception
......@@ -1753,7 +1753,7 @@ ENTRY(fast_store_prohibited)
mov a1, a2
rsr a2, PS
bbsi.l a2, PS_UM_SHIFT, 1f
bbsi.l a2, PS_UM_BIT, 1f
j _kernel_exception
1: j _user_exception
......@@ -1924,7 +1924,7 @@ ENTRY(_switch_to)
/* Disable ints while we manipulate the stack pointer; spill regs. */
movi a5, PS_EXCM_MASK | LOCKLEVEL
movi a5, (1 << PS_EXCM_BIT) | LOCKLEVEL
xsr a5, PS
rsr a3, EXCSAVE_1
rsync
......
......@@ -15,9 +15,9 @@
* Kevin Chea
*/
#include <xtensa/cacheasm.h>
#include <asm/processor.h>
#include <asm/page.h>
#include <asm/cacheasm.h>
/*
* This module contains the entry code for kernel images. It performs the
......@@ -32,13 +32,6 @@
*
*/
.macro iterate from, to , cmd
.ifeq ((\to - \from) & ~0xfff)
\cmd \from
iterate "(\from+1)", \to, \cmd
.endif
.endm
/*
* _start
*
......@@ -64,7 +57,7 @@ _startup:
/* Disable interrupts and exceptions. */
movi a0, XCHAL_PS_EXCM_MASK
movi a0, LOCKLEVEL
wsr a0, PS
/* Preserve the pointer to the boot parameter list in EXCSAVE_1 */
......@@ -91,11 +84,11 @@ _startup:
movi a1, 15
wsr a0, ICOUNTLEVEL
.macro reset_dbreak num
wsr a0, DBREAKC + \num
.endm
iterate 0, XCHAL_NUM_IBREAK-1, reset_dbreak
.set _index, 0
.rept XCHAL_NUM_DBREAK - 1
wsr a0, DBREAKC + _index
.set _index, _index + 1
.endr
#endif
/* Clear CCOUNT (not really necessary, but nice) */
......@@ -110,10 +103,11 @@ _startup:
/* Disable all timers. */
.macro reset_timer num
wsr a0, CCOMPARE_0 + \num
.endm
iterate 0, XCHAL_NUM_TIMERS-1, reset_timer
.set _index, 0
.rept XCHAL_NUM_TIMERS - 1
wsr a0, CCOMPARE + _index
.set _index, _index + 1
.endr
/* Interrupt initialization. */
......@@ -139,12 +133,21 @@ _startup:
rsync
/* Initialize the caches.
* Does not include flushing writeback d-cache.
* a6, a7 are just working registers (clobbered).
* a2, a3 are just working registers (clobbered).
*/
icache_reset a2, a3
dcache_reset a2, a3
#if XCHAL_DCACHE_LINE_LOCKABLE
___unlock_dcache_all a2 a3
#endif
#if XCHAL_ICACHE_LINE_LOCKABLE
___unlock_icache_all a2 a3
#endif
___invalidate_dcache_all a2 a3
___invalidate_icache_all a2 a3
isync
/* Unpack data sections
*
......@@ -181,9 +184,9 @@ _startup:
movi a2, _bss_start # start of BSS
movi a3, _bss_end # end of BSS
1: addi a2, a2, 4
__loopt a2, a3, a4, 2
s32i a0, a2, 0
blt a2, a3, 1b
__endla a2, a4, 4
#if XCHAL_DCACHE_IS_WRITEBACK
......@@ -191,7 +194,7 @@ _startup:
* instructions/data are available.
*/
dcache_writeback_all a2, a3
___flush_dcache_all a2 a3
#endif
/* Setup stack and enable window exceptions (keep irqs disabled) */
......
/*
* arch/xtensa/kernel/pci-dma.c
* arch/xtensa/pci-dma.c
*
* DMA coherent memory allocation.
*
......@@ -29,28 +29,48 @@
*/
void *
dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp)
dma_alloc_coherent(struct device *dev,size_t size,dma_addr_t *handle,gfp_t flag)
{
void *ret;
unsigned long ret;
unsigned long uncached = 0;
/* ignore region speicifiers */
gfp &= ~(__GFP_DMA | __GFP_HIGHMEM);
if (dev == NULL || (*dev->dma_mask < 0xffffffff))
gfp |= GFP_DMA;
ret = (void *)__get_free_pages(gfp, get_order(size));
flag &= ~(__GFP_DMA | __GFP_HIGHMEM);
if (ret != NULL) {
memset(ret, 0, size);
*handle = virt_to_bus(ret);
if (dev == NULL || (dev->coherent_dma_mask < 0xffffffff))
flag |= GFP_DMA;
ret = (unsigned long)__get_free_pages(flag, get_order(size));
if (ret == 0)
return NULL;
/* We currently don't support coherent memory outside KSEG */
if (ret < XCHAL_KSEG_CACHED_VADDR
|| ret >= XCHAL_KSEG_CACHED_VADDR + XCHAL_KSEG_SIZE)
BUG();
if (ret != 0) {
memset((void*) ret, 0, size);
uncached = ret+XCHAL_KSEG_BYPASS_VADDR-XCHAL_KSEG_CACHED_VADDR;
*handle = virt_to_bus((void*)ret);
__flush_invalidate_dcache_range(ret, size);
}
return (void*) BYPASS_ADDR((unsigned long)ret);
return (void*)uncached;
}
void dma_free_coherent(struct device *hwdev, size_t size,
void *vaddr, dma_addr_t dma_handle)
{
free_pages(CACHED_ADDR((unsigned long)vaddr), get_order(size));
long addr=(long)vaddr+XCHAL_KSEG_CACHED_VADDR-XCHAL_KSEG_BYPASS_VADDR;
if (addr < 0 || addr >= XCHAL_KSEG_SIZE)
BUG();
free_pages(addr, get_order(size));
}
......
// TODO verify coprocessor handling
/*
* arch/xtensa/kernel/process.c
*
......@@ -43,7 +42,7 @@
#include <asm/irq.h>
#include <asm/atomic.h>
#include <asm/asm-offsets.h>
#include <asm/coprocessor.h>
#include <asm/regs.h>
extern void ret_from_fork(void);
......@@ -67,25 +66,6 @@ void (*pm_power_off)(void) = NULL;
EXPORT_SYMBOL(pm_power_off);
#if XCHAL_CP_NUM > 0
/*
* Coprocessor ownership.
*/
coprocessor_info_t coprocessor_info[] = {
{ 0, XTENSA_CPE_CP0_OFFSET },
{ 0, XTENSA_CPE_CP1_OFFSET },
{ 0, XTENSA_CPE_CP2_OFFSET },
{ 0, XTENSA_CPE_CP3_OFFSET },
{ 0, XTENSA_CPE_CP4_OFFSET },
{ 0, XTENSA_CPE_CP5_OFFSET },
{ 0, XTENSA_CPE_CP6_OFFSET },
{ 0, XTENSA_CPE_CP7_OFFSET },
};
#endif
/*
* Powermanagement idle function, if any is provided by the platform.
*/
......@@ -110,12 +90,10 @@ void cpu_idle(void)
void exit_thread(void)
{
release_coprocessors(current); /* Empty macro if no CPs are defined */
}
void flush_thread(void)
{
release_coprocessors(current); /* Empty macro if no CPs are defined */
}
/*
......@@ -275,7 +253,7 @@ void do_copy_regs (xtensa_gregset_t *elfregs, struct pt_regs *regs,
*/
elfregs->pc = regs->pc;
elfregs->ps = (regs->ps & ~XCHAL_PS_EXCM_MASK);
elfregs->ps = (regs->ps & ~(1 << PS_EXCM_BIT));
elfregs->exccause = regs->exccause;
elfregs->excvaddr = regs->excvaddr;
elfregs->windowbase = regs->windowbase;
......@@ -325,7 +303,7 @@ void do_restore_regs (xtensa_gregset_t *elfregs, struct pt_regs *regs,
*/
regs->pc = elfregs->pc;
regs->ps = (elfregs->ps | XCHAL_PS_EXCM_MASK);
regs->ps = (elfregs->ps | (1 << PS_EXCM_BIT));
regs->exccause = elfregs->exccause;
regs->excvaddr = elfregs->excvaddr;
regs->windowbase = elfregs->windowbase;
......@@ -459,16 +437,7 @@ int do_restore_fpregs (elf_fpregset_t *fpregs, struct pt_regs *regs,
int
dump_task_fpu(struct pt_regs *regs, struct task_struct *task, elf_fpregset_t *r)
{
/* see asm/coprocessor.h for this magic number 16 */
#if XTENSA_CP_EXTRA_SIZE > 16
do_save_fpregs (r, regs, task);
/* For now, bit 16 means some extra state may be present: */
// FIXME!! need to track to return more accurate mask
return 0x10000 | XCHAL_CP_MASK;
#else
return 0; /* no coprocessors active on this processor */
#endif
}
/*
......
......@@ -96,7 +96,7 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
/* Note: PS.EXCM is not set while user task is running;
* its being set in regs is for exception handling
* convenience. */
tmp = (regs->ps & ~XCHAL_PS_EXCM_MASK);
tmp = (regs->ps & ~(1 << PS_EXCM_BIT));
break;
case REG_WB:
tmp = regs->windowbase;
......
......@@ -42,8 +42,6 @@
#include <asm/page.h>
#include <asm/setup.h>
#include <xtensa/config/system.h>
#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
struct screen_info screen_info = { 0, 24, 0, 0, 0, 80, 0, 0, 0, 24, 1, 16};
#endif
......@@ -336,7 +334,7 @@ c_show(struct seq_file *f, void *slot)
/* high-level stuff */
seq_printf(f,"processor\t: 0\n"
"vendor_id\t: Tensilica\n"
"model\t\t: Xtensa " XCHAL_HW_RELEASE_NAME "\n"
"model\t\t: Xtensa " XCHAL_HW_VERSION_NAME "\n"