Commit 0e2ee0c0 authored by Andrew Lunn's avatar Andrew Lunn Committed by Jason Cooper

arm: kirkwood: Instantiate cpufreq driver

Register a platform driver structure for the cpufreq driver.
Signed-off-by: default avatarAndrew Lunn <andrew@lunn.ch>
Tested-by: default avatarAdam Baker <linux@baker-net.org.uk>
Signed-off-by: default avatarJason Cooper <jason@lakedaemon.net>
parent 3207792e
......@@ -501,6 +501,7 @@ config ARCH_DOVE
config ARCH_KIRKWOOD
bool "Marvell Kirkwood"
select ARCH_HAS_CPUFREQ
select ARCH_REQUIRE_GPIOLIB
select CPU_FEROCEON
select GENERIC_CLOCKEVENTS
......
......@@ -92,6 +92,8 @@ static void __init kirkwood_dt_init(void)
kirkwood_l2_init();
kirkwood_cpufreq_init();
/* Setup root of clk tree */
kirkwood_of_clk_init();
......
......@@ -603,6 +603,29 @@ void __init kirkwood_audio_init(void)
platform_device_register(&kirkwood_pcm_device);
}
/*****************************************************************************
* CPU Frequency
****************************************************************************/
static struct resource kirkwood_cpufreq_resources[] = {
[0] = {
.start = CPU_CONTROL_PHYS,
.end = CPU_CONTROL_PHYS + 3,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device kirkwood_cpufreq_device = {
.name = "kirkwood-cpufreq",
.id = -1,
.num_resources = ARRAY_SIZE(kirkwood_cpufreq_resources),
.resource = kirkwood_cpufreq_resources,
};
void __init kirkwood_cpufreq_init(void)
{
platform_device_register(&kirkwood_cpufreq_device);
}
/*****************************************************************************
* General
****************************************************************************/
......
......@@ -51,6 +51,8 @@ void kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
int (*dev_ready)(struct mtd_info *));
void kirkwood_audio_init(void);
void kirkwood_cpuidle_init(void);
void kirkwood_cpufreq_init(void);
void kirkwood_restart(char, const char *);
void kirkwood_clk_init(void);
......
......@@ -17,6 +17,7 @@
#define CPU_CONFIG_ERROR_PROP 0x00000004
#define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104)
#define CPU_CONTROL_PHYS (BRIDGE_PHYS_BASE + 0x0104)
#define CPU_RESET 0x00000002
#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108)
......@@ -69,6 +70,7 @@
#define CGC_RUNIT (1 << 7)
#define CGC_XOR0 (1 << 8)
#define CGC_AUDIO (1 << 9)
#define CGC_POWERSAVE (1 << 11)
#define CGC_SATA0 (1 << 14)
#define CGC_SATA1 (1 << 15)
#define CGC_XOR1 (1 << 16)
......
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