Commit 08441a96 authored by Robert Yang's avatar Robert Yang Committed by Stephen Boyd

clk: tegra: Return the exact clock rate from clk_round_rate

The current behavior is that clk_round_rate would return the same clock
rate passed to it for valid PLL configurations. This change will return
the exact rate the PLL will provide in accordance with clk API.
Signed-off-by: default avatarRobert Yang <decatf@gmail.com>
Reviewed-by: Dmitry Osipenko's avatarDmitry Osipenko <digetx@gmail.com>
Tested-by: Dmitry Osipenko's avatarDmitry Osipenko <digetx@gmail.com>
Acked-by: default avatarThierry Reding <treding@nvidia.com>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent b158aeea
......@@ -590,12 +590,13 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
cfg->n = cfg->output_rate / cfreq;
cfg->cpcon = OUT_OF_TABLE_CPCON;
if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) ||
(1 << p_div) > divp_max(pll)
|| cfg->output_rate > pll->params->vco_max) {
if (cfg->m == 0 || cfg->m > divm_max(pll) ||
cfg->n > divn_max(pll) || (1 << p_div) > divp_max(pll) ||
cfg->output_rate > pll->params->vco_max) {
return -EINVAL;
}
cfg->output_rate = cfg->n * DIV_ROUND_UP(parent_rate, cfg->m);
cfg->output_rate >>= p_div;
if (pll->params->pdiv_tohw) {
......
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