Commit 0493e649 authored by Patrice Chotard's avatar Patrice Chotard Committed by Linus Walleij

pinctrl: add abx500 pinctrl driver core

This adds the AB8500 core driver, which will be utilized by
the follow-on drivers for different ABx500 variants.
Sselect the driver from the DBX500_SOC, as this chip is
powering and clocking that SoC.

Cc: Samuel Ortiz <>
Signed-off-by: default avatarPatrice Chotard <>
Signed-off-by: Linus Walleij's avatarLinus Walleij <>
parent a718ff6f
......@@ -11,6 +11,7 @@ config UX500_SOC_COMMON
select PINCTRL
select PINCTRL_ABX500
select PL310_ERRATA_753970 if CACHE_PL310
config UX500_SOC_DB8500
......@@ -90,26 +90,9 @@ static struct platform_device snowball_gpio_en_3v3_regulator_dev = {
static struct ab8500_gpio_platform_data ab8500_gpio_pdata = {
static struct abx500_gpio_platform_data ab8500_gpio_pdata = {
.gpio_base = MOP500_AB8500_PIN_GPIO(1),
.irq_base = MOP500_AB8500_VIR_GPIO_IRQ_BASE,
/* config_reg is the initial configuration of ab8500 pins.
* The pins can be configured as GPIO or alt functions based
* on value present in GpioSel1 to GpioSel6 and AlternatFunction
* register. This is the array of 7 configuration settings.
* One has to compile time decide these settings. Below is the
* explanation of these setting
* GpioSel1 = 0x00 => Pins GPIO1 to GPIO8 are not used as GPIO
* GpioSel2 = 0x1E => Pins GPIO10 to GPIO13 are configured as GPIO
* GpioSel3 = 0x80 => Pin GPIO24 is configured as GPIO
* GpioSel4 = 0x01 => Pin GPIo25 is configured as GPIO
* GpioSel5 = 0x7A => Pins GPIO34, GPIO36 to GPIO39 are conf as GPIO
* GpioSel6 = 0x00 => Pins GPIO41 & GPIo42 are not configured as GPIO
* AlternaFunction = 0x00 => If Pins GPIO10 to 13 are not configured
* as GPIO then this register selectes the alternate fucntions
.config_reg = {0x00, 0x1E, 0x80, 0x01,
0x7A, 0x00, 0x00},
/* ab8500-codec */
......@@ -26,6 +26,13 @@ config DEBUG_PINCTRL
Say Y here to add some extra checks and diagnostics to PINCTRL calls.
config PINCTRL_ABX500
bool "ST-Ericsson ABx500 family Mixed Signal Circuit gpio functions"
depends on AB8500_CORE
Select this to enable the ABx500 family IC GPIO driver
config PINCTRL_AT91
bool "AT91 pinctrl driver"
depends on OF
......@@ -9,6 +9,7 @@ ifeq ($(CONFIG_OF),y)
obj-$(CONFIG_PINCTRL) += devicetree.o
obj-$(CONFIG_GENERIC_PINCONF) += pinconf-generic.o
obj-$(CONFIG_PINCTRL_ABX500) += pinctrl-abx500.o
obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o
obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o
obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
This diff is collapsed.
/* Package definitions */
#define PINCTRL_AB8500 0
#define PINCTRL_AB8540 1
#define PINCTRL_AB9540 2
#define PINCTRL_AB8505 3
/* pins alternate function */
enum abx500_pin_func {
* struct abx500_function - ABx500 pinctrl mux function
* @name: The name of the function, exported to pinctrl core.
* @groups: An array of pin groups that may select this function.
* @ngroups: The number of entries in @groups.
struct abx500_function {
const char *name;
const char * const *groups;
unsigned ngroups;
* struct abx500_pingroup - describes a ABx500 pin group
* @name: the name of this specific pin group
* @pins: an array of discrete physical pins used in this group, taken
* from the driver-local pin enumeration space
* @num_pins: the number of pins in this group array, i.e. the number of
* elements in .pins so we can iterate over that array
* @altsetting: the altsetting to apply to all pins in this group to
* configure them to be used by a function
struct abx500_pingroup {
const char *name;
const unsigned int *pins;
const unsigned npins;
int altsetting;
#define ALTERNATE_FUNCTIONS(pin, sel_bit, alt1, alt2, alta, altb, altc) \
{ \
.pin_number = pin, \
.gpiosel_bit = sel_bit, \
.alt_bit1 = alt1, \
.alt_bit2 = alt2, \
.alta_val = alta, \
.altb_val = altb, \
.altc_val = altc, \
#define UNUSED -1
* struct alternate_functions
* @pin_number: The pin number
* @gpiosel_bit: Control bit in GPIOSEL register,
* @alt_bit1: First AlternateFunction bit used to select the
* alternate function
* @alt_bit2: Second AlternateFunction bit used to select the
* alternate function
* these 3 following fields are necessary due to none
* coherency on how to select the altA, altB and altC
* function between the ABx500 SOC family when using
* alternatfunc register.
* @alta_val: value to write in alternatfunc to select altA function
* @altb_val: value to write in alternatfunc to select altB function
* @altc_val: value to write in alternatfunc to select altC function
struct alternate_functions {
unsigned pin_number;
s8 gpiosel_bit;
s8 alt_bit1;
s8 alt_bit2;
u8 alta_val;
u8 altb_val;
u8 altc_val;
* struct pullud - specific pull up/down feature
* @first_pin: The pin number of the first pins which support
* specific pull up/down
* @last_pin: The pin number of the last pins
struct pullud {
unsigned first_pin;
unsigned last_pin;
#define GPIO_IRQ_CLUSTER(a, b, c) \
{ \
.start = a, \
.end = b, \
.offset = c, \
* struct abx500_gpio_irq_cluster - indicates GPIOs which are interrupt
* capable
* @start: The pin number of the first pin interrupt capable
* @end: The pin number of the last pin interrupt capable
* @offset: offset used to compute specific setting strategy of
* the interrupt line
struct abx500_gpio_irq_cluster {
int start;
int end;
int offset;
* struct abx500_pinrange - map pin numbers to GPIO offsets
* @offset: offset into the GPIO local numberspace, incidentally
* identical to the offset into the local pin numberspace
* @npins: number of pins to map from both offsets
* @altfunc: altfunc setting to be used to enable GPIO on a pin in
* this range (may vary)
struct abx500_pinrange {
unsigned int offset;
unsigned int npins;
int altfunc;
#define ABX500_PINRANGE(a, b, c) { .offset = a, .npins = b, .altfunc = c }
* struct abx500_pinctrl_soc_data - ABx500 pin controller per-SoC configuration
* @gpio_ranges: An array of GPIO ranges for this SoC
* @gpio_num_ranges: The number of GPIO ranges for this SoC
* @pins: An array describing all pins the pin controller affects.
* All pins which are also GPIOs must be listed first within the
* array, and be numbered identically to the GPIO controller's
* numbering.
* @npins: The number of entries in @pins.
* @functions: The functions supported on this SoC.
* @nfunction: The number of entries in @functions.
* @groups: An array describing all pin groups the pin SoC supports.
* @ngroups: The number of entries in @groups.
* @alternate_functions: array describing pins which supports alternate and
* how to set it.
* @pullud: array describing pins which supports pull up/down
* specific registers.
* @gpio_irq_cluster: An array of GPIO interrupt capable for this SoC
* @ngpio_irq_cluster: The number of GPIO inetrrupt capable for this SoC
* @irq_gpio_rising_offset: Interrupt offset used as base to compute specific
* setting strategy of the rising interrupt line
* @irq_gpio_falling_offset: Interrupt offset used as base to compute specific
* setting strategy of the falling interrupt line
* @irq_gpio_factor: Factor used to compute specific setting strategy of
* the interrupt line
struct abx500_pinctrl_soc_data {
const struct abx500_pinrange *gpio_ranges;
unsigned gpio_num_ranges;
const struct pinctrl_pin_desc *pins;
unsigned npins;
const struct abx500_function *functions;
unsigned nfunctions;
const struct abx500_pingroup *groups;
unsigned ngroups;
struct alternate_functions *alternate_functions;
struct pullud *pullud;
struct abx500_gpio_irq_cluster *gpio_irq_cluster;
unsigned ngpio_irq_cluster;
int irq_gpio_rising_offset;
int irq_gpio_falling_offset;
int irq_gpio_factor;
#endif /* PINCTRL_PINCTRL_ABx500_H */
......@@ -14,10 +14,21 @@
* registers.
struct ab8500_gpio_platform_data {
struct abx500_gpio_platform_data {
int gpio_base;
u32 irq_base;
u8 config_reg[8];
enum abx500_gpio_pull_updown {
ABX500_GPIO_PULL_UP = 0x3,
enum abx500_gpio_vinsel {
#endif /* _AB8500_GPIO_H */
......@@ -385,7 +385,7 @@ struct ab8500_platform_data {
struct ab8500_regulator_reg_init *regulator_reg_init;
int num_regulator;
struct regulator_init_data *regulator;
struct ab8500_gpio_platform_data *gpio;
struct abx500_gpio_platform_data *gpio;
struct ab8500_codec_platform_data *codec;
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