core.c 59.9 KB
Newer Older
1
/*
2
 * Performance events x86 architecture code
3
 *
4 5 6 7
 *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
 *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
 *  Copyright (C) 2009 Jaswinder Singh Rajput
 *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8
 *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
9
 *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10
 *  Copyright (C) 2009 Google, Inc., Stephane Eranian
11 12 13 14
 *
 *  For licencing details see kernel-base/COPYING
 */

15
#include <linux/perf_event.h>
16 17 18 19
#include <linux/capability.h>
#include <linux/notifier.h>
#include <linux/hardirq.h>
#include <linux/kprobes.h>
20 21
#include <linux/export.h>
#include <linux/init.h>
22
#include <linux/kdebug.h>
23
#include <linux/sched/mm.h>
24
#include <linux/sched/clock.h>
25
#include <linux/uaccess.h>
26
#include <linux/slab.h>
27
#include <linux/cpu.h>
28
#include <linux/bitops.h>
29
#include <linux/device.h>
30 31

#include <asm/apic.h>
32
#include <asm/stacktrace.h>
Peter Zijlstra's avatar
Peter Zijlstra committed
33
#include <asm/nmi.h>
34
#include <asm/smp.h>
35
#include <asm/alternative.h>
36
#include <asm/mmu_context.h>
37
#include <asm/tlbflush.h>
38
#include <asm/timer.h>
39 40
#include <asm/desc.h>
#include <asm/ldt.h>
41
#include <asm/unwind.h>
42

43
#include "perf_event.h"
44 45

struct x86_pmu x86_pmu __read_mostly;
46

47
DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
48 49
	.enabled = 1,
};
50

51
DEFINE_STATIC_KEY_FALSE(rdpmc_always_available_key);
52

53
u64 __read_mostly hw_cache_event_ids
54 55 56
				[PERF_COUNT_HW_CACHE_MAX]
				[PERF_COUNT_HW_CACHE_OP_MAX]
				[PERF_COUNT_HW_CACHE_RESULT_MAX];
57
u64 __read_mostly hw_cache_extra_regs
58 59 60
				[PERF_COUNT_HW_CACHE_MAX]
				[PERF_COUNT_HW_CACHE_OP_MAX]
				[PERF_COUNT_HW_CACHE_RESULT_MAX];
61

62
/*
63 64
 * Propagate event elapsed time into the generic event.
 * Can only be executed on the CPU where the event is active.
65 66
 * Returns the delta events processed.
 */
67
u64 x86_perf_event_update(struct perf_event *event)
68
{
69
	struct hw_perf_event *hwc = &event->hw;
70
	int shift = 64 - x86_pmu.cntval_bits;
71
	u64 prev_raw_count, new_raw_count;
72
	int idx = hwc->idx;
73
	u64 delta;
74

75
	if (idx == INTEL_PMC_IDX_FIXED_BTS)
76 77
		return 0;

78
	/*
79
	 * Careful: an NMI might modify the previous event value.
80 81 82
	 *
	 * Our tactic to handle this is to first atomically read and
	 * exchange a new raw count - then add that new-prev delta
83
	 * count to the generic event atomically:
84 85
	 */
again:
86
	prev_raw_count = local64_read(&hwc->prev_count);
87
	rdpmcl(hwc->event_base_rdpmc, new_raw_count);
88

89
	if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
90 91 92 93 94 95
					new_raw_count) != prev_raw_count)
		goto again;

	/*
	 * Now we have the new raw value and have updated the prev
	 * timestamp already. We can now calculate the elapsed delta
96
	 * (event-)time and add that to the generic event.
97 98
	 *
	 * Careful, not all hw sign-extends above the physical width
99
	 * of the count.
100
	 */
101 102
	delta = (new_raw_count << shift) - (prev_raw_count << shift);
	delta >>= shift;
103

104 105
	local64_add(delta, &event->count);
	local64_sub(delta, &hwc->period_left);
106 107

	return new_raw_count;
108 109
}

110 111 112 113 114
/*
 * Find and validate any extra registers to set up.
 */
static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
{
115
	struct hw_perf_event_extra *reg;
116 117
	struct extra_reg *er;

118
	reg = &event->hw.extra_reg;
119 120 121 122 123 124 125 126 127

	if (!x86_pmu.extra_regs)
		return 0;

	for (er = x86_pmu.extra_regs; er->msr; er++) {
		if (er->event != (config & er->config_mask))
			continue;
		if (event->attr.config1 & ~er->valid_mask)
			return -EINVAL;
128 129 130
		/* Check if the extra msrs can be safely accessed*/
		if (!er->extra_msr_access)
			return -ENXIO;
131 132 133 134

		reg->idx = er->idx;
		reg->config = event->attr.config1;
		reg->reg = er->msr;
135 136 137 138 139
		break;
	}
	return 0;
}

140
static atomic_t active_events;
141
static atomic_t pmc_refcount;
Peter Zijlstra's avatar
Peter Zijlstra committed
142 143
static DEFINE_MUTEX(pmc_reserve_mutex);

144 145
#ifdef CONFIG_X86_LOCAL_APIC

Peter Zijlstra's avatar
Peter Zijlstra committed
146 147 148 149
static bool reserve_pmc_hardware(void)
{
	int i;

150
	for (i = 0; i < x86_pmu.num_counters; i++) {
151
		if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
Peter Zijlstra's avatar
Peter Zijlstra committed
152 153 154
			goto perfctr_fail;
	}

155
	for (i = 0; i < x86_pmu.num_counters; i++) {
156
		if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
Peter Zijlstra's avatar
Peter Zijlstra committed
157 158 159 160 161 162 163
			goto eventsel_fail;
	}

	return true;

eventsel_fail:
	for (i--; i >= 0; i--)
164
		release_evntsel_nmi(x86_pmu_config_addr(i));
Peter Zijlstra's avatar
Peter Zijlstra committed
165

166
	i = x86_pmu.num_counters;
Peter Zijlstra's avatar
Peter Zijlstra committed
167 168 169

perfctr_fail:
	for (i--; i >= 0; i--)
170
		release_perfctr_nmi(x86_pmu_event_addr(i));
Peter Zijlstra's avatar
Peter Zijlstra committed
171 172 173 174 175 176 177 178

	return false;
}

static void release_pmc_hardware(void)
{
	int i;

179
	for (i = 0; i < x86_pmu.num_counters; i++) {
180 181
		release_perfctr_nmi(x86_pmu_event_addr(i));
		release_evntsel_nmi(x86_pmu_config_addr(i));
Peter Zijlstra's avatar
Peter Zijlstra committed
182 183 184
	}
}

185 186 187 188 189 190 191
#else

static bool reserve_pmc_hardware(void) { return true; }
static void release_pmc_hardware(void) {}

#endif

192 193
static bool check_hw_exists(void)
{
194 195
	u64 val, val_fail = -1, val_new= ~0;
	int i, reg, reg_fail = -1, ret = 0;
196
	int bios_fail = 0;
197
	int reg_safe = -1;
198

199 200 201 202 203
	/*
	 * Check to see if the BIOS enabled any of the counters, if so
	 * complain and bail.
	 */
	for (i = 0; i < x86_pmu.num_counters; i++) {
204
		reg = x86_pmu_config_addr(i);
205 206 207
		ret = rdmsrl_safe(reg, &val);
		if (ret)
			goto msr_fail;
208 209 210 211
		if (val & ARCH_PERFMON_EVENTSEL_ENABLE) {
			bios_fail = 1;
			val_fail = val;
			reg_fail = reg;
212 213
		} else {
			reg_safe = i;
214
		}
215 216 217 218 219 220 221 222
	}

	if (x86_pmu.num_counters_fixed) {
		reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
		ret = rdmsrl_safe(reg, &val);
		if (ret)
			goto msr_fail;
		for (i = 0; i < x86_pmu.num_counters_fixed; i++) {
223 224 225 226 227
			if (val & (0x03 << i*4)) {
				bios_fail = 1;
				val_fail = val;
				reg_fail = reg;
			}
228 229 230
		}
	}

231 232 233 234 235 236 237 238 239 240 241
	/*
	 * If all the counters are enabled, the below test will always
	 * fail.  The tools will also become useless in this scenario.
	 * Just fail and disable the hardware counters.
	 */

	if (reg_safe == -1) {
		reg = reg_safe;
		goto msr_fail;
	}

242
	/*
243 244 245
	 * Read the current value, change it and read it back to see if it
	 * matches, this is needed to detect certain hardware emulators
	 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
246
	 */
247
	reg = x86_pmu_event_addr(reg_safe);
248 249 250
	if (rdmsrl_safe(reg, &val))
		goto msr_fail;
	val ^= 0xffffUL;
251 252
	ret = wrmsrl_safe(reg, val);
	ret |= rdmsrl_safe(reg, &val_new);
253
	if (ret || val != val_new)
254
		goto msr_fail;
255

256 257 258
	/*
	 * We still allow the PMU driver to operate:
	 */
259
	if (bios_fail) {
260 261 262
		pr_cont("Broken BIOS detected, complain to your hardware vendor.\n");
		pr_err(FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n",
			      reg_fail, val_fail);
263
	}
264 265

	return true;
266 267

msr_fail:
268 269 270 271 272 273 274
	if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
		pr_cont("PMU not available due to virtualization, using software events only.\n");
	} else {
		pr_cont("Broken PMU hardware detected, using software events only.\n");
		pr_err("Failed to access perfctr msr (MSR %x is %Lx)\n",
		       reg, val_new);
	}
275

276
	return false;
277 278
}

279
static void hw_perf_event_destroy(struct perf_event *event)
Peter Zijlstra's avatar
Peter Zijlstra committed
280
{
281
	x86_release_hardware();
282
	atomic_dec(&active_events);
Peter Zijlstra's avatar
Peter Zijlstra committed
283 284
}

285 286 287 288 289 290 291 292
void hw_perf_lbr_event_destroy(struct perf_event *event)
{
	hw_perf_event_destroy(event);

	/* undo the lbr/bts event accounting */
	x86_del_exclusive(x86_lbr_exclusive_lbr);
}

293 294 295 296 297
static inline int x86_pmu_initialized(void)
{
	return x86_pmu.handle_irq != NULL;
}

298
static inline int
299
set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
300
{
301
	struct perf_event_attr *attr = &event->attr;
302 303 304 305 306
	unsigned int cache_type, cache_op, cache_result;
	u64 config, val;

	config = attr->config;

307
	cache_type = (config >> 0) & 0xff;
308 309
	if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
		return -EINVAL;
310
	cache_type = array_index_nospec(cache_type, PERF_COUNT_HW_CACHE_MAX);
311 312 313 314

	cache_op = (config >>  8) & 0xff;
	if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
		return -EINVAL;
315
	cache_op = array_index_nospec(cache_op, PERF_COUNT_HW_CACHE_OP_MAX);
316 317 318 319

	cache_result = (config >> 16) & 0xff;
	if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
		return -EINVAL;
320
	cache_result = array_index_nospec(cache_result, PERF_COUNT_HW_CACHE_RESULT_MAX);
321 322 323 324 325 326 327 328 329 330

	val = hw_cache_event_ids[cache_type][cache_op][cache_result];

	if (val == 0)
		return -ENOENT;

	if (val == -1)
		return -EINVAL;

	hwc->config |= val;
331 332
	attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result];
	return x86_pmu_extra_regs(val, event);
333 334
}

335 336 337 338
int x86_reserve_hardware(void)
{
	int err = 0;

339
	if (!atomic_inc_not_zero(&pmc_refcount)) {
340
		mutex_lock(&pmc_reserve_mutex);
341
		if (atomic_read(&pmc_refcount) == 0) {
342 343 344 345 346 347
			if (!reserve_pmc_hardware())
				err = -EBUSY;
			else
				reserve_ds_buffers();
		}
		if (!err)
348
			atomic_inc(&pmc_refcount);
349 350 351 352 353 354 355 356
		mutex_unlock(&pmc_reserve_mutex);
	}

	return err;
}

void x86_release_hardware(void)
{
357
	if (atomic_dec_and_mutex_lock(&pmc_refcount, &pmc_reserve_mutex)) {
358 359 360 361 362 363
		release_pmc_hardware();
		release_ds_buffers();
		mutex_unlock(&pmc_reserve_mutex);
	}
}

364 365 366 367 368 369
/*
 * Check if we can create event of a certain type (that no conflicting events
 * are present).
 */
int x86_add_exclusive(unsigned int what)
{
370
	int i;
371

372 373 374 375 376
	/*
	 * When lbr_pt_coexist we allow PT to coexist with either LBR or BTS.
	 * LBR and BTS are still mutually exclusive.
	 */
	if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
377 378
		return 0;

379 380 381 382 383 384 385 386
	if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) {
		mutex_lock(&pmc_reserve_mutex);
		for (i = 0; i < ARRAY_SIZE(x86_pmu.lbr_exclusive); i++) {
			if (i != what && atomic_read(&x86_pmu.lbr_exclusive[i]))
				goto fail_unlock;
		}
		atomic_inc(&x86_pmu.lbr_exclusive[what]);
		mutex_unlock(&pmc_reserve_mutex);
387
	}
388

389 390
	atomic_inc(&active_events);
	return 0;
391

392
fail_unlock:
393
	mutex_unlock(&pmc_reserve_mutex);
394
	return -EBUSY;
395 396 397 398
}

void x86_del_exclusive(unsigned int what)
{
399
	if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
400 401
		return;

402
	atomic_dec(&x86_pmu.lbr_exclusive[what]);
403
	atomic_dec(&active_events);
404 405
}

406
int x86_setup_perfctr(struct perf_event *event)
407 408 409 410 411
{
	struct perf_event_attr *attr = &event->attr;
	struct hw_perf_event *hwc = &event->hw;
	u64 config;

412
	if (!is_sampling_event(event)) {
413 414
		hwc->sample_period = x86_pmu.max_period;
		hwc->last_period = hwc->sample_period;
415
		local64_set(&hwc->period_left, hwc->sample_period);
416 417 418
	}

	if (attr->type == PERF_TYPE_RAW)
419
		return x86_pmu_extra_regs(event->attr.config, event);
420 421

	if (attr->type == PERF_TYPE_HW_CACHE)
422
		return set_ext_hw_attr(hwc, event);
423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440

	if (attr->config >= x86_pmu.max_events)
		return -EINVAL;

	/*
	 * The generic map:
	 */
	config = x86_pmu.event_map(attr->config);

	if (config == 0)
		return -ENOENT;

	if (config == -1LL)
		return -EINVAL;

	/*
	 * Branch tracing:
	 */
Peter Zijlstra's avatar
Peter Zijlstra committed
441 442
	if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS &&
	    !attr->freq && hwc->sample_period == 1) {
443
		/* BTS is not supported by this architecture. */
444
		if (!x86_pmu.bts_active)
445 446 447 448 449
			return -EOPNOTSUPP;

		/* BTS is currently only allowed for user-mode. */
		if (!attr->exclude_kernel)
			return -EOPNOTSUPP;
450 451 452 453 454 455

		/* disallow bts if conflicting events are present */
		if (x86_add_exclusive(x86_lbr_exclusive_lbr))
			return -EBUSY;

		event->destroy = hw_perf_lbr_event_destroy;
456 457 458 459 460 461
	}

	hwc->config |= config;

	return 0;
}
462

463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492
/*
 * check that branch_sample_type is compatible with
 * settings needed for precise_ip > 1 which implies
 * using the LBR to capture ALL taken branches at the
 * priv levels of the measurement
 */
static inline int precise_br_compat(struct perf_event *event)
{
	u64 m = event->attr.branch_sample_type;
	u64 b = 0;

	/* must capture all branches */
	if (!(m & PERF_SAMPLE_BRANCH_ANY))
		return 0;

	m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER;

	if (!event->attr.exclude_user)
		b |= PERF_SAMPLE_BRANCH_USER;

	if (!event->attr.exclude_kernel)
		b |= PERF_SAMPLE_BRANCH_KERNEL;

	/*
	 * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
	 */

	return m == b;
}

493
int x86_pmu_max_precise(void)
494
{
495 496 497 498 499
	int precise = 0;

	/* Support for constant skid */
	if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) {
		precise++;
500

501 502
		/* Support for IP fixup */
		if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2)
503 504
			precise++;

505 506 507 508 509
		if (x86_pmu.pebs_prec_dist)
			precise++;
	}
	return precise;
}
510

511 512 513 514
int x86_pmu_hw_config(struct perf_event *event)
{
	if (event->attr.precise_ip) {
		int precise = x86_pmu_max_precise();
515 516 517

		if (event->attr.precise_ip > precise)
			return -EOPNOTSUPP;
518 519 520 521

		/* There's no sense in having PEBS for non sampling events: */
		if (!is_sampling_event(event))
			return -EINVAL;
522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550
	}
	/*
	 * check that PEBS LBR correction does not conflict with
	 * whatever the user is asking with attr->branch_sample_type
	 */
	if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format < 2) {
		u64 *br_type = &event->attr.branch_sample_type;

		if (has_branch_stack(event)) {
			if (!precise_br_compat(event))
				return -EOPNOTSUPP;

			/* branch_sample_type is compatible */

		} else {
			/*
			 * user did not specify  branch_sample_type
			 *
			 * For PEBS fixups, we capture all
			 * the branches at the priv level of the
			 * event.
			 */
			*br_type = PERF_SAMPLE_BRANCH_ANY;

			if (!event->attr.exclude_user)
				*br_type |= PERF_SAMPLE_BRANCH_USER;

			if (!event->attr.exclude_kernel)
				*br_type |= PERF_SAMPLE_BRANCH_KERNEL;
551
		}
552 553
	}

554 555 556
	if (event->attr.branch_sample_type & PERF_SAMPLE_BRANCH_CALL_STACK)
		event->attach_state |= PERF_ATTACH_TASK_DATA;

557 558 559 560
	/*
	 * Generate PMC IRQs:
	 * (keep 'enabled' bit clear for now)
	 */
561
	event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
562 563 564 565

	/*
	 * Count user and OS events unless requested not to
	 */
566 567 568 569
	if (!event->attr.exclude_user)
		event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
	if (!event->attr.exclude_kernel)
		event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
570

571 572
	if (event->attr.type == PERF_TYPE_RAW)
		event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
573

574 575 576 577 578 579
	if (event->attr.sample_period && x86_pmu.limit_period) {
		if (x86_pmu.limit_period(event, event->attr.sample_period) >
				event->attr.sample_period)
			return -EINVAL;
	}

580
	return x86_setup_perfctr(event);
581 582
}

583
/*
584
 * Setup the hardware configuration for a given attr_type
585
 */
586
static int __x86_pmu_event_init(struct perf_event *event)
587
{
Peter Zijlstra's avatar
Peter Zijlstra committed
588
	int err;
589

590 591
	if (!x86_pmu_initialized())
		return -ENODEV;
592

593
	err = x86_reserve_hardware();
Peter Zijlstra's avatar
Peter Zijlstra committed
594 595 596
	if (err)
		return err;

597
	atomic_inc(&active_events);
598
	event->destroy = hw_perf_event_destroy;
599

600 601 602
	event->hw.idx = -1;
	event->hw.last_cpu = -1;
	event->hw.last_tag = ~0ULL;
603

604 605
	/* mark unused */
	event->hw.extra_reg.idx = EXTRA_REG_NONE;
606 607
	event->hw.branch_reg.idx = EXTRA_REG_NONE;

608
	return x86_pmu.hw_config(event);
609 610
}

611
void x86_pmu_disable_all(void)
612
{
613
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
614 615
	int idx;

616
	for (idx = 0; idx < x86_pmu.num_counters; idx++) {
617 618
		u64 val;

619
		if (!test_bit(idx, cpuc->active_mask))
620
			continue;
621
		rdmsrl(x86_pmu_config_addr(idx), val);
622
		if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
623
			continue;
624
		val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
625
		wrmsrl(x86_pmu_config_addr(idx), val);
626 627 628
	}
}

629 630 631 632 633 634 635 636 637 638 639 640 641
/*
 * There may be PMI landing after enabled=0. The PMI hitting could be before or
 * after disable_all.
 *
 * If PMI hits before disable_all, the PMU will be disabled in the NMI handler.
 * It will not be re-enabled in the NMI handler again, because enabled=0. After
 * handling the NMI, disable_all will be called, which will not change the
 * state either. If PMI hits after disable_all, the PMU is already disabled
 * before entering NMI handler. The NMI handler will not change the state
 * either.
 *
 * So either situation is harmless.
 */
Peter Zijlstra's avatar
Peter Zijlstra committed
642
static void x86_pmu_disable(struct pmu *pmu)
643
{
644
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
645

646
	if (!x86_pmu_initialized())
647
		return;
648

649 650 651 652 653 654
	if (!cpuc->enabled)
		return;

	cpuc->n_added = 0;
	cpuc->enabled = 0;
	barrier();
655 656

	x86_pmu.disable_all();
657
}
658

659
void x86_pmu_enable_all(int added)
660
{
661
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
662 663
	int idx;

664
	for (idx = 0; idx < x86_pmu.num_counters; idx++) {
665
		struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
666

667
		if (!test_bit(idx, cpuc->active_mask))
668
			continue;
669

670
		__x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
671 672 673
	}
}

Peter Zijlstra's avatar
Peter Zijlstra committed
674
static struct pmu pmu;
675 676 677 678 679 680

static inline int is_x86_event(struct perf_event *event)
{
	return event->pmu == &pmu;
}

681 682 683 684 685 686 687 688 689 690 691 692
/*
 * Event scheduler state:
 *
 * Assign events iterating over all events and counters, beginning
 * with events with least weights first. Keep the current iterator
 * state in struct sched_state.
 */
struct sched_state {
	int	weight;
	int	event;		/* event index */
	int	counter;	/* counter index */
	int	unassigned;	/* number of events to be assigned left */
693
	int	nr_gp;		/* number of GP counters used */
694 695 696
	unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
};

697 698 699
/* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
#define	SCHED_STATES_MAX	2

700 701 702
struct perf_sched {
	int			max_weight;
	int			max_events;
703 704
	int			max_gp;
	int			saved_states;
705
	struct event_constraint	**constraints;
706
	struct sched_state	state;
707
	struct sched_state	saved[SCHED_STATES_MAX];
708 709 710 711 712
};

/*
 * Initialize interator that runs through all events and counters.
 */
713
static void perf_sched_init(struct perf_sched *sched, struct event_constraint **constraints,
714
			    int num, int wmin, int wmax, int gpmax)
715 716 717 718 719 720
{
	int idx;

	memset(sched, 0, sizeof(*sched));
	sched->max_events	= num;
	sched->max_weight	= wmax;
721
	sched->max_gp		= gpmax;
722
	sched->constraints	= constraints;
723 724

	for (idx = 0; idx < num; idx++) {
725
		if (constraints[idx]->weight == wmin)
726 727 728 729 730 731 732 733
			break;
	}

	sched->state.event	= idx;		/* start with min weight */
	sched->state.weight	= wmin;
	sched->state.unassigned	= num;
}

734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756
static void perf_sched_save_state(struct perf_sched *sched)
{
	if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX))
		return;

	sched->saved[sched->saved_states] = sched->state;
	sched->saved_states++;
}

static bool perf_sched_restore_state(struct perf_sched *sched)
{
	if (!sched->saved_states)
		return false;

	sched->saved_states--;
	sched->state = sched->saved[sched->saved_states];

	/* continue with next counter: */
	clear_bit(sched->state.counter++, sched->state.used);

	return true;
}

757 758 759 760
/*
 * Select a counter for the current event to schedule. Return true on
 * success.
 */
761
static bool __perf_sched_find_counter(struct perf_sched *sched)
762 763 764 765 766 767 768 769 770 771
{
	struct event_constraint *c;
	int idx;

	if (!sched->state.unassigned)
		return false;

	if (sched->state.event >= sched->max_events)
		return false;

772
	c = sched->constraints[sched->state.event];
773
	/* Prefer fixed purpose counters */
774 775
	if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) {
		idx = INTEL_PMC_IDX_FIXED;
776
		for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) {
777 778 779 780
			if (!__test_and_set_bit(idx, sched->state.used))
				goto done;
		}
	}
781

782 783
	/* Grab the first unused counter starting with idx */
	idx = sched->state.counter;
784
	for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) {
785 786 787 788
		if (!__test_and_set_bit(idx, sched->state.used)) {
			if (sched->state.nr_gp++ >= sched->max_gp)
				return false;

789
			goto done;
790
		}
791 792
	}

793 794 795 796
	return false;

done:
	sched->state.counter = idx;
797

798 799 800 801 802 803 804 805 806 807 808 809 810
	if (c->overlap)
		perf_sched_save_state(sched);

	return true;
}

static bool perf_sched_find_counter(struct perf_sched *sched)
{
	while (!__perf_sched_find_counter(sched)) {
		if (!perf_sched_restore_state(sched))
			return false;
	}

811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834
	return true;
}

/*
 * Go through all unassigned events and find the next one to schedule.
 * Take events with the least weight first. Return true on success.
 */
static bool perf_sched_next_event(struct perf_sched *sched)
{
	struct event_constraint *c;

	if (!sched->state.unassigned || !--sched->state.unassigned)
		return false;

	do {
		/* next event */
		sched->state.event++;
		if (sched->state.event >= sched->max_events) {
			/* next weight */
			sched->state.event = 0;
			sched->state.weight++;
			if (sched->state.weight > sched->max_weight)
				return false;
		}
835
		c = sched->constraints[sched->state.event];
836 837 838 839 840 841 842 843 844 845
	} while (c->weight != sched->state.weight);

	sched->state.counter = 0;	/* start with first counter */

	return true;
}

/*
 * Assign a counter for each event.
 */
846
int perf_assign_events(struct event_constraint **constraints, int n,
847
			int wmin, int wmax, int gpmax, int *assign)
848 849 850
{
	struct perf_sched sched;

851
	perf_sched_init(&sched, constraints, n, wmin, wmax, gpmax);
852 853 854 855 856 857 858 859 860 861

	do {
		if (!perf_sched_find_counter(&sched))
			break;	/* failed */
		if (assign)
			assign[sched.state.event] = sched.state.counter;
	} while (perf_sched_next_event(&sched));

	return sched.state.unassigned;
}
862
EXPORT_SYMBOL_GPL(perf_assign_events);
863

864
int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
865
{
866
	struct event_constraint *c;
867
	unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
868
	struct perf_event *e;
869
	int i, wmin, wmax, unsched = 0;
870 871 872 873
	struct hw_perf_event *hwc;

	bitmap_zero(used_mask, X86_PMC_IDX_MAX);

874 875 876
	if (x86_pmu.start_scheduling)
		x86_pmu.start_scheduling(cpuc);

877
	for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) {
878
		cpuc->event_constraint[i] = NULL;
879
		c = x86_pmu.get_event_constraints(cpuc, i, cpuc->event_list[i]);
880
		cpuc->event_constraint[i] = c;
881

882 883
		wmin = min(wmin, c->weight);
		wmax = max(wmax, c->weight);
884 885
	}

886 887 888
	/*
	 * fastpath, try to reuse previous register
	 */
889
	for (i = 0; i < n; i++) {
890
		hwc = &cpuc->event_list[i]->hw;
891
		c = cpuc->event_constraint[i];
892 893 894 895 896 897

		/* never assigned */
		if (hwc->idx == -1)
			break;

		/* constraint still honored */
898
		if (!test_bit(hwc->idx, c->idxmsk))
899 900 901 902 903 904
			break;

		/* not already used */
		if (test_bit(hwc->idx, used_mask))
			break;

905
		__set_bit(hwc->idx, used_mask);
906 907 908 909
		if (assign)
			assign[i] = hwc->idx;
	}

910
	/* slow path */
911
	if (i != n) {
912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927
		int gpmax = x86_pmu.num_counters;

		/*
		 * Do not allow scheduling of more than half the available
		 * generic counters.
		 *
		 * This helps avoid counter starvation of sibling thread by
		 * ensuring at most half the counters cannot be in exclusive
		 * mode. There is no designated counters for the limits. Any
		 * N/2 counters can be used. This helps with events with
		 * specific counter constraints.
		 */
		if (is_ht_workaround_enabled() && !cpuc->is_fake &&
		    READ_ONCE(cpuc->excl_cntrs->exclusive_present))
			gpmax /= 2;

928
		unsched = perf_assign_events(cpuc->event_constraint, n, wmin,
929
					     wmax, gpmax, assign);
930
	}
931

932
	/*
933 934 935 936 937 938 939 940
	 * In case of success (unsched = 0), mark events as committed,
	 * so we do not put_constraint() in case new events are added
	 * and fail to be scheduled
	 *
	 * We invoke the lower level commit callback to lock the resource
	 *
	 * We do not need to do all of this in case we are called to
	 * validate an event group (assign == NULL)
941
	 */
942
	if (!unsched && assign) {
943 944 945
		for (i = 0; i < n; i++) {
			e = cpuc->event_list[i];
			e->hw.flags |= PERF_X86_EVENT_COMMITTED;
946
			if (x86_pmu.commit_scheduling)
947
				x86_pmu.commit_scheduling(cpuc, i, assign[i]);
948
		}
949
	} else {
950
		for (i = 0; i < n; i++) {
951 952 953 954 955 956 957 958
			e = cpuc->event_list[i];
			/*
			 * do not put_constraint() on comitted events,
			 * because they are good to go
			 */
			if ((e->hw.flags & PERF_X86_EVENT_COMMITTED))
				continue;

959 960 961
			/*
			 * release events that failed scheduling
			 */
962
			if (x86_pmu.put_event_constraints)
963
				x86_pmu.put_event_constraints(cpuc, e);
964 965
		}
	}
966 967 968 969

	if (x86_pmu.stop_scheduling)
		x86_pmu.stop_scheduling(cpuc);

970
	return unsched ? -EINVAL : 0;
971 972 973 974 975 976 977 978 979 980 981
}

/*
 * dogrp: true if must collect siblings events (group)
 * returns total number of events and error code
 */
static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
{
	struct perf_event *event;
	int n, max_count;

982
	max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;