uncore.c 34.2 KB
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#include <linux/module.h>

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#include <asm/cpu_device_id.h>
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#include "uncore.h"
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static struct intel_uncore_type *empty_uncore[] = { NULL, };
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struct intel_uncore_type **uncore_msr_uncores = empty_uncore;
struct intel_uncore_type **uncore_pci_uncores = empty_uncore;
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static bool pcidrv_registered;
struct pci_driver *uncore_pci_driver;
/* pci bus to socket mapping */
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DEFINE_RAW_SPINLOCK(pci2phy_map_lock);
struct list_head pci2phy_map_head = LIST_HEAD_INIT(pci2phy_map_head);
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struct pci_extra_dev *uncore_extra_pci_dev;
static int max_packages;
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/* mask of cpus that collect uncore events */
static cpumask_t uncore_cpu_mask;

/* constraint for the fixed counter */
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static struct event_constraint uncore_constraint_fixed =
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	EVENT_CONSTRAINT(~0ULL, 1 << UNCORE_PMC_IDX_FIXED, ~0ULL);
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struct event_constraint uncore_constraint_empty =
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	EVENT_CONSTRAINT(0, 0, 0);
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MODULE_LICENSE("GPL");

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static int uncore_pcibus_to_physid(struct pci_bus *bus)
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{
	struct pci2phy_map *map;
	int phys_id = -1;

	raw_spin_lock(&pci2phy_map_lock);
	list_for_each_entry(map, &pci2phy_map_head, list) {
		if (map->segment == pci_domain_nr(bus)) {
			phys_id = map->pbus_to_physid[bus->number];
			break;
		}
	}
	raw_spin_unlock(&pci2phy_map_lock);

	return phys_id;
}

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static void uncore_free_pcibus_map(void)
{
	struct pci2phy_map *map, *tmp;

	list_for_each_entry_safe(map, tmp, &pci2phy_map_head, list) {
		list_del(&map->list);
		kfree(map);
	}
}

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struct pci2phy_map *__find_pci2phy_map(int segment)
{
	struct pci2phy_map *map, *alloc = NULL;
	int i;

	lockdep_assert_held(&pci2phy_map_lock);

lookup:
	list_for_each_entry(map, &pci2phy_map_head, list) {
		if (map->segment == segment)
			goto end;
	}

	if (!alloc) {
		raw_spin_unlock(&pci2phy_map_lock);
		alloc = kmalloc(sizeof(struct pci2phy_map), GFP_KERNEL);
		raw_spin_lock(&pci2phy_map_lock);

		if (!alloc)
			return NULL;

		goto lookup;
	}

	map = alloc;
	alloc = NULL;
	map->segment = segment;
	for (i = 0; i < 256; i++)
		map->pbus_to_physid[i] = -1;
	list_add_tail(&map->list, &pci2phy_map_head);

end:
	kfree(alloc);
	return map;
}

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ssize_t uncore_event_show(struct kobject *kobj,
			  struct kobj_attribute *attr, char *buf)
{
	struct uncore_event_desc *event =
		container_of(attr, struct uncore_event_desc, attr);
	return sprintf(buf, "%s", event->config);
}

struct intel_uncore_box *uncore_pmu_to_box(struct intel_uncore_pmu *pmu, int cpu)
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{
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	return pmu->boxes[topology_logical_package_id(cpu)];
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}

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u64 uncore_msr_read_counter(struct intel_uncore_box *box, struct perf_event *event)
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{
	u64 count;

	rdmsrl(event->hw.event_base, count);

	return count;
}

/*
 * generic get constraint function for shared match/mask registers.
 */
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struct event_constraint *
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uncore_get_constraint(struct intel_uncore_box *box, struct perf_event *event)
{
	struct intel_uncore_extra_reg *er;
	struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
	struct hw_perf_event_extra *reg2 = &event->hw.branch_reg;
	unsigned long flags;
	bool ok = false;

	/*
	 * reg->alloc can be set due to existing state, so for fake box we
	 * need to ignore this, otherwise we might fail to allocate proper
	 * fake state for this extra reg constraint.
	 */
	if (reg1->idx == EXTRA_REG_NONE ||
	    (!uncore_box_is_fake(box) && reg1->alloc))
		return NULL;

	er = &box->shared_regs[reg1->idx];
	raw_spin_lock_irqsave(&er->lock, flags);
	if (!atomic_read(&er->ref) ||
	    (er->config1 == reg1->config && er->config2 == reg2->config)) {
		atomic_inc(&er->ref);
		er->config1 = reg1->config;
		er->config2 = reg2->config;
		ok = true;
	}
	raw_spin_unlock_irqrestore(&er->lock, flags);

	if (ok) {
		if (!uncore_box_is_fake(box))
			reg1->alloc = 1;
		return NULL;
	}

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	return &uncore_constraint_empty;
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}

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void uncore_put_constraint(struct intel_uncore_box *box, struct perf_event *event)
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{
	struct intel_uncore_extra_reg *er;
	struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;

	/*
	 * Only put constraint if extra reg was actually allocated. Also
	 * takes care of event which do not use an extra shared reg.
	 *
	 * Also, if this is a fake box we shouldn't touch any event state
	 * (reg->alloc) and we don't care about leaving inconsistent box
	 * state either since it will be thrown out.
	 */
	if (uncore_box_is_fake(box) || !reg1->alloc)
		return;

	er = &box->shared_regs[reg1->idx];
	atomic_dec(&er->ref);
	reg1->alloc = 0;
}

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u64 uncore_shared_reg_config(struct intel_uncore_box *box, int idx)
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{
	struct intel_uncore_extra_reg *er;
	unsigned long flags;
	u64 config;

	er = &box->shared_regs[idx];

	raw_spin_lock_irqsave(&er->lock, flags);
	config = er->config;
	raw_spin_unlock_irqrestore(&er->lock, flags);

	return config;
}

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static void uncore_assign_hw_event(struct intel_uncore_box *box,
				   struct perf_event *event, int idx)
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{
	struct hw_perf_event *hwc = &event->hw;

	hwc->idx = idx;
	hwc->last_tag = ++box->tags[idx];

	if (hwc->idx == UNCORE_PMC_IDX_FIXED) {
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		hwc->event_base = uncore_fixed_ctr(box);
		hwc->config_base = uncore_fixed_ctl(box);
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		return;
	}

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	hwc->config_base = uncore_event_ctl(box, hwc->idx);
	hwc->event_base  = uncore_perf_ctr(box, hwc->idx);
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}

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void uncore_perf_event_update(struct intel_uncore_box *box, struct perf_event *event)
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{
	u64 prev_count, new_count, delta;
	int shift;

	if (event->hw.idx >= UNCORE_PMC_IDX_FIXED)
		shift = 64 - uncore_fixed_ctr_bits(box);
	else
		shift = 64 - uncore_perf_ctr_bits(box);

	/* the hrtimer might modify the previous event value */
again:
	prev_count = local64_read(&event->hw.prev_count);
	new_count = uncore_read_counter(box, event);
	if (local64_xchg(&event->hw.prev_count, new_count) != prev_count)
		goto again;

	delta = (new_count << shift) - (prev_count << shift);
	delta >>= shift;

	local64_add(delta, &event->count);
}

/*
 * The overflow interrupt is unavailable for SandyBridge-EP, is broken
 * for SandyBridge. So we use hrtimer to periodically poll the counter
 * to avoid overflow.
 */
static enum hrtimer_restart uncore_pmu_hrtimer(struct hrtimer *hrtimer)
{
	struct intel_uncore_box *box;
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	struct perf_event *event;
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	unsigned long flags;
	int bit;

	box = container_of(hrtimer, struct intel_uncore_box, hrtimer);
	if (!box->n_active || box->cpu != smp_processor_id())
		return HRTIMER_NORESTART;
	/*
	 * disable local interrupt to prevent uncore_pmu_event_start/stop
	 * to interrupt the update process
	 */
	local_irq_save(flags);

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	/*
	 * handle boxes with an active event list as opposed to active
	 * counters
	 */
	list_for_each_entry(event, &box->active_list, active_entry) {
		uncore_perf_event_update(box, event);
	}

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	for_each_set_bit(bit, box->active_mask, UNCORE_PMC_IDX_MAX)
		uncore_perf_event_update(box, box->events[bit]);

	local_irq_restore(flags);

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	hrtimer_forward_now(hrtimer, ns_to_ktime(box->hrtimer_duration));
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	return HRTIMER_RESTART;
}

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void uncore_pmu_start_hrtimer(struct intel_uncore_box *box)
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{
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	hrtimer_start(&box->hrtimer, ns_to_ktime(box->hrtimer_duration),
		      HRTIMER_MODE_REL_PINNED);
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}

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void uncore_pmu_cancel_hrtimer(struct intel_uncore_box *box)
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{
	hrtimer_cancel(&box->hrtimer);
}

static void uncore_pmu_init_hrtimer(struct intel_uncore_box *box)
{
	hrtimer_init(&box->hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
	box->hrtimer.function = uncore_pmu_hrtimer;
}

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static struct intel_uncore_box *uncore_alloc_box(struct intel_uncore_type *type,
						 int node)
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{
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	int i, size, numshared = type->num_shared_regs ;
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	struct intel_uncore_box *box;

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	size = sizeof(*box) + numshared * sizeof(struct intel_uncore_extra_reg);
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	box = kzalloc_node(size, GFP_KERNEL, node);
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	if (!box)
		return NULL;

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	for (i = 0; i < numshared; i++)
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		raw_spin_lock_init(&box->shared_regs[i].lock);

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	uncore_pmu_init_hrtimer(box);
	box->cpu = -1;
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	box->pci_phys_id = -1;
	box->pkgid = -1;
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	/* set default hrtimer timeout */
	box->hrtimer_duration = UNCORE_PMU_HRTIMER_INTERVAL;
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	INIT_LIST_HEAD(&box->active_list);
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	return box;
}

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/*
 * Using uncore_pmu_event_init pmu event_init callback
 * as a detection point for uncore events.
 */
static int uncore_pmu_event_init(struct perf_event *event);

static bool is_uncore_event(struct perf_event *event)
{
	return event->pmu->event_init == uncore_pmu_event_init;
}

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static int
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uncore_collect_events(struct intel_uncore_box *box, struct perf_event *leader,
		      bool dogrp)
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{
	struct perf_event *event;
	int n, max_count;

	max_count = box->pmu->type->num_counters;
	if (box->pmu->type->fixed_ctl)
		max_count++;

	if (box->n_events >= max_count)
		return -EINVAL;

	n = box->n_events;
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	if (is_uncore_event(leader)) {
		box->event_list[n] = leader;
		n++;
	}

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	if (!dogrp)
		return n;

	list_for_each_entry(event, &leader->sibling_list, group_entry) {
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		if (!is_uncore_event(event) ||
		    event->state <= PERF_EVENT_STATE_OFF)
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			continue;

		if (n >= max_count)
			return -EINVAL;

		box->event_list[n] = event;
		n++;
	}
	return n;
}

static struct event_constraint *
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uncore_get_event_constraint(struct intel_uncore_box *box, struct perf_event *event)
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{
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	struct intel_uncore_type *type = box->pmu->type;
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	struct event_constraint *c;

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	if (type->ops->get_constraint) {
		c = type->ops->get_constraint(box, event);
		if (c)
			return c;
	}

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	if (event->attr.config == UNCORE_FIXED_EVENT)
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		return &uncore_constraint_fixed;
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	if (type->constraints) {
		for_each_event_constraint(c, type->constraints) {
			if ((event->hw.config & c->cmask) == c->code)
				return c;
		}
	}

	return &type->unconstrainted;
}

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static void uncore_put_event_constraint(struct intel_uncore_box *box,
					struct perf_event *event)
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{
	if (box->pmu->type->ops->put_constraint)
		box->pmu->type->ops->put_constraint(box, event);
}

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static int uncore_assign_events(struct intel_uncore_box *box, int assign[], int n)
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{
	unsigned long used_mask[BITS_TO_LONGS(UNCORE_PMC_IDX_MAX)];
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	struct event_constraint *c;
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	int i, wmin, wmax, ret = 0;
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	struct hw_perf_event *hwc;

	bitmap_zero(used_mask, UNCORE_PMC_IDX_MAX);

	for (i = 0, wmin = UNCORE_PMC_IDX_MAX, wmax = 0; i < n; i++) {
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		c = uncore_get_event_constraint(box, box->event_list[i]);
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		box->event_constraint[i] = c;
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		wmin = min(wmin, c->weight);
		wmax = max(wmax, c->weight);
	}

	/* fastpath, try to reuse previous register */
	for (i = 0; i < n; i++) {
		hwc = &box->event_list[i]->hw;
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		c = box->event_constraint[i];
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		/* never assigned */
		if (hwc->idx == -1)
			break;

		/* constraint still honored */
		if (!test_bit(hwc->idx, c->idxmsk))
			break;

		/* not already used */
		if (test_bit(hwc->idx, used_mask))
			break;

		__set_bit(hwc->idx, used_mask);
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		if (assign)
			assign[i] = hwc->idx;
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	}
	/* slow path */
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	if (i != n)
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		ret = perf_assign_events(box->event_constraint, n,
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					 wmin, wmax, n, assign);
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	if (!assign || ret) {
		for (i = 0; i < n; i++)
			uncore_put_event_constraint(box, box->event_list[i]);
	}
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	return ret ? -EINVAL : 0;
}

static void uncore_pmu_event_start(struct perf_event *event, int flags)
{
	struct intel_uncore_box *box = uncore_event_to_box(event);
	int idx = event->hw.idx;

	if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
		return;

	if (WARN_ON_ONCE(idx == -1 || idx >= UNCORE_PMC_IDX_MAX))
		return;

	event->hw.state = 0;
	box->events[idx] = event;
	box->n_active++;
	__set_bit(idx, box->active_mask);

	local64_set(&event->hw.prev_count, uncore_read_counter(box, event));
	uncore_enable_event(box, event);

	if (box->n_active == 1) {
		uncore_enable_box(box);
		uncore_pmu_start_hrtimer(box);
	}
}

static void uncore_pmu_event_stop(struct perf_event *event, int flags)
{
	struct intel_uncore_box *box = uncore_event_to_box(event);
	struct hw_perf_event *hwc = &event->hw;

	if (__test_and_clear_bit(hwc->idx, box->active_mask)) {
		uncore_disable_event(box, event);
		box->n_active--;
		box->events[hwc->idx] = NULL;
		WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
		hwc->state |= PERF_HES_STOPPED;

		if (box->n_active == 0) {
			uncore_disable_box(box);
			uncore_pmu_cancel_hrtimer(box);
		}
	}

	if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
		/*
		 * Drain the remaining delta count out of a event
		 * that we are disabling:
		 */
		uncore_perf_event_update(box, event);
		hwc->state |= PERF_HES_UPTODATE;
	}
}

static int uncore_pmu_event_add(struct perf_event *event, int flags)
{
	struct intel_uncore_box *box = uncore_event_to_box(event);
	struct hw_perf_event *hwc = &event->hw;
	int assign[UNCORE_PMC_IDX_MAX];
	int i, n, ret;

	if (!box)
		return -ENODEV;

	ret = n = uncore_collect_events(box, event, false);
	if (ret < 0)
		return ret;

	hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
	if (!(flags & PERF_EF_START))
		hwc->state |= PERF_HES_ARCH;

	ret = uncore_assign_events(box, assign, n);
	if (ret)
		return ret;

	/* save events moving to new counters */
	for (i = 0; i < box->n_events; i++) {
		event = box->event_list[i];
		hwc = &event->hw;

		if (hwc->idx == assign[i] &&
			hwc->last_tag == box->tags[assign[i]])
			continue;
		/*
		 * Ensure we don't accidentally enable a stopped
		 * counter simply because we rescheduled.
		 */
		if (hwc->state & PERF_HES_STOPPED)
			hwc->state |= PERF_HES_ARCH;

		uncore_pmu_event_stop(event, PERF_EF_UPDATE);
	}

	/* reprogram moved events into new counters */
	for (i = 0; i < n; i++) {
		event = box->event_list[i];
		hwc = &event->hw;

		if (hwc->idx != assign[i] ||
			hwc->last_tag != box->tags[assign[i]])
			uncore_assign_hw_event(box, event, assign[i]);
		else if (i < box->n_events)
			continue;

		if (hwc->state & PERF_HES_ARCH)
			continue;

		uncore_pmu_event_start(event, 0);
	}
	box->n_events = n;

	return 0;
}

static void uncore_pmu_event_del(struct perf_event *event, int flags)
{
	struct intel_uncore_box *box = uncore_event_to_box(event);
	int i;

	uncore_pmu_event_stop(event, PERF_EF_UPDATE);

	for (i = 0; i < box->n_events; i++) {
		if (event == box->event_list[i]) {
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			uncore_put_event_constraint(box, event);

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			for (++i; i < box->n_events; i++)
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				box->event_list[i - 1] = box->event_list[i];

			--box->n_events;
			break;
		}
	}

	event->hw.idx = -1;
	event->hw.last_tag = ~0ULL;
}

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void uncore_pmu_event_read(struct perf_event *event)
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{
	struct intel_uncore_box *box = uncore_event_to_box(event);
	uncore_perf_event_update(box, event);
}

/*
 * validation ensures the group can be loaded onto the
 * PMU if it was the only group available.
 */
static int uncore_validate_group(struct intel_uncore_pmu *pmu,
				struct perf_event *event)
{
	struct perf_event *leader = event->group_leader;
	struct intel_uncore_box *fake_box;
	int ret = -EINVAL, n;

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	fake_box = uncore_alloc_box(pmu->type, NUMA_NO_NODE);
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	if (!fake_box)
		return -ENOMEM;

	fake_box->pmu = pmu;
	/*
	 * the event is not yet connected with its
	 * siblings therefore we must first collect
	 * existing siblings, then add the new event
	 * before we can simulate the scheduling
	 */
	n = uncore_collect_events(fake_box, leader, true);
	if (n < 0)
		goto out;

	fake_box->n_events = n;
	n = uncore_collect_events(fake_box, event, false);
	if (n < 0)
		goto out;

	fake_box->n_events = n;

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	ret = uncore_assign_events(fake_box, NULL, n);
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out:
	kfree(fake_box);
	return ret;
}

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static int uncore_pmu_event_init(struct perf_event *event)
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{
	struct intel_uncore_pmu *pmu;
	struct intel_uncore_box *box;
	struct hw_perf_event *hwc = &event->hw;
	int ret;

	if (event->attr.type != event->pmu->type)
		return -ENOENT;

	pmu = uncore_event_to_pmu(event);
	/* no device found for this pmu */
	if (pmu->func_id < 0)
		return -ENOENT;

	/*
	 * Uncore PMU does measure at all privilege level all the time.
	 * So it doesn't make sense to specify any exclude bits.
	 */
	if (event->attr.exclude_user || event->attr.exclude_kernel ||
			event->attr.exclude_hv || event->attr.exclude_idle)
		return -EINVAL;

	/* Sampling not supported yet */
	if (hwc->sample_period)
		return -EINVAL;

	/*
	 * Place all uncore events for a particular physical package
	 * onto a single cpu
	 */
	if (event->cpu < 0)
		return -EINVAL;
	box = uncore_pmu_to_box(pmu, event->cpu);
	if (!box || box->cpu < 0)
		return -EINVAL;
	event->cpu = box->cpu;
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	event->pmu_private = box;
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	event->hw.idx = -1;
	event->hw.last_tag = ~0ULL;
	event->hw.extra_reg.idx = EXTRA_REG_NONE;
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	event->hw.branch_reg.idx = EXTRA_REG_NONE;
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	if (event->attr.config == UNCORE_FIXED_EVENT) {
		/* no fixed counter */
		if (!pmu->type->fixed_ctl)
			return -EINVAL;
		/*
		 * if there is only one fixed counter, only the first pmu
		 * can access the fixed counter
		 */
		if (pmu->type->single_fixed && pmu->pmu_idx > 0)
			return -EINVAL;
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		/* fixed counters have event field hardcoded to zero */
		hwc->config = 0ULL;
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	} else {
		hwc->config = event->attr.config & pmu->type->event_mask;
686 687 688 689 690
		if (pmu->type->ops->hw_config) {
			ret = pmu->type->ops->hw_config(box, event);
			if (ret)
				return ret;
		}
691 692 693 694 695 696 697 698 699 700
	}

	if (event->group_leader != event)
		ret = uncore_validate_group(pmu, event);
	else
		ret = 0;

	return ret;
}

701 702 703
static ssize_t uncore_get_attr_cpumask(struct device *dev,
				struct device_attribute *attr, char *buf)
{
704
	return cpumap_print_to_pagebuf(true, buf, &uncore_cpu_mask);
705 706 707 708 709 710 711 712 713 714 715 716 717
}

static DEVICE_ATTR(cpumask, S_IRUGO, uncore_get_attr_cpumask, NULL);

static struct attribute *uncore_pmu_attrs[] = {
	&dev_attr_cpumask.attr,
	NULL,
};

static struct attribute_group uncore_pmu_attr_group = {
	.attrs = uncore_pmu_attrs,
};

718
static int uncore_pmu_register(struct intel_uncore_pmu *pmu)
719 720 721
{
	int ret;

722 723 724 725 726 727 728 729 730 731 732 733 734 735 736
	if (!pmu->type->pmu) {
		pmu->pmu = (struct pmu) {
			.attr_groups	= pmu->type->attr_groups,
			.task_ctx_nr	= perf_invalid_context,
			.event_init	= uncore_pmu_event_init,
			.add		= uncore_pmu_event_add,
			.del		= uncore_pmu_event_del,
			.start		= uncore_pmu_event_start,
			.stop		= uncore_pmu_event_stop,
			.read		= uncore_pmu_event_read,
		};
	} else {
		pmu->pmu = *pmu->type->pmu;
		pmu->pmu.attr_groups = pmu->type->attr_groups;
	}
737 738 739 740 741 742 743 744 745 746 747 748

	if (pmu->type->num_boxes == 1) {
		if (strlen(pmu->type->name) > 0)
			sprintf(pmu->name, "uncore_%s", pmu->type->name);
		else
			sprintf(pmu->name, "uncore");
	} else {
		sprintf(pmu->name, "uncore_%s_%d", pmu->type->name,
			pmu->pmu_idx);
	}

	ret = perf_pmu_register(&pmu->pmu, pmu->name, -1);
749 750
	if (!ret)
		pmu->registered = true;
751 752 753
	return ret;
}

754 755 756 757 758 759 760 761
static void uncore_pmu_unregister(struct intel_uncore_pmu *pmu)
{
	if (!pmu->registered)
		return;
	perf_pmu_unregister(&pmu->pmu);
	pmu->registered = false;
}

762
static void __uncore_exit_boxes(struct intel_uncore_type *type, int cpu)
763 764 765 766 767 768 769 770 771 772 773 774 775 776 777
{
	struct intel_uncore_pmu *pmu = type->pmus;
	struct intel_uncore_box *box;
	int i, pkg;

	if (pmu) {
		pkg = topology_physical_package_id(cpu);
		for (i = 0; i < type->num_boxes; i++, pmu++) {
			box = pmu->boxes[pkg];
			if (box)
				uncore_box_exit(box);
		}
	}
}

778
static void uncore_exit_boxes(void *dummy)
779 780 781 782 783 784 785
{
	struct intel_uncore_type **types;

	for (types = uncore_msr_uncores; *types; types++)
		__uncore_exit_boxes(*types++, smp_processor_id());
}

786 787 788 789 790 791 792 793 794
static void uncore_free_boxes(struct intel_uncore_pmu *pmu)
{
	int pkg;

	for (pkg = 0; pkg < max_packages; pkg++)
		kfree(pmu->boxes[pkg]);
	kfree(pmu->boxes);
}

795
static void uncore_type_exit(struct intel_uncore_type *type)
796
{
797
	struct intel_uncore_pmu *pmu = type->pmus;
798 799
	int i;

800 801 802 803
	if (pmu) {
		for (i = 0; i < type->num_boxes; i++, pmu++) {
			uncore_pmu_unregister(pmu);
			uncore_free_boxes(pmu);
804
		}
805 806 807
		kfree(type->pmus);
		type->pmus = NULL;
	}
808 809
	kfree(type->events_group);
	type->events_group = NULL;
810 811
}

812
static void uncore_types_exit(struct intel_uncore_type **types)
813
{
814 815
	for (; *types; types++)
		uncore_type_exit(*types);
816 817
}

818
static int __init uncore_type_init(struct intel_uncore_type *type, bool setid)
819 820
{
	struct intel_uncore_pmu *pmus;
821
	struct attribute_group *attr_group;
822
	struct attribute **attrs;
823
	size_t size;
824 825 826 827 828 829
	int i, j;

	pmus = kzalloc(sizeof(*pmus) * type->num_boxes, GFP_KERNEL);
	if (!pmus)
		return -ENOMEM;

830
	size = max_packages * sizeof(struct intel_uncore_box *);
831 832

	for (i = 0; i < type->num_boxes; i++) {
833 834 835 836 837
		pmus[i].func_id	= setid ? i : -1;
		pmus[i].pmu_idx	= i;
		pmus[i].type	= type;
		pmus[i].boxes	= kzalloc(size, GFP_KERNEL);
		if (!pmus[i].boxes)
838
			return -ENOMEM;
839 840
	}

841 842 843 844 845
	type->pmus = pmus;
	type->unconstrainted = (struct event_constraint)
		__EVENT_CONSTRAINT(0, (1ULL << type->num_counters) - 1,
				0, type->num_counters, 0, 0);

846
	if (type->event_descs) {
847
		for (i = 0; type->event_descs[i].attr.attr.name; i++);
848

849 850 851
		attr_group = kzalloc(sizeof(struct attribute *) * (i + 1) +
					sizeof(*attr_group), GFP_KERNEL);
		if (!attr_group)
852
			return -ENOMEM;
853

854 855 856
		attrs = (struct attribute **)(attr_group + 1);
		attr_group->name = "events";
		attr_group->attrs = attrs;
857 858 859 860

		for (j = 0; j < i; j++)
			attrs[j] = &type->event_descs[j].attr.attr;

861
		type->events_group = attr_group;
862 863
	}

864
	type->pmu_group = &uncore_pmu_attr_group;
865 866 867
	return 0;
}

868 869
static int __init
uncore_types_init(struct intel_uncore_type **types, bool setid)
870
{
871
	int ret;
872

873 874
	for (; *types; types++) {
		ret = uncore_type_init(*types, setid);
875
		if (ret)
876
			return ret;
877 878 879 880
	}
	return 0;
}

881 882 883
/*
 * add a pci uncore device
 */
884
static int uncore_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
885
{
886
	struct intel_uncore_type *type;
887 888
	struct intel_uncore_pmu *pmu;
	struct intel_uncore_box *box;
889
	int phys_id, pkg, ret;
890

891
	phys_id = uncore_pcibus_to_physid(pdev->bus);
892
	if (phys_id < 0)
893 894
		return -ENODEV;

895
	pkg = topology_phys_to_logical_pkg(phys_id);
896
	if (pkg < 0)
897 898
		return -EINVAL;

899
	if (UNCORE_PCI_DEV_TYPE(id->driver_data) == UNCORE_EXTRA_PCI_DEV) {
900
		int idx = UNCORE_PCI_DEV_IDX(id->driver_data);
901 902

		uncore_extra_pci_dev[pkg].dev[idx] = pdev;
903 904 905 906
		pci_set_drvdata(pdev, NULL);
		return 0;
	}

907
	type = uncore_pci_uncores[UNCORE_PCI_DEV_TYPE(id->driver_data)];
908 909 910 911
	/*
	 * for performance monitoring unit with multiple boxes,
	 * each box has a different function id.
	 */
912
	pmu = &type->pmus[UNCORE_PCI_DEV_IDX(id->driver_data)];
913 914 915 916 917 918
	/* Knights Landing uses a common PCI device ID for multiple instances of
	 * an uncore PMU device type. There is only one entry per device type in
	 * the knl_uncore_pci_ids table inspite of multiple devices present for
	 * some device types. Hence PCI device idx would be 0 for all devices.
	 * So increment pmu pointer to point to an unused array element.
	 */
919
	if (boot_cpu_data.x86_model == 87) {
920 921
		while (pmu->func_id >= 0)
			pmu++;
922 923
	}

924 925 926 927 928 929 930
	if (WARN_ON_ONCE(pmu->boxes[pkg] != NULL))
		return -EINVAL;

	box = uncore_alloc_box(type, NUMA_NO_NODE);
	if (!box)
		return -ENOMEM;

931 932 933 934
	if (pmu->func_id < 0)
		pmu->func_id = pdev->devfn;
	else
		WARN_ON_ONCE(pmu->func_id != pdev->devfn);
935

936 937 938
	atomic_inc(&box->refcnt);
	box->pci_phys_id = phys_id;
	box->pkgid = pkg;
939 940
	box->pci_dev = pdev;
	box->pmu = pmu;
941
	uncore_box_init(box);
942 943
	pci_set_drvdata(pdev, box);

944 945
	pmu->boxes[pkg] = box;
	if (atomic_inc_return(&pmu->activeboxes) > 1)
946 947
		return 0;

948
	/* First active box registers the pmu */
949 950 951
	ret = uncore_pmu_register(pmu);
	if (ret) {
		pci_set_drvdata(pdev, NULL);
952
		pmu->boxes[pkg] = NULL;
953
		uncore_box_exit(box);
954 955 956
		kfree(box);
	}
	return ret;
957 958
}

959
static void uncore_pci_remove(struct pci_dev *pdev)
960 961
{
	struct intel_uncore_box *box = pci_get_drvdata(pdev);
962
	struct intel_uncore_pmu *pmu;
963
	int i, phys_id, pkg;
964

965
	phys_id = uncore_pcibus_to_physid(pdev->bus);
966 967
	pkg = topology_phys_to_logical_pkg(phys_id);

968 969 970
	box = pci_get_drvdata(pdev);
	if (!box) {
		for (i = 0; i < UNCORE_EXTRA_PCI_DEV_MAX; i++) {
971 972
			if (uncore_extra_pci_dev[pkg].dev[i] == pdev) {
				uncore_extra_pci_dev[pkg].dev[i] = NULL;
973 974 975 976 977 978
				break;
			}
		}
		WARN_ON_ONCE(i >= UNCORE_EXTRA_PCI_DEV_MAX);
		return;
	}
979

980
	pmu = box->pmu;
981
	if (WARN_ON_ONCE(phys_id != box->pci_phys_id))
982 983
		return;

984
	pci_set_drvdata(pdev, NULL);
985 986 987
	pmu->boxes[pkg] = NULL;
	if (atomic_dec_return(&pmu->activeboxes) == 0)
		uncore_pmu_unregister(pmu);
988
	uncore_box_exit(box);
989 990 991 992 993
	kfree(box);
}

static int __init uncore_pci_init(void)
{
994
	size_t size;
995 996
	int ret;

997 998 999 1000
	size = max_packages * sizeof(struct pci_extra_dev);
	uncore_extra_pci_dev = kzalloc(size, GFP_KERNEL);
	if (!uncore_extra_pci_dev) {
		ret = -ENOMEM;
1001
		goto err;
1002 1003 1004 1005 1006
	}

	ret = uncore_types_init(uncore_pci_uncores, false);
	if (ret)
		goto errtype;
1007 1008 1009 1010 1011

	uncore_pci_driver->probe = uncore_pci_probe;
	uncore_pci_driver->remove = uncore_pci_remove;

	ret = pci_register_driver(uncore_pci_driver);
1012
	if (ret)
1013
		goto errtype;
1014 1015 1016

	pcidrv_registered = true;
	return 0;
1017

1018
errtype:
1019
	uncore_types_exit(uncore_pci_uncores);
1020 1021
	kfree(uncore_extra_pci_dev);
	uncore_extra_pci_dev = NULL;
1022
	uncore_free_pcibus_map();
1023 1024
err:
	uncore_pci_uncores = empty_uncore;
1025 1026 1027
	return ret;
}

1028
static void uncore_pci_exit(void)
1029 1030 1031 1032
{
	if (pcidrv_registered) {
		pcidrv_registered = false;
		pci_unregister_driver(uncore_pci_driver);
1033
		uncore_types_exit(uncore_pci_uncores);
1034
		kfree(uncore_extra_pci_dev);
1035
		uncore_free_pcibus_map();
1036 1037 1038
	}
}

1039
static void uncore_cpu_dying(int cpu)
1040
{
1041
	struct intel_uncore_type *type, **types = uncore_msr_uncores;
1042 1043
	struct intel_uncore_pmu *pmu;
	struct intel_uncore_box *box;
1044
	int i, pkg;
1045

1046 1047 1048 1049 1050 1051 1052
	pkg = topology_logical_package_id(cpu);
	for (; *types; types++) {
		type = *types;
		pmu = type->pmus;
		for (i = 0; i < type->num_boxes; i++, pmu++) {
			box = pmu->boxes[pkg];
			if (box && atomic_dec_return(&box->refcnt) == 0)
1053
				uncore_box_exit(box);
1054 1055 1056 1057
		}
	}
}

1058
static void uncore_cpu_starting(int cpu, bool init)
1059
{
1060
	struct intel_uncore_type *type, **types = uncore_msr_uncores;
1061
	struct intel_uncore_pmu *pmu;
1062 1063
	struct intel_uncore_box *box;
	int i, pkg, ncpus = 1;
1064

1065 1066 1067 1068 1069 1070 1071
	if (init) {
		/*
		 * On init we get the number of online cpus in the package
		 * and set refcount for all of them.
		 */
		ncpus = cpumask_weight(topology_core_cpumask(cpu));
	}
1072

1073 1074 1075 1076 1077 1078 1079 1080 1081 1082
	pkg = topology_logical_package_id(cpu);
	for (; *types; types++) {
		type = *types;
		pmu = type->pmus;
		for (i = 0; i < type->num_boxes; i++, pmu++) {
			box = pmu->boxes[pkg];
			if (!box)
				continue;
			/* The first cpu on a package activates the box */
			if (atomic_add_return(ncpus, &box->refcnt) == ncpus)
1083
				uncore_box_init(box);
1084 1085 1086 1087
		}
	}
}

1088
static int uncore_cpu_prepare(int cpu)
1089
{
1090
	struct intel_uncore_type *type, **types = uncore_msr_uncores;
1091 1092
	struct intel_uncore_pmu *pmu;
	struct intel_uncore_box *box;
1093
	int i, pkg;
1094

1095 1096 1097 1098 1099 1100 1101 1102
	pkg = topology_logical_package_id(cpu);
	for (; *types; types++) {
		type = *types;
		pmu = type->pmus;
		for (i = 0; i < type->num_boxes; i++, pmu++) {
			if (pmu->boxes[pkg])
				continue;
			/* First cpu of a package allocates the box */
1103
			box = uncore_alloc_box(type, cpu_to_node(cpu));
1104 1105 1106
			if (!box)
				return -ENOMEM;
			box->pmu = pmu;
1107 1108
			box->pkgid = pkg;
			pmu->boxes[pkg] = box;
1109 1110 1111 1112 1113
		}
	}
	return 0;
}

1114 1115
static void uncore_change_type_ctx(struct intel_uncore_type *type, int old_cpu,
				   int new_cpu)
1116
{
1117
	struct intel_uncore_pmu *pmu = type->pmus;
1118
	struct intel_uncore_box *box;
1119
	int i, pkg;
1120

1121
	pkg = topology_logical_package_id(old_cpu < 0 ? new_cpu : old_cpu);
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