gtt.c 59.8 KB
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/*
 * GTT virtualization
 *
 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 *
 * Authors:
 *    Zhi Wang <zhi.a.wang@intel.com>
 *    Zhenyu Wang <zhenyuw@linux.intel.com>
 *    Xiao Zheng <xiao.zheng@intel.com>
 *
 * Contributors:
 *    Min He <min.he@intel.com>
 *    Bing Niu <bing.niu@intel.com>
 *
 */

#include "i915_drv.h"
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#include "gvt.h"
#include "i915_pvinfo.h"
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#include "trace.h"

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#if defined(VERBOSE_DEBUG)
#define gvt_vdbg_mm(fmt, args...) gvt_dbg_mm(fmt, ##args)
#else
#define gvt_vdbg_mm(fmt, args...)
#endif

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static bool enable_out_of_sync = false;
static int preallocated_oos_pages = 8192;

/*
 * validate a gm address and related range size,
 * translate it to host gm address
 */
bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size)
{
	if ((!vgpu_gmadr_is_valid(vgpu, addr)) || (size
			&& !vgpu_gmadr_is_valid(vgpu, addr + size - 1))) {
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		gvt_vgpu_err("invalid range gmadr 0x%llx size 0x%x\n",
				addr, size);
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		return false;
	}
	return true;
}

/* translate a guest gmadr to host gmadr */
int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr)
{
	if (WARN(!vgpu_gmadr_is_valid(vgpu, g_addr),
		 "invalid guest gmadr %llx\n", g_addr))
		return -EACCES;

	if (vgpu_gmadr_is_aperture(vgpu, g_addr))
		*h_addr = vgpu_aperture_gmadr_base(vgpu)
			  + (g_addr - vgpu_aperture_offset(vgpu));
	else
		*h_addr = vgpu_hidden_gmadr_base(vgpu)
			  + (g_addr - vgpu_hidden_offset(vgpu));
	return 0;
}

/* translate a host gmadr to guest gmadr */
int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr)
{
	if (WARN(!gvt_gmadr_is_valid(vgpu->gvt, h_addr),
		 "invalid host gmadr %llx\n", h_addr))
		return -EACCES;

	if (gvt_gmadr_is_aperture(vgpu->gvt, h_addr))
		*g_addr = vgpu_aperture_gmadr_base(vgpu)
			+ (h_addr - gvt_aperture_gmadr_base(vgpu->gvt));
	else
		*g_addr = vgpu_hidden_gmadr_base(vgpu)
			+ (h_addr - gvt_hidden_gmadr_base(vgpu->gvt));
	return 0;
}

int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu, unsigned long g_index,
			     unsigned long *h_index)
{
	u64 h_addr;
	int ret;

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	ret = intel_gvt_ggtt_gmadr_g2h(vgpu, g_index << I915_GTT_PAGE_SHIFT,
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				       &h_addr);
	if (ret)
		return ret;

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	*h_index = h_addr >> I915_GTT_PAGE_SHIFT;
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	return 0;
}

int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index,
			     unsigned long *g_index)
{
	u64 g_addr;
	int ret;

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	ret = intel_gvt_ggtt_gmadr_h2g(vgpu, h_index << I915_GTT_PAGE_SHIFT,
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				       &g_addr);
	if (ret)
		return ret;

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	*g_index = g_addr >> I915_GTT_PAGE_SHIFT;
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	return 0;
}

#define gtt_type_is_entry(type) \
	(type > GTT_TYPE_INVALID && type < GTT_TYPE_PPGTT_ENTRY \
	 && type != GTT_TYPE_PPGTT_PTE_ENTRY \
	 && type != GTT_TYPE_PPGTT_ROOT_ENTRY)

#define gtt_type_is_pt(type) \
	(type >= GTT_TYPE_PPGTT_PTE_PT && type < GTT_TYPE_MAX)

#define gtt_type_is_pte_pt(type) \
	(type == GTT_TYPE_PPGTT_PTE_PT)

#define gtt_type_is_root_pointer(type) \
	(gtt_type_is_entry(type) && type > GTT_TYPE_PPGTT_ROOT_ENTRY)

#define gtt_init_entry(e, t, p, v) do { \
	(e)->type = t; \
	(e)->pdev = p; \
	memcpy(&(e)->val64, &v, sizeof(v)); \
} while (0)

/*
 * Mappings between GTT_TYPE* enumerations.
 * Following information can be found according to the given type:
 * - type of next level page table
 * - type of entry inside this level page table
 * - type of entry with PSE set
 *
 * If the given type doesn't have such a kind of information,
 * e.g. give a l4 root entry type, then request to get its PSE type,
 * give a PTE page table type, then request to get its next level page
 * table type, as we know l4 root entry doesn't have a PSE bit,
 * and a PTE page table doesn't have a next level page table type,
 * GTT_TYPE_INVALID will be returned. This is useful when traversing a
 * page table.
 */

struct gtt_type_table_entry {
	int entry_type;
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	int pt_type;
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	int next_pt_type;
	int pse_entry_type;
};

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#define GTT_TYPE_TABLE_ENTRY(type, e_type, cpt_type, npt_type, pse_type) \
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	[type] = { \
		.entry_type = e_type, \
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		.pt_type = cpt_type, \
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		.next_pt_type = npt_type, \
		.pse_entry_type = pse_type, \
	}

static struct gtt_type_table_entry gtt_type_table[] = {
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_ROOT_L4_ENTRY,
			GTT_TYPE_PPGTT_ROOT_L4_ENTRY,
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			GTT_TYPE_INVALID,
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			GTT_TYPE_PPGTT_PML4_PT,
			GTT_TYPE_INVALID),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PML4_PT,
			GTT_TYPE_PPGTT_PML4_ENTRY,
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			GTT_TYPE_PPGTT_PML4_PT,
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			GTT_TYPE_PPGTT_PDP_PT,
			GTT_TYPE_INVALID),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PML4_ENTRY,
			GTT_TYPE_PPGTT_PML4_ENTRY,
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			GTT_TYPE_PPGTT_PML4_PT,
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			GTT_TYPE_PPGTT_PDP_PT,
			GTT_TYPE_INVALID),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDP_PT,
			GTT_TYPE_PPGTT_PDP_ENTRY,
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			GTT_TYPE_PPGTT_PDP_PT,
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			GTT_TYPE_PPGTT_PDE_PT,
			GTT_TYPE_PPGTT_PTE_1G_ENTRY),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_ROOT_L3_ENTRY,
			GTT_TYPE_PPGTT_ROOT_L3_ENTRY,
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			GTT_TYPE_INVALID,
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			GTT_TYPE_PPGTT_PDE_PT,
			GTT_TYPE_PPGTT_PTE_1G_ENTRY),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDP_ENTRY,
			GTT_TYPE_PPGTT_PDP_ENTRY,
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			GTT_TYPE_PPGTT_PDP_PT,
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			GTT_TYPE_PPGTT_PDE_PT,
			GTT_TYPE_PPGTT_PTE_1G_ENTRY),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDE_PT,
			GTT_TYPE_PPGTT_PDE_ENTRY,
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			GTT_TYPE_PPGTT_PDE_PT,
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			GTT_TYPE_PPGTT_PTE_PT,
			GTT_TYPE_PPGTT_PTE_2M_ENTRY),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDE_ENTRY,
			GTT_TYPE_PPGTT_PDE_ENTRY,
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			GTT_TYPE_PPGTT_PDE_PT,
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			GTT_TYPE_PPGTT_PTE_PT,
			GTT_TYPE_PPGTT_PTE_2M_ENTRY),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_PT,
			GTT_TYPE_PPGTT_PTE_4K_ENTRY,
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			GTT_TYPE_PPGTT_PTE_PT,
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			GTT_TYPE_INVALID,
			GTT_TYPE_INVALID),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_4K_ENTRY,
			GTT_TYPE_PPGTT_PTE_4K_ENTRY,
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			GTT_TYPE_PPGTT_PTE_PT,
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			GTT_TYPE_INVALID,
			GTT_TYPE_INVALID),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_2M_ENTRY,
			GTT_TYPE_PPGTT_PDE_ENTRY,
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			GTT_TYPE_PPGTT_PDE_PT,
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			GTT_TYPE_INVALID,
			GTT_TYPE_PPGTT_PTE_2M_ENTRY),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_1G_ENTRY,
			GTT_TYPE_PPGTT_PDP_ENTRY,
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			GTT_TYPE_PPGTT_PDP_PT,
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			GTT_TYPE_INVALID,
			GTT_TYPE_PPGTT_PTE_1G_ENTRY),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_GGTT_PTE,
			GTT_TYPE_GGTT_PTE,
			GTT_TYPE_INVALID,
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			GTT_TYPE_INVALID,
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			GTT_TYPE_INVALID),
};

static inline int get_next_pt_type(int type)
{
	return gtt_type_table[type].next_pt_type;
}

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static inline int get_pt_type(int type)
{
	return gtt_type_table[type].pt_type;
}

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static inline int get_entry_type(int type)
{
	return gtt_type_table[type].entry_type;
}

static inline int get_pse_type(int type)
{
	return gtt_type_table[type].pse_entry_type;
}

static u64 read_pte64(struct drm_i915_private *dev_priv, unsigned long index)
{
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	void __iomem *addr = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + index;
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	return readq(addr);
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}

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static void ggtt_invalidate(struct drm_i915_private *dev_priv)
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{
	mmio_hw_access_pre(dev_priv);
	I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
	mmio_hw_access_post(dev_priv);
}

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static void write_pte64(struct drm_i915_private *dev_priv,
		unsigned long index, u64 pte)
{
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	void __iomem *addr = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + index;
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	writeq(pte, addr);
}

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static inline int gtt_get_entry64(void *pt,
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		struct intel_gvt_gtt_entry *e,
		unsigned long index, bool hypervisor_access, unsigned long gpa,
		struct intel_vgpu *vgpu)
{
	const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
	int ret;

	if (WARN_ON(info->gtt_entry_size != 8))
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		return -EINVAL;
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	if (hypervisor_access) {
		ret = intel_gvt_hypervisor_read_gpa(vgpu, gpa +
				(index << info->gtt_entry_size_shift),
				&e->val64, 8);
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		if (WARN_ON(ret))
			return ret;
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	} else if (!pt) {
		e->val64 = read_pte64(vgpu->gvt->dev_priv, index);
	} else {
		e->val64 = *((u64 *)pt + index);
	}
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	return 0;
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}

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static inline int gtt_set_entry64(void *pt,
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		struct intel_gvt_gtt_entry *e,
		unsigned long index, bool hypervisor_access, unsigned long gpa,
		struct intel_vgpu *vgpu)
{
	const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
	int ret;

	if (WARN_ON(info->gtt_entry_size != 8))
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		return -EINVAL;
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	if (hypervisor_access) {
		ret = intel_gvt_hypervisor_write_gpa(vgpu, gpa +
				(index << info->gtt_entry_size_shift),
				&e->val64, 8);
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		if (WARN_ON(ret))
			return ret;
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	} else if (!pt) {
		write_pte64(vgpu->gvt->dev_priv, index, e->val64);
	} else {
		*((u64 *)pt + index) = e->val64;
	}
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	return 0;
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}

#define GTT_HAW 46

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#define ADDR_1G_MASK (((1UL << (GTT_HAW - 30)) - 1) << 30)
#define ADDR_2M_MASK (((1UL << (GTT_HAW - 21)) - 1) << 21)
#define ADDR_4K_MASK (((1UL << (GTT_HAW - 12)) - 1) << 12)
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static unsigned long gen8_gtt_get_pfn(struct intel_gvt_gtt_entry *e)
{
	unsigned long pfn;

	if (e->type == GTT_TYPE_PPGTT_PTE_1G_ENTRY)
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		pfn = (e->val64 & ADDR_1G_MASK) >> PAGE_SHIFT;
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	else if (e->type == GTT_TYPE_PPGTT_PTE_2M_ENTRY)
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		pfn = (e->val64 & ADDR_2M_MASK) >> PAGE_SHIFT;
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	else
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		pfn = (e->val64 & ADDR_4K_MASK) >> PAGE_SHIFT;
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	return pfn;
}

static void gen8_gtt_set_pfn(struct intel_gvt_gtt_entry *e, unsigned long pfn)
{
	if (e->type == GTT_TYPE_PPGTT_PTE_1G_ENTRY) {
		e->val64 &= ~ADDR_1G_MASK;
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		pfn &= (ADDR_1G_MASK >> PAGE_SHIFT);
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	} else if (e->type == GTT_TYPE_PPGTT_PTE_2M_ENTRY) {
		e->val64 &= ~ADDR_2M_MASK;
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		pfn &= (ADDR_2M_MASK >> PAGE_SHIFT);
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	} else {
		e->val64 &= ~ADDR_4K_MASK;
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		pfn &= (ADDR_4K_MASK >> PAGE_SHIFT);
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	}

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	e->val64 |= (pfn << PAGE_SHIFT);
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}

static bool gen8_gtt_test_pse(struct intel_gvt_gtt_entry *e)
{
	/* Entry doesn't have PSE bit. */
	if (get_pse_type(e->type) == GTT_TYPE_INVALID)
		return false;

	e->type = get_entry_type(e->type);
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	if (!(e->val64 & _PAGE_PSE))
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		return false;

	e->type = get_pse_type(e->type);
	return true;
}

static bool gen8_gtt_test_present(struct intel_gvt_gtt_entry *e)
{
	/*
	 * i915 writes PDP root pointer registers without present bit,
	 * it also works, so we need to treat root pointer entry
	 * specifically.
	 */
	if (e->type == GTT_TYPE_PPGTT_ROOT_L3_ENTRY
			|| e->type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY)
		return (e->val64 != 0);
	else
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		return (e->val64 & _PAGE_PRESENT);
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}

static void gtt_entry_clear_present(struct intel_gvt_gtt_entry *e)
{
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	e->val64 &= ~_PAGE_PRESENT;
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}

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static void gtt_entry_set_present(struct intel_gvt_gtt_entry *e)
{
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	e->val64 |= _PAGE_PRESENT;
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}

/*
 * Per-platform GMA routines.
 */
static unsigned long gma_to_ggtt_pte_index(unsigned long gma)
{
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	unsigned long x = (gma >> I915_GTT_PAGE_SHIFT);
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	trace_gma_index(__func__, gma, x);
	return x;
}

#define DEFINE_PPGTT_GMA_TO_INDEX(prefix, ename, exp) \
static unsigned long prefix##_gma_to_##ename##_index(unsigned long gma) \
{ \
	unsigned long x = (exp); \
	trace_gma_index(__func__, gma, x); \
	return x; \
}

DEFINE_PPGTT_GMA_TO_INDEX(gen8, pte, (gma >> 12 & 0x1ff));
DEFINE_PPGTT_GMA_TO_INDEX(gen8, pde, (gma >> 21 & 0x1ff));
DEFINE_PPGTT_GMA_TO_INDEX(gen8, l3_pdp, (gma >> 30 & 0x3));
DEFINE_PPGTT_GMA_TO_INDEX(gen8, l4_pdp, (gma >> 30 & 0x1ff));
DEFINE_PPGTT_GMA_TO_INDEX(gen8, pml4, (gma >> 39 & 0x1ff));

static struct intel_gvt_gtt_pte_ops gen8_gtt_pte_ops = {
	.get_entry = gtt_get_entry64,
	.set_entry = gtt_set_entry64,
	.clear_present = gtt_entry_clear_present,
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	.set_present = gtt_entry_set_present,
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	.test_present = gen8_gtt_test_present,
	.test_pse = gen8_gtt_test_pse,
	.get_pfn = gen8_gtt_get_pfn,
	.set_pfn = gen8_gtt_set_pfn,
};

static struct intel_gvt_gtt_gma_ops gen8_gtt_gma_ops = {
	.gma_to_ggtt_pte_index = gma_to_ggtt_pte_index,
	.gma_to_pte_index = gen8_gma_to_pte_index,
	.gma_to_pde_index = gen8_gma_to_pde_index,
	.gma_to_l3_pdp_index = gen8_gma_to_l3_pdp_index,
	.gma_to_l4_pdp_index = gen8_gma_to_l4_pdp_index,
	.gma_to_pml4_index = gen8_gma_to_pml4_index,
};

/*
 * MM helpers.
 */
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static void _ppgtt_get_root_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index,
		bool guest)
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{
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	struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
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	GEM_BUG_ON(mm->type != INTEL_GVT_MM_PPGTT);
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	entry->type = mm->ppgtt_mm.root_entry_type;
	pte_ops->get_entry(guest ? mm->ppgtt_mm.guest_pdps :
			   mm->ppgtt_mm.shadow_pdps,
			   entry, index, false, 0, mm->vgpu);
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	pte_ops->test_pse(entry);
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}

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static inline void ppgtt_get_guest_root_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index)
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{
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	_ppgtt_get_root_entry(mm, entry, index, true);
}

static inline void ppgtt_get_shadow_root_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index)
{
	_ppgtt_get_root_entry(mm, entry, index, false);
}

static void _ppgtt_set_root_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index,
		bool guest)
{
	struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;

	pte_ops->set_entry(guest ? mm->ppgtt_mm.guest_pdps :
			   mm->ppgtt_mm.shadow_pdps,
			   entry, index, false, 0, mm->vgpu);
}

static inline void ppgtt_set_guest_root_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index)
{
	_ppgtt_set_root_entry(mm, entry, index, true);
}

static inline void ppgtt_set_shadow_root_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index)
{
	_ppgtt_set_root_entry(mm, entry, index, false);
}

static void ggtt_get_guest_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index)
{
	struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;

	GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);

	entry->type = GTT_TYPE_GGTT_PTE;
	pte_ops->get_entry(mm->ggtt_mm.virtual_ggtt, entry, index,
			   false, 0, mm->vgpu);
}

static void ggtt_set_guest_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index)
{
	struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;

	GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);

	pte_ops->set_entry(mm->ggtt_mm.virtual_ggtt, entry, index,
			   false, 0, mm->vgpu);
}

static void ggtt_set_host_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index)
{
	struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;

	GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);
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	pte_ops->set_entry(NULL, entry, index, false, 0, mm->vgpu);
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}

/*
 * PPGTT shadow page table helpers.
 */
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static inline int ppgtt_spt_get_entry(
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		struct intel_vgpu_ppgtt_spt *spt,
		void *page_table, int type,
		struct intel_gvt_gtt_entry *e, unsigned long index,
		bool guest)
{
	struct intel_gvt *gvt = spt->vgpu->gvt;
	struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
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	int ret;
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	e->type = get_entry_type(type);

	if (WARN(!gtt_type_is_entry(e->type), "invalid entry type\n"))
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		return -EINVAL;
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	ret = ops->get_entry(page_table, e, index, guest,
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			spt->guest_page.gfn << I915_GTT_PAGE_SHIFT,
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			spt->vgpu);
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	if (ret)
		return ret;

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	ops->test_pse(e);
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	gvt_vdbg_mm("read ppgtt entry, spt type %d, entry type %d, index %lu, value %llx\n",
		    type, e->type, index, e->val64);
571
	return 0;
572 573
}

574
static inline int ppgtt_spt_set_entry(
575 576 577 578 579 580 581 582 583
		struct intel_vgpu_ppgtt_spt *spt,
		void *page_table, int type,
		struct intel_gvt_gtt_entry *e, unsigned long index,
		bool guest)
{
	struct intel_gvt *gvt = spt->vgpu->gvt;
	struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;

	if (WARN(!gtt_type_is_entry(e->type), "invalid entry type\n"))
584
		return -EINVAL;
585

586 587 588
	gvt_vdbg_mm("set ppgtt entry, spt type %d, entry type %d, index %lu, value %llx\n",
		    type, e->type, index, e->val64);

589
	return ops->set_entry(page_table, e, index, guest,
590
			spt->guest_page.gfn << I915_GTT_PAGE_SHIFT,
591 592 593 594 595
			spt->vgpu);
}

#define ppgtt_get_guest_entry(spt, e, index) \
	ppgtt_spt_get_entry(spt, NULL, \
596
		spt->guest_page.type, e, index, true)
597 598 599

#define ppgtt_set_guest_entry(spt, e, index) \
	ppgtt_spt_set_entry(spt, NULL, \
600
		spt->guest_page.type, e, index, true)
601 602 603 604 605 606 607 608 609

#define ppgtt_get_shadow_entry(spt, e, index) \
	ppgtt_spt_get_entry(spt, spt->shadow_page.vaddr, \
		spt->shadow_page.type, e, index, false)

#define ppgtt_set_shadow_entry(spt, e, index) \
	ppgtt_spt_set_entry(spt, spt->shadow_page.vaddr, \
		spt->shadow_page.type, e, index, false)

610
static void *alloc_spt(gfp_t gfp_mask)
611
{
612
	struct intel_vgpu_ppgtt_spt *spt;
613

614 615 616
	spt = kzalloc(sizeof(*spt), gfp_mask);
	if (!spt)
		return NULL;
617

618 619 620 621 622 623
	spt->shadow_page.page = alloc_page(gfp_mask);
	if (!spt->shadow_page.page) {
		kfree(spt);
		return NULL;
	}
	return spt;
624 625
}

626
static void free_spt(struct intel_vgpu_ppgtt_spt *spt)
627
{
628 629
	__free_page(spt->shadow_page.page);
	kfree(spt);
630 631
}

632 633 634
static int detach_oos_page(struct intel_vgpu *vgpu,
		struct intel_vgpu_oos_page *oos_page);

635
static void ppgtt_free_spt(struct intel_vgpu_ppgtt_spt *spt)
636
{
637
	struct device *kdev = &spt->vgpu->gvt->dev_priv->drm.pdev->dev;
638

639
	trace_spt_free(spt->vgpu->id, spt, spt->guest_page.type);
640

641 642 643 644
	dma_unmap_page(kdev, spt->shadow_page.mfn << I915_GTT_PAGE_SHIFT, 4096,
		       PCI_DMA_BIDIRECTIONAL);
	if (!hlist_unhashed(&spt->node))
		hash_del(&spt->node);
645

646 647
	if (spt->guest_page.oos_page)
		detach_oos_page(spt->vgpu, spt->guest_page.oos_page);
648

649
	intel_vgpu_unregister_page_track(spt->vgpu, spt->guest_page.gfn);
650 651 652 653 654

	list_del_init(&spt->post_shadow_list);
	free_spt(spt);
}

655
static void ppgtt_free_all_spt(struct intel_vgpu *vgpu)
656 657
{
	struct hlist_node *n;
658
	struct intel_vgpu_ppgtt_spt *spt;
659 660
	int i;

661 662
	hash_for_each_safe(vgpu->gtt.spt_hash_table, i, n, spt, node)
		ppgtt_free_spt(spt);
663 664
}

665
static int ppgtt_handle_guest_write_page_table_bytes(
666
		struct intel_vgpu_ppgtt_spt *spt,
667 668
		u64 pa, void *p_data, int bytes);

669 670 671
static int ppgtt_write_protection_handler(
		struct intel_vgpu_page_track *page_track,
		u64 gpa, void *data, int bytes)
672
{
673 674
	struct intel_vgpu_ppgtt_spt *spt = page_track->priv_data;

675 676 677 678 679
	int ret;

	if (bytes != 4 && bytes != 8)
		return -EINVAL;

680
	ret = ppgtt_handle_guest_write_page_table_bytes(spt, gpa, data, bytes);
681 682 683 684 685
	if (ret)
		return ret;
	return ret;
}

686 687 688 689 690 691
/* Find a spt by guest gfn. */
static struct intel_vgpu_ppgtt_spt *intel_vgpu_find_spt_by_gfn(
		struct intel_vgpu *vgpu, unsigned long gfn)
{
	struct intel_vgpu_page_track *track;

692 693 694
	track = intel_vgpu_find_page_track(vgpu, gfn);
	if (track && track->handler == ppgtt_write_protection_handler)
		return track->priv_data;
695 696 697 698 699 700 701 702 703 704

	return NULL;
}

/* Find the spt by shadow page mfn. */
static struct intel_vgpu_ppgtt_spt *intel_vgpu_find_spt_by_mfn(
		struct intel_vgpu *vgpu, unsigned long mfn)
{
	struct intel_vgpu_ppgtt_spt *spt;

705
	hash_for_each_possible(vgpu->gtt.spt_hash_table, spt, node, mfn) {
706 707 708 709 710 711
		if (spt->shadow_page.mfn == mfn)
			return spt;
	}
	return NULL;
}

712
static int reclaim_one_ppgtt_mm(struct intel_gvt *gvt);
713

714
static struct intel_vgpu_ppgtt_spt *ppgtt_alloc_spt(
715 716
		struct intel_vgpu *vgpu, int type, unsigned long gfn)
{
717
	struct device *kdev = &vgpu->gvt->dev_priv->drm.pdev->dev;
718
	struct intel_vgpu_ppgtt_spt *spt = NULL;
719
	dma_addr_t daddr;
720
	int ret;
721 722 723 724

retry:
	spt = alloc_spt(GFP_KERNEL | __GFP_ZERO);
	if (!spt) {
725
		if (reclaim_one_ppgtt_mm(vgpu->gvt))
726 727
			goto retry;

728
		gvt_vgpu_err("fail to allocate ppgtt shadow page\n");
729 730 731 732 733 734 735 736
		return ERR_PTR(-ENOMEM);
	}

	spt->vgpu = vgpu;
	atomic_set(&spt->refcount, 1);
	INIT_LIST_HEAD(&spt->post_shadow_list);

	/*
737
	 * Init shadow_page.
738
	 */
739 740 741 742 743 744 745
	spt->shadow_page.type = type;
	daddr = dma_map_page(kdev, spt->shadow_page.page,
			     0, 4096, PCI_DMA_BIDIRECTIONAL);
	if (dma_mapping_error(kdev, daddr)) {
		gvt_vgpu_err("fail to map dma addr\n");
		free_spt(spt);
		return ERR_PTR(-EINVAL);
746
	}
747 748
	spt->shadow_page.vaddr = page_address(spt->shadow_page.page);
	spt->shadow_page.mfn = daddr >> I915_GTT_PAGE_SHIFT;
749

750 751 752 753 754
	/*
	 * Init guest_page.
	 */
	spt->guest_page.type = type;
	spt->guest_page.gfn = gfn;
755

756 757 758 759 760 761 762
	ret = intel_vgpu_register_page_track(vgpu, spt->guest_page.gfn,
					ppgtt_write_protection_handler, spt);
	if (ret) {
		free_spt(spt);
		dma_unmap_page(kdev, daddr, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
		return ERR_PTR(ret);
	}
763

764
	INIT_HLIST_NODE(&spt->node);
765
	hash_add(vgpu->gtt.spt_hash_table, &spt->node, spt->shadow_page.mfn);
766

767 768
	trace_spt_alloc(vgpu->id, spt, type, spt->shadow_page.mfn, gfn);
	return spt;
769 770 771 772 773 774
}

#define pt_entry_size_shift(spt) \
	((spt)->vgpu->gvt->device_info.gtt_entry_size_shift)

#define pt_entries(spt) \
775
	(I915_GTT_PAGE_SIZE >> pt_entry_size_shift(spt))
776 777 778

#define for_each_present_guest_entry(spt, e, i) \
	for (i = 0; i < pt_entries(spt); i++) \
779 780
		if (!ppgtt_get_guest_entry(spt, e, i) && \
		    spt->vgpu->gvt->gtt.pte_ops->test_present(e))
781 782 783

#define for_each_present_shadow_entry(spt, e, i) \
	for (i = 0; i < pt_entries(spt); i++) \
784 785
		if (!ppgtt_get_shadow_entry(spt, e, i) && \
		    spt->vgpu->gvt->gtt.pte_ops->test_present(e))
786

787
static void ppgtt_get_spt(struct intel_vgpu_ppgtt_spt *spt)
788 789 790 791 792 793 794 795
{
	int v = atomic_read(&spt->refcount);

	trace_spt_refcount(spt->vgpu->id, "inc", spt, v, (v + 1));

	atomic_inc(&spt->refcount);
}

796
static int ppgtt_invalidate_spt(struct intel_vgpu_ppgtt_spt *spt);
797

798
static int ppgtt_invalidate_spt_by_shadow_entry(struct intel_vgpu *vgpu,
799 800 801 802
		struct intel_gvt_gtt_entry *e)
{
	struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
	struct intel_vgpu_ppgtt_spt *s;
803
	intel_gvt_gtt_type_t cur_pt_type;
804

805
	GEM_BUG_ON(!gtt_type_is_pt(get_next_pt_type(e->type)));
806

807 808 809 810 811 812 813
	if (e->type != GTT_TYPE_PPGTT_ROOT_L3_ENTRY
		&& e->type != GTT_TYPE_PPGTT_ROOT_L4_ENTRY) {
		cur_pt_type = get_next_pt_type(e->type) + 1;
		if (ops->get_pfn(e) ==
			vgpu->gtt.scratch_pt[cur_pt_type].page_mfn)
			return 0;
	}
814
	s = intel_vgpu_find_spt_by_mfn(vgpu, ops->get_pfn(e));
815
	if (!s) {
816 817
		gvt_vgpu_err("fail to find shadow page: mfn: 0x%lx\n",
				ops->get_pfn(e));
818 819
		return -ENXIO;
	}
820
	return ppgtt_invalidate_spt(s);
821 822
}

823
static int ppgtt_invalidate_spt(struct intel_vgpu_ppgtt_spt *spt)
824
{
825
	struct intel_vgpu *vgpu = spt->vgpu;
826 827 828 829 830 831
	struct intel_gvt_gtt_entry e;
	unsigned long index;
	int ret;
	int v = atomic_read(&spt->refcount);

	trace_spt_change(spt->vgpu->id, "die", spt,
832
			spt->guest_page.gfn, spt->shadow_page.type);
833 834 835 836 837 838 839 840 841 842

	trace_spt_refcount(spt->vgpu->id, "dec", spt, v, (v - 1));

	if (atomic_dec_return(&spt->refcount) > 0)
		return 0;

	if (gtt_type_is_pte_pt(spt->shadow_page.type))
		goto release;

	for_each_present_shadow_entry(spt, &e, index) {
843 844 845 846 847 848 849 850 851 852 853 854
		switch (e.type) {
		case GTT_TYPE_PPGTT_PTE_4K_ENTRY:
			gvt_vdbg_mm("invalidate 4K entry\n");
			continue;
		case GTT_TYPE_PPGTT_PTE_2M_ENTRY:
		case GTT_TYPE_PPGTT_PTE_1G_ENTRY:
			WARN(1, "GVT doesn't support 2M/1GB page\n");
			continue;
		case GTT_TYPE_PPGTT_PML4_ENTRY:
		case GTT_TYPE_PPGTT_PDP_ENTRY:
		case GTT_TYPE_PPGTT_PDE_ENTRY:
			gvt_vdbg_mm("invalidate PMUL4/PDP/PDE entry\n");
855
			ret = ppgtt_invalidate_spt_by_shadow_entry(
856 857 858 859 860 861
					spt->vgpu, &e);
			if (ret)
				goto fail;
			break;
		default:
			GEM_BUG_ON(1);
862 863 864 865
		}
	}
release:
	trace_spt_change(spt->vgpu->id, "release", spt,
866
			 spt->guest_page.gfn, spt->shadow_page.type);
867
	ppgtt_free_spt(spt);
868 869
	return 0;
fail:
870 871
	gvt_vgpu_err("fail: shadow page %p shadow entry 0x%llx type %d\n",
			spt, e.val64, e.type);
872 873 874
	return ret;
}

875
static int ppgtt_populate_spt(struct intel_vgpu_ppgtt_spt *spt);
876

877
static struct intel_vgpu_ppgtt_spt *ppgtt_populate_spt_by_guest_entry(
878 879 880
		struct intel_vgpu *vgpu, struct intel_gvt_gtt_entry *we)
{
	struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
881
	struct intel_vgpu_ppgtt_spt *spt = NULL;
882 883
	int ret;

884
	GEM_BUG_ON(!gtt_type_is_pt(get_next_pt_type(we->type)));
885

886 887
	spt = intel_vgpu_find_spt_by_gfn(vgpu, ops->get_pfn(we));
	if (spt)
888
		ppgtt_get_spt(spt);
889
	else {
890 891
		int type = get_next_pt_type(we->type);

892
		spt = ppgtt_alloc_spt(vgpu, type, ops->get_pfn(we));
893 894
		if (IS_ERR(spt)) {
			ret = PTR_ERR(spt);
895 896 897
			goto fail;
		}

898
		ret = intel_vgpu_enable_page_track(vgpu, spt->guest_page.gfn);
899 900 901
		if (ret)
			goto fail;

902
		ret = ppgtt_populate_spt(spt);
903 904 905
		if (ret)
			goto fail;

906 907
		trace_spt_change(vgpu->id, "new", spt, spt->guest_page.gfn,
				 spt->shadow_page.type);
908
	}
909
	return spt;
910
fail:
911
	gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n",
912
		     spt, we->val64, we->type);
913 914 915 916 917 918 919 920 921 922 923 924 925 926
	return ERR_PTR(ret);
}

static inline void ppgtt_generate_shadow_entry(struct intel_gvt_gtt_entry *se,
		struct intel_vgpu_ppgtt_spt *s, struct intel_gvt_gtt_entry *ge)
{
	struct intel_gvt_gtt_pte_ops *ops = s->vgpu->gvt->gtt.pte_ops;

	se->type = ge->type;
	se->val64 = ge->val64;

	ops->set_pfn(se, s->shadow_page.mfn);
}

927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961
static int ppgtt_populate_shadow_entry(struct intel_vgpu *vgpu,
	struct intel_vgpu_ppgtt_spt *spt, unsigned long index,
	struct intel_gvt_gtt_entry *ge)
{
	struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
	struct intel_gvt_gtt_entry se = *ge;
	unsigned long gfn, mfn;

	if (!pte_ops->test_present(ge))
		return 0;

	gfn = pte_ops->get_pfn(ge);

	switch (ge->type) {
	case GTT_TYPE_PPGTT_PTE_4K_ENTRY:
		gvt_vdbg_mm("shadow 4K gtt entry\n");
		break;
	case GTT_TYPE_PPGTT_PTE_2M_ENTRY:
	case GTT_TYPE_PPGTT_PTE_1G_ENTRY:
		gvt_vgpu_err("GVT doesn't support 2M/1GB entry\n");
		return -EINVAL;
	default:
		GEM_BUG_ON(1);
	};

	/* direct shadow */
	mfn = intel_gvt_hypervisor_gfn_to_mfn(vgpu, gfn);
	if (mfn == INTEL_GVT_INVALID_ADDR)
		return -ENXIO;

	pte_ops->set_pfn(&se, mfn);
	ppgtt_set_shadow_entry(spt, &se, index);
	return 0;
}

962
static int ppgtt_populate_spt(struct intel_vgpu_ppgtt_spt *spt)
963 964
{
	struct intel_vgpu *vgpu = spt->vgpu;
965 966
	struct intel_gvt *gvt = vgpu->gvt;
	struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
967 968
	struct intel_vgpu_ppgtt_spt *s;
	struct intel_gvt_gtt_entry se, ge;
969
	unsigned long gfn, i;
970 971 972
	int ret;

	trace_spt_change(spt->vgpu->id, "born", spt,
973
			 spt->guest_page.gfn, spt->shadow_page.type);
974

975 976
	for_each_present_guest_entry(spt, &ge, i) {
		if (gtt_type_is_pt(get_next_pt_type(ge.type))) {
977
			s = ppgtt_populate_spt_by_guest_entry(vgpu, &ge);
978 979 980 981 982 983 984 985
			if (IS_ERR(s)) {
				ret = PTR_ERR(s);
				goto fail;
			}
			ppgtt_get_shadow_entry(spt, &se, i);
			ppgtt_generate_shadow_entry(&se, s, &ge);
			ppgtt_set_shadow_entry(spt, &se, i);
		} else {
986
			gfn = ops->get_pfn(&ge);
987
			if (!intel_gvt_hypervisor_is_valid_gfn(vgpu, gfn)) {
988
				ops->set_pfn(&se, gvt->gtt.scratch_mfn);
989 990 991
				ppgtt_set_shadow_entry(spt, &se, i);
				continue;
			}
992

993 994 995
			ret = ppgtt_populate_shadow_entry(vgpu, spt, i, &ge);
			if (ret)
				goto fail;
996 997 998 999
		}
	}
	return 0;
fail:
1000 1001
	gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n",
			spt, ge.val64, ge.type);
1002 1003 1004
	return ret;
}

1005
static int ppgtt_handle_guest_entry_removal(struct intel_vgpu_ppgtt_spt *spt,
1006
		struct intel_gvt_gtt_entry *se, unsigned long index)
1007 1008 1009 1010 1011
{
	struct intel_vgpu *vgpu = spt->vgpu;
	struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
	int ret;

1012 1013
	trace_spt_guest_change(spt->vgpu->id, "remove", spt,
			       spt->shadow_page.type, se->val64, index);
1014

1015 1016 1017
	gvt_vdbg_mm("destroy old shadow entry, type %d, index %lu, value %llx\n",
		    se->type, index, se->val64);

1018
	if (!ops->test_present(se))
1019 1020
		return 0;

1021 1022
	if (ops->get_pfn(se) ==
	    vgpu->gtt.scratch_pt[spt->shadow_page.type].page_mfn)
1023 1024
		return 0;

1025
	if (gtt_type_is_pt(get_next_pt_type(se->type))) {
1026
		struct intel_vgpu_ppgtt_spt *s =
1027
			intel_vgpu_find_spt_by_mfn(vgpu, ops->get_pfn(se));
1028
		if (!s) {
1029
			gvt_vgpu_err("fail to find guest page\n");
1030 1031 1032
			ret = -ENXIO;
			goto fail;
		}
1033
		ret = ppgtt_invalidate_spt(s);
1034 1035 1036 1037 1038
		if (ret)
			goto fail;
	}
	return 0;
fail:
1039
	gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n",
1040
			spt, se->val64, se->type);
1041 1042 1043
	return ret;
}

1044
static int ppgtt_handle_guest_entry_add(struct intel_vgpu_ppgtt_spt *spt,
1045 1046 1047 1048 1049 1050 1051
		struct intel_gvt_gtt_entry *we, unsigned long index)
{
	struct intel_vgpu *vgpu = spt->vgpu;
	struct intel_gvt_gtt_entry m;
	struct intel_vgpu_ppgtt_spt *s;
	int ret;

1052 1053
	trace_spt_guest_change(spt->vgpu->id, "add", spt, spt->shadow_page.type,
			       we->val64, index);
1054

1055 1056 1057
	gvt_vdbg_mm("add shadow entry: type %d, index %lu, value %llx\n",
		    we->type, index, we->val64);

1058
	if (gtt_type_is_pt(get_next_pt_type(we->type))) {
1059
		s = ppgtt_populate_spt_by_guest_entry(vgpu, we);
1060 1061 1062 1063 1064 1065 1066 1067
		if (IS_ERR(s)) {
			ret = PTR_ERR(s);
			goto fail;
		}
		ppgtt_get_shadow_entry(spt, &m, index);
		ppgtt_generate_shadow_entry(&m, s, we);
		ppgtt_set_shadow_entry(spt, &m, index);
	} else {
1068
		ret = ppgtt_populate_shadow_entry(vgpu, spt, index, we);
1069 1070 1071 1072 1073
		if (ret)
			goto fail;
	}
	return 0;
fail:
1074 1075
	gvt_vgpu_err("fail: spt %p guest entry 0x%llx type %d\n",
		spt, we->val64, we->type);
1076 1077 1078 1079 1080 1081 1082 1083 1084
	return ret;
}

static int sync_oos_page(struct intel_vgpu *vgpu,
		struct intel_vgpu_oos_page *oos_page)
{
	const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
	struct intel_gvt *gvt = vgpu->gvt;
	struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
1085
	struct intel_vgpu_ppgtt_spt *spt = oos_page->spt;
1086
	struct intel_gvt_gtt_entry old, new;
1087 1088 1089 1090
	int index;
	int ret;

	trace_oos_change(vgpu->id, "sync", oos_page->id,
1091
			 spt, spt->guest_page.type);
1092

1093
	old.type = new.type = get_entry_type(spt->guest_page.type);
1094 1095
	old.val64 = new.val64 = 0;

1096 1097
	for (index = 0; index < (I915_GTT_PAGE_SIZE >>
				info->gtt_entry_size_shift); index++) {
1098 1099
		ops->get_entry(oos_page->mem, &old, index, false, 0, vgpu);
		ops->get_entry(NULL, &new, index, true,
1100
			       spt->guest_page.gfn << PAGE_SHIFT