rcar_du_group.c 7.92 KB
Newer Older
1 2 3
/*
 * rcar_du_group.c  --  R-Car Display Unit Channels Pair
 *
4
 * Copyright (C) 2013-2015 Renesas Electronics Corporation
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
 *
 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

/*
 * The R8A7779 DU is split in per-CRTC resources (scan-out engine, blending
 * unit, timings generator, ...) and device-global resources (start/stop
 * control, planes, ...) shared between the two CRTCs.
 *
 * The R8A7790 introduced a third CRTC with its own set of global resources.
 * This would be modeled as two separate DU device instances if it wasn't for
 * a handful or resources that are shared between the three CRTCs (mostly
 * related to input and output routing). For this reason the R8A7790 DU must be
 * modeled as a single device with three CRTCs, two sets of "semi-global"
 * resources, and a few device-global resources.
 *
 * The rcar_du_group object is a driver specific object, without any real
 * counterpart in the DU documentation, that models those semi-global resources.
 */

30
#include <linux/clk.h>
31 32 33 34 35 36
#include <linux/io.h>

#include "rcar_du_drv.h"
#include "rcar_du_group.h"
#include "rcar_du_regs.h"

37
u32 rcar_du_group_read(struct rcar_du_group *rgrp, u32 reg)
38 39 40 41
{
	return rcar_du_read(rgrp->dev, rgrp->mmio_offset + reg);
}

42
void rcar_du_group_write(struct rcar_du_group *rgrp, u32 reg, u32 data)
43 44 45 46
{
	rcar_du_write(rgrp->dev, rgrp->mmio_offset + reg, data);
}

47 48
static void rcar_du_group_setup_pins(struct rcar_du_group *rgrp)
{
49
	u32 defr6 = DEFR6_CODE;
50

51 52 53 54
	if (rgrp->channels_mask & BIT(0))
		defr6 |= DEFR6_ODPM02_DISP;

	if (rgrp->channels_mask & BIT(1))
55
		defr6 |= DEFR6_ODPM12_DISP;
56 57 58 59

	rcar_du_group_write(rgrp, DEFR6, defr6);
}

60 61
static void rcar_du_group_setup_defr8(struct rcar_du_group *rgrp)
{
62 63 64 65
	struct rcar_du_device *rcdu = rgrp->dev;
	unsigned int possible_crtcs =
		rcdu->info->routes[RCAR_DU_OUTPUT_DPAD0].possible_crtcs;
	u32 defr8 = DEFR8_CODE;
66

67 68 69
	if (rcdu->info->gen < 3) {
		defr8 |= DEFR8_DEFE8;

70 71
		/*
		 * On Gen2 the DEFR8 register for the first group also controls
72 73 74 75 76 77 78 79 80 81
		 * RGB output routing to DPAD0 and VSPD1 routing to DU0/1/2 for
		 * DU instances that support it.
		 */
		if (rgrp->index == 0) {
			if (possible_crtcs > 1)
				defr8 |= DEFR8_DRGBS_DU(rcdu->dpad0_source);
			if (rgrp->dev->vspd1_sink == 2)
				defr8 |= DEFR8_VSCS;
		}
	} else {
82 83
		/*
		 * On Gen3 VSPD routing can't be configured, but DPAD routing
84 85
		 * needs to be set despite having a single option available.
		 */
86 87
		unsigned int rgb_crtc = ffs(possible_crtcs) - 1;
		struct rcar_du_crtc *crtc = &rcdu->crtcs[rgb_crtc];
88

89 90
		if (crtc->index / 2 == rgrp->index)
			defr8 |= DEFR8_DRGBS_DU(crtc->index);
91
	}
92 93 94 95

	rcar_du_group_write(rgrp, DEFR8, defr8);
}

96 97
static void rcar_du_group_setup(struct rcar_du_group *rgrp)
{
98 99
	struct rcar_du_device *rcdu = rgrp->dev;

100 101
	/* Enable extended features */
	rcar_du_group_write(rgrp, DEFR, DEFR_CODE | DEFR_DEFE);
102 103 104 105 106
	if (rcdu->info->gen < 3) {
		rcar_du_group_write(rgrp, DEFR2, DEFR2_CODE | DEFR2_DEFE2G);
		rcar_du_group_write(rgrp, DEFR3, DEFR3_CODE | DEFR3_DEFE3);
		rcar_du_group_write(rgrp, DEFR4, DEFR4_CODE);
	}
107
	rcar_du_group_write(rgrp, DEFR5, DEFR5_CODE | DEFR5_DEFE5);
108

109 110
	rcar_du_group_setup_pins(rgrp);

111
	if (rcar_du_has(rgrp->dev, RCAR_DU_FEATURE_EXT_CTRL_REGS)) {
112
		rcar_du_group_setup_defr8(rgrp);
113

114 115 116 117 118 119 120 121 122 123
		/*
		 * Configure input dot clock routing. We currently hardcode the
		 * configuration to routing DOTCLKINn to DUn. Register fields
		 * depend on the DU generation, but the resulting value is 0 in
		 * all cases.
		 *
		 * On Gen2 a single register in the first group controls dot
		 * clock selection for all channels, while on Gen3 dot clocks
		 * are setup through per-group registers, only available when
		 * the group has two channels.
124
		 */
125 126 127
		if ((rcdu->info->gen < 3 && rgrp->index == 0) ||
		    (rcdu->info->gen == 3 &&  rgrp->num_crtcs > 1))
			rcar_du_group_write(rgrp, DIDSR, DIDSR_CODE);
128 129
	}

130 131 132
	if (rcdu->info->gen >= 3)
		rcar_du_group_write(rgrp, DEFR10, DEFR10_CODE | DEFR10_DEFE10);

133 134
	/*
	 * Use DS1PR and DS2PR to configure planes priorities and connects the
135 136 137
	 * superposition 0 to DU0 pins. DU1 pins will be configured dynamically.
	 */
	rcar_du_group_write(rgrp, DORCR, DORCR_PG1D_DS1 | DORCR_DPRS);
138 139 140 141 142 143

	/* Apply planes to CRTCs association. */
	mutex_lock(&rgrp->lock);
	rcar_du_group_write(rgrp, DPTSR, (rgrp->dptsr_planes << 16) |
			    rgrp->dptsr_planes);
	mutex_unlock(&rgrp->lock);
144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186
}

/*
 * rcar_du_group_get - Acquire a reference to the DU channels group
 *
 * Acquiring the first reference setups core registers. A reference must be held
 * before accessing any hardware registers.
 *
 * This function must be called with the DRM mode_config lock held.
 *
 * Return 0 in case of success or a negative error code otherwise.
 */
int rcar_du_group_get(struct rcar_du_group *rgrp)
{
	if (rgrp->use_count)
		goto done;

	rcar_du_group_setup(rgrp);

done:
	rgrp->use_count++;
	return 0;
}

/*
 * rcar_du_group_put - Release a reference to the DU
 *
 * This function must be called with the DRM mode_config lock held.
 */
void rcar_du_group_put(struct rcar_du_group *rgrp)
{
	--rgrp->use_count;
}

static void __rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start)
{
	rcar_du_group_write(rgrp, DSYSR,
		(rcar_du_group_read(rgrp, DSYSR) & ~(DSYSR_DRES | DSYSR_DEN)) |
		(start ? DSYSR_DEN : DSYSR_DRES));
}

void rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start)
{
187 188
	/*
	 * Many of the configuration bits are only updated when the display
189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210
	 * reset (DRES) bit in DSYSR is set to 1, disabling *both* CRTCs. Some
	 * of those bits could be pre-configured, but others (especially the
	 * bits related to plane assignment to display timing controllers) need
	 * to be modified at runtime.
	 *
	 * Restart the display controller if a start is requested. Sorry for the
	 * flicker. It should be possible to move most of the "DRES-update" bits
	 * setup to driver initialization time and minimize the number of cases
	 * when the display controller will have to be restarted.
	 */
	if (start) {
		if (rgrp->used_crtcs++ != 0)
			__rcar_du_group_start_stop(rgrp, false);
		__rcar_du_group_start_stop(rgrp, true);
	} else {
		if (--rgrp->used_crtcs == 0)
			__rcar_du_group_start_stop(rgrp, false);
	}
}

void rcar_du_group_restart(struct rcar_du_group *rgrp)
{
211 212
	rgrp->need_restart = false;

213 214 215
	__rcar_du_group_start_stop(rgrp, false);
	__rcar_du_group_start_stop(rgrp, true);
}
216

217
int rcar_du_set_dpad0_vsp1_routing(struct rcar_du_device *rcdu)
218
{
219 220 221
	struct rcar_du_group *rgrp;
	struct rcar_du_crtc *crtc;
	unsigned int index;
222 223
	int ret;

224 225 226
	if (!rcar_du_has(rcdu, RCAR_DU_FEATURE_EXT_CTRL_REGS))
		return 0;

227 228
	/*
	 * RGB output routing to DPAD0 and VSP1D routing to DU0/1/2 are
229 230 231 232
	 * configured in the DEFR8 register of the first group on Gen2 and the
	 * last group on Gen3. As this function can be called with the DU
	 * channels of the corresponding CRTCs disabled, we need to enable the
	 * group clock before accessing the register.
233
	 */
234 235 236 237 238
	index = rcdu->info->gen < 3 ? 0 : DIV_ROUND_UP(rcdu->num_crtcs, 2) - 1;
	rgrp = &rcdu->groups[index];
	crtc = &rcdu->crtcs[index * 2];

	ret = clk_prepare_enable(crtc->clock);
239 240 241
	if (ret < 0)
		return ret;

242
	rcar_du_group_setup_defr8(rgrp);
243

244
	clk_disable_unprepare(crtc->clock);
245 246 247 248 249

	return 0;
}

int rcar_du_group_set_routing(struct rcar_du_group *rgrp)
250 251 252 253 254 255
{
	struct rcar_du_crtc *crtc0 = &rgrp->dev->crtcs[rgrp->index * 2];
	u32 dorcr = rcar_du_group_read(rgrp, DORCR);

	dorcr &= ~(DORCR_PG2T | DORCR_DK2S | DORCR_PG2D_MASK);

256 257
	/*
	 * Set the DPAD1 pins sources. Select CRTC 0 if explicitly requested and
258 259
	 * CRTC 1 in all other cases to avoid cloning CRTC 0 to DPAD0 and DPAD1
	 * by default.
260
	 */
261
	if (crtc0->outputs & BIT(RCAR_DU_OUTPUT_DPAD1))
262 263 264 265 266
		dorcr |= DORCR_PG2D_DS1;
	else
		dorcr |= DORCR_PG2T | DORCR_DK2S | DORCR_PG2D_DS2;

	rcar_du_group_write(rgrp, DORCR, dorcr);
267

268
	return rcar_du_set_dpad0_vsp1_routing(rgrp->dev);
269
}