nvme.h 9.27 KB
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/*
 * Copyright (c) 2011-2014, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */

#ifndef _NVME_H
#define _NVME_H

#include <linux/nvme.h>
#include <linux/pci.h>
#include <linux/kref.h>
#include <linux/blk-mq.h>
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#include <linux/lightnvm.h>
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#include <linux/sed-opal.h>
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extern unsigned int nvme_io_timeout;
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#define NVME_IO_TIMEOUT	(nvme_io_timeout * HZ)

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extern unsigned int admin_timeout;
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#define ADMIN_TIMEOUT	(admin_timeout * HZ)

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#define NVME_DEFAULT_KATO	5
#define NVME_KATO_GRACE		10

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extern struct workqueue_struct *nvme_wq;

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enum {
	NVME_NS_LBA		= 0,
	NVME_NS_LIGHTNVM	= 1,
};

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/*
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 * List of workarounds for devices that required behavior not specified in
 * the standard.
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 */
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enum nvme_quirks {
	/*
	 * Prefers I/O aligned to a stripe size specified in a vendor
	 * specific Identify field.
	 */
	NVME_QUIRK_STRIPE_SIZE			= (1 << 0),
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	/*
	 * The controller doesn't handle Identify value others than 0 or 1
	 * correctly.
	 */
	NVME_QUIRK_IDENTIFY_CNS			= (1 << 1),
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	/*
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	 * The controller deterministically returns O's on reads to
	 * logical blocks that deallocate was called on.
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	 */
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	NVME_QUIRK_DEALLOCATE_ZEROES		= (1 << 2),
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	/*
	 * The controller needs a delay before starts checking the device
	 * readiness, which is done by reading the NVME_CSTS_RDY bit.
	 */
	NVME_QUIRK_DELAY_BEFORE_CHK_RDY		= (1 << 3),
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	/*
	 * APST should not be used.
	 */
	NVME_QUIRK_NO_APST			= (1 << 4),
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	/*
	 * The deepest sleep state should not be used.
	 */
	NVME_QUIRK_NO_DEEPEST_PS		= (1 << 5),
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	/*
	 * Supports the LighNVM command set if indicated in vs[1].
	 */
	NVME_QUIRK_LIGHTNVM			= (1 << 6),
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};

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/*
 * Common request structure for NVMe passthrough.  All drivers must have
 * this structure as the first member of their request-private data.
 */
struct nvme_request {
	struct nvme_command	*cmd;
	union nvme_result	result;
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	u8			retries;
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	u8			flags;
	u16			status;
};

enum {
	NVME_REQ_CANCELLED		= (1 << 0),
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};

static inline struct nvme_request *nvme_req(struct request *req)
{
	return blk_mq_rq_to_pdu(req);
}

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/* The below value is the specific amount of delay needed before checking
 * readiness in case of the PCI_DEVICE(0x1c58, 0x0003), which needs the
 * NVME_QUIRK_DELAY_BEFORE_CHK_RDY quirk enabled. The value (in ms) was
 * found empirically.
 */
#define NVME_QUIRK_DELAY_AMOUNT		2000

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enum nvme_ctrl_state {
	NVME_CTRL_NEW,
	NVME_CTRL_LIVE,
	NVME_CTRL_RESETTING,
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	NVME_CTRL_RECONNECTING,
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	NVME_CTRL_DELETING,
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	NVME_CTRL_DEAD,
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};

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struct nvme_ctrl {
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	enum nvme_ctrl_state state;
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	bool identified;
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	spinlock_t lock;
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	const struct nvme_ctrl_ops *ops;
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	struct request_queue *admin_q;
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	struct request_queue *connect_q;
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	struct device *dev;
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	struct kref kref;
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	int instance;
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	struct blk_mq_tag_set *tagset;
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	struct blk_mq_tag_set *admin_tagset;
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	struct list_head namespaces;
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	struct mutex namespaces_mutex;
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	struct device *device;	/* char device */
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	struct list_head node;
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	struct ida ns_ida;
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	struct work_struct reset_work;
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	struct opal_dev *opal_dev;
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	char name[12];
	char serial[20];
	char model[40];
	char firmware_rev[8];
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	char subnqn[NVMF_NQN_SIZE];
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	u16 cntlid;
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	u32 ctrl_config;
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	u16 mtfa;
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	u32 queue_count;
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	u64 cap;
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	u32 page_size;
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	u32 max_hw_sectors;
	u16 oncs;
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	u16 vid;
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	u16 oacs;
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	u16 nssa;
	u16 nr_streams;
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	atomic_t abort_limit;
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	u8 event_limit;
	u8 vwc;
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	u32 vs;
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	u32 sgls;
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	u16 kas;
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	u8 npss;
	u8 apsta;
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	unsigned int shutdown_timeout;
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	unsigned int kato;
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	bool subsystem;
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	unsigned long quirks;
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	struct nvme_id_power_state psd[32];
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	struct work_struct scan_work;
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	struct work_struct async_event_work;
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	struct delayed_work ka_work;
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	struct work_struct fw_act_work;
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	/* Power saving configuration */
	u64 ps_max_latency_us;
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	bool apst_enabled;
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	/* PCIe only: */
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	u32 hmpre;
	u32 hmmin;
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	u32 hmminds;
	u16 hmmaxd;
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	/* Fabrics only */
	u16 sqsize;
	u32 ioccsz;
	u32 iorcsz;
	u16 icdoff;
	u16 maxcmd;
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	int nr_reconnects;
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	struct nvmf_ctrl_options *opts;
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};

struct nvme_ns {
	struct list_head list;

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	struct nvme_ctrl *ctrl;
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	struct request_queue *queue;
	struct gendisk *disk;
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	struct nvm_dev *ndev;
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	struct kref kref;
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	int instance;
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	u8 eui[8];
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	u8 nguid[16];
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	uuid_t uuid;
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	unsigned ns_id;
	int lba_shift;
	u16 ms;
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	u16 sgs;
	u32 sws;
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	bool ext;
	u8 pi_type;
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	unsigned long flags;
#define NVME_NS_REMOVING 0
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#define NVME_NS_DEAD     1
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	u16 noiob;
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};

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struct nvme_ctrl_ops {
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	const char *name;
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	struct module *module;
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	unsigned int flags;
#define NVME_F_FABRICS			(1 << 0)
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#define NVME_F_METADATA_SUPPORTED	(1 << 1)
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	int (*reg_read32)(struct nvme_ctrl *ctrl, u32 off, u32 *val);
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	int (*reg_write32)(struct nvme_ctrl *ctrl, u32 off, u32 val);
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	int (*reg_read64)(struct nvme_ctrl *ctrl, u32 off, u64 *val);
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	void (*free_ctrl)(struct nvme_ctrl *ctrl);
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	void (*submit_async_event)(struct nvme_ctrl *ctrl, int aer_idx);
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	int (*delete_ctrl)(struct nvme_ctrl *ctrl);
	int (*get_address)(struct nvme_ctrl *ctrl, char *buf, int size);
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	int (*reinit_request)(void *data, struct request *rq);
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};

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static inline bool nvme_ctrl_ready(struct nvme_ctrl *ctrl)
{
	u32 val = 0;

	if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &val))
		return false;
	return val & NVME_CSTS_RDY;
}

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static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl)
{
	if (!ctrl->subsystem)
		return -ENOTTY;
	return ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65);
}

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static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector)
{
	return (sector >> (ns->lba_shift - 9));
}

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static inline void nvme_cleanup_cmd(struct request *req)
{
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	if (req->rq_flags & RQF_SPECIAL_PAYLOAD) {
		kfree(page_address(req->special_vec.bv_page) +
		      req->special_vec.bv_offset);
	}
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}

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static inline void nvme_end_request(struct request *req, __le16 status,
		union nvme_result result)
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{
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	struct nvme_request *rq = nvme_req(req);
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	rq->status = le16_to_cpu(status) >> 1;
	rq->result = result;
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	blk_mq_complete_request(req);
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}

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void nvme_complete_rq(struct request *req);
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void nvme_cancel_request(struct request *req, void *data, bool reserved);
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bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl,
		enum nvme_ctrl_state new_state);
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int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap);
int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap);
int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl);
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int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev,
		const struct nvme_ctrl_ops *ops, unsigned long quirks);
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void nvme_uninit_ctrl(struct nvme_ctrl *ctrl);
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void nvme_start_ctrl(struct nvme_ctrl *ctrl);
void nvme_stop_ctrl(struct nvme_ctrl *ctrl);
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void nvme_put_ctrl(struct nvme_ctrl *ctrl);
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int nvme_init_identify(struct nvme_ctrl *ctrl);
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void nvme_queue_scan(struct nvme_ctrl *ctrl);
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void nvme_remove_namespaces(struct nvme_ctrl *ctrl);
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int nvme_sec_submit(void *data, u16 spsp, u8 secp, void *buffer, size_t len,
		bool send);
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#define NVME_NR_AERS	1
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void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status,
		union nvme_result *res);
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void nvme_queue_async_events(struct nvme_ctrl *ctrl);

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void nvme_stop_queues(struct nvme_ctrl *ctrl);
void nvme_start_queues(struct nvme_ctrl *ctrl);
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void nvme_kill_queues(struct nvme_ctrl *ctrl);
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void nvme_unfreeze(struct nvme_ctrl *ctrl);
void nvme_wait_freeze(struct nvme_ctrl *ctrl);
void nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout);
void nvme_start_freeze(struct nvme_ctrl *ctrl);
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int nvme_reinit_tagset(struct nvme_ctrl *ctrl, struct blk_mq_tag_set *set);
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#define NVME_QID_ANY -1
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struct request *nvme_alloc_request(struct request_queue *q,
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		struct nvme_command *cmd, unsigned int flags, int qid);
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blk_status_t nvme_setup_cmd(struct nvme_ns *ns, struct request *req,
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		struct nvme_command *cmd);
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int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
		void *buf, unsigned bufflen);
int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
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		union nvme_result *result, void *buffer, unsigned bufflen,
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		unsigned timeout, int qid, int at_head, int flags);
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int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count);
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void nvme_start_keep_alive(struct nvme_ctrl *ctrl);
void nvme_stop_keep_alive(struct nvme_ctrl *ctrl);
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int nvme_reset_ctrl(struct nvme_ctrl *ctrl);
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#ifdef CONFIG_NVM
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int nvme_nvm_register(struct nvme_ns *ns, char *disk_name, int node);
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void nvme_nvm_unregister(struct nvme_ns *ns);
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int nvme_nvm_register_sysfs(struct nvme_ns *ns);
void nvme_nvm_unregister_sysfs(struct nvme_ns *ns);
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int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd, unsigned long arg);
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#else
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static inline int nvme_nvm_register(struct nvme_ns *ns, char *disk_name,
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				    int node)
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{
	return 0;
}

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static inline void nvme_nvm_unregister(struct nvme_ns *ns) {};
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static inline int nvme_nvm_register_sysfs(struct nvme_ns *ns)
{
	return 0;
}
static inline void nvme_nvm_unregister_sysfs(struct nvme_ns *ns) {};
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static inline int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd,
							unsigned long arg)
{
	return -ENOTTY;
}
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#endif /* CONFIG_NVM */

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static inline struct nvme_ns *nvme_get_ns_from_dev(struct device *dev)
{
	return dev_to_disk(dev)->private_data;
}
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int __init nvme_core_init(void);
void nvme_core_exit(void);

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#endif /* _NVME_H */