irq.c 3.92 KB
Newer Older
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
/*
 * arch/arm/mach-dove/irq.c
 *
 * Dove IRQ handling.
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/gpio.h>
#include <linux/io.h>
#include <asm/mach/arch.h>
#include <plat/irq.h>
#include <asm/mach/irq.h>
#include <mach/pm.h>
#include <mach/bridge-regs.h>
21
#include <plat/orion-gpio.h>
22 23
#include "common.h"

24
static void pmu_irq_mask(struct irq_data *d)
25
{
26
	int pin = irq_to_pmu(d->irq);
27 28 29 30 31 32 33
	u32 u;

	u = readl(PMU_INTERRUPT_MASK);
	u &= ~(1 << (pin & 31));
	writel(u, PMU_INTERRUPT_MASK);
}

34
static void pmu_irq_unmask(struct irq_data *d)
35
{
36
	int pin = irq_to_pmu(d->irq);
37 38 39 40 41 42 43
	u32 u;

	u = readl(PMU_INTERRUPT_MASK);
	u |= 1 << (pin & 31);
	writel(u, PMU_INTERRUPT_MASK);
}

44
static void pmu_irq_ack(struct irq_data *d)
45
{
46
	int pin = irq_to_pmu(d->irq);
47 48
	u32 u;

49 50 51 52 53 54 55 56 57 58 59
	/*
	 * The PMU mask register is not RW0C: it is RW.  This means that
	 * the bits take whatever value is written to them; if you write
	 * a '1', you will set the interrupt.
	 *
	 * Unfortunately this means there is NO race free way to clear
	 * these interrupts.
	 *
	 * So, let's structure the code so that the window is as small as
	 * possible.
	 */
60
	u = ~(1 << (pin & 31));
61 62
	u &= readl_relaxed(PMU_INTERRUPT_CAUSE);
	writel_relaxed(u, PMU_INTERRUPT_CAUSE);
63 64 65 66
}

static struct irq_chip pmu_irq_chip = {
	.name		= "pmu_irq",
67 68 69
	.irq_mask	= pmu_irq_mask,
	.irq_unmask	= pmu_irq_unmask,
	.irq_ack	= pmu_irq_ack,
70 71
};

72
static void pmu_irq_handler(struct irq_desc *desc)
73 74
{
	unsigned long cause = readl(PMU_INTERRUPT_CAUSE);
75
	unsigned int irq;
76 77 78

	cause &= readl(PMU_INTERRUPT_MASK);
	if (cause == 0) {
79
		do_bad_IRQ(desc);
80 81 82 83 84 85 86
		return;
	}

	for (irq = 0; irq < NR_PMU_IRQS; irq++) {
		if (!(cause & (1 << irq)))
			continue;
		irq = pmu_to_irq(irq);
87
		generic_handle_irq(irq);
88 89 90
	}
}

91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111
static int __initdata gpio0_irqs[4] = {
	IRQ_DOVE_GPIO_0_7,
	IRQ_DOVE_GPIO_8_15,
	IRQ_DOVE_GPIO_16_23,
	IRQ_DOVE_GPIO_24_31,
};

static int __initdata gpio1_irqs[4] = {
	IRQ_DOVE_HIGH_GPIO,
	0,
	0,
	0,
};

static int __initdata gpio2_irqs[4] = {
	0,
	0,
	0,
	0,
};

112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129
#ifdef CONFIG_MULTI_IRQ_HANDLER
/*
 * Compiling with both non-DT and DT support enabled, will
 * break asm irq handler used by non-DT boards. Therefore,
 * we provide a C-style irq handler even for non-DT boards,
 * if MULTI_IRQ_HANDLER is set.
 */

static void __iomem *dove_irq_base = IRQ_VIRT_BASE;

static asmlinkage void
__exception_irq_entry dove_legacy_handle_irq(struct pt_regs *regs)
{
	u32 stat;

	stat = readl_relaxed(dove_irq_base + IRQ_CAUSE_LOW_OFF);
	stat &= readl_relaxed(dove_irq_base + IRQ_MASK_LOW_OFF);
	if (stat) {
130
		unsigned int hwirq = 1 + __fls(stat);
131 132 133 134 135 136
		handle_IRQ(hwirq, regs);
		return;
	}
	stat = readl_relaxed(dove_irq_base + IRQ_CAUSE_HIGH_OFF);
	stat &= readl_relaxed(dove_irq_base + IRQ_MASK_HIGH_OFF);
	if (stat) {
137
		unsigned int hwirq = 33 + __fls(stat);
138 139 140 141 142 143
		handle_IRQ(hwirq, regs);
		return;
	}
}
#endif

144 145 146 147
void __init dove_init_irq(void)
{
	int i;

148 149
	orion_irq_init(1, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
	orion_irq_init(33, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
150

151 152 153 154
#ifdef CONFIG_MULTI_IRQ_HANDLER
	set_handle_irq(dove_legacy_handle_irq);
#endif

155
	/*
156
	 * Initialize gpiolib for GPIOs 0-71.
157
	 */
158
	orion_gpio_init(NULL, 0, 32, DOVE_GPIO_LO_VIRT_BASE, 0,
159 160
			IRQ_DOVE_GPIO_START, gpio0_irqs);

161
	orion_gpio_init(NULL, 32, 32, DOVE_GPIO_HI_VIRT_BASE, 0,
162 163
			IRQ_DOVE_GPIO_START + 32, gpio1_irqs);

164
	orion_gpio_init(NULL, 64, 8, DOVE_GPIO2_VIRT_BASE, 0,
165
			IRQ_DOVE_GPIO_START + 64, gpio2_irqs);
166 167 168 169 170 171 172 173

	/*
	 * Mask and clear PMU interrupts
	 */
	writel(0, PMU_INTERRUPT_MASK);
	writel(0, PMU_INTERRUPT_CAUSE);

	for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) {
174
		irq_set_chip_and_handler(i, &pmu_irq_chip, handle_level_irq);
175
		irq_set_status_flags(i, IRQ_LEVEL);
176
		irq_clear_status_flags(i, IRQ_NOREQUEST);
177
	}
178
	irq_set_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler);
179
}