hda_intel.c 74.9 KB
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/*
 *
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 *  hda_intel.c - Implementation of primary alsa driver code base
 *                for Intel HD Audio.
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 *
 *  Copyright(c) 2004 Intel Corporation. All rights reserved.
 *
 *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
 *                     PeiSen Hou <pshou@realtek.com.tw>
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License as published by the Free
 *  Software Foundation; either version 2 of the License, or (at your option)
 *  any later version.
 *
 *  This program is distributed in the hope that it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 *  more details.
 *
 *  You should have received a copy of the GNU General Public License along with
 *  this program; if not, write to the Free Software Foundation, Inc., 59
 *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
 *
 *  CONTACTS:
 *
 *  Matt Jared		matt.jared@intel.com
 *  Andy Kopp		andy.kopp@intel.com
 *  Dan Kogan		dan.d.kogan@intel.com
 *
 *  CHANGES:
 *
 *  2004.12.01	Major rewrite by tiwai, merged the work of pshou
 * 
 */

#include <linux/delay.h>
#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/dma-mapping.h>
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#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/pci.h>
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#include <linux/mutex.h>
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#include <linux/io.h>
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#include <linux/pm_runtime.h>
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#include <linux/clocksource.h>
#include <linux/time.h>
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#include <linux/completion.h>
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#ifdef CONFIG_X86
/* for snoop control */
#include <asm/pgtable.h>
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#include <asm/set_memory.h>
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#include <asm/cpufeature.h>
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#endif
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#include <sound/core.h>
#include <sound/initval.h>
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#include <sound/hdaudio.h>
#include <sound/hda_i915.h>
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#include <linux/vgaarb.h>
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#include <linux/vga_switcheroo.h>
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#include <linux/firmware.h>
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#include <sound/hda_codec.h>
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#include "hda_controller.h"
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#include "hda_intel.h"
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#define CREATE_TRACE_POINTS
#include "hda_intel_trace.h"

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/* position fix mode */
enum {
	POS_FIX_AUTO,
	POS_FIX_LPIB,
	POS_FIX_POSBUF,
	POS_FIX_VIACOMBO,
	POS_FIX_COMBO,
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	POS_FIX_SKL,
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};

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/* Defines for ATI HD Audio support in SB450 south bridge */
#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
#define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02

/* Defines for Nvidia HDA support */
#define NVIDIA_HDA_TRANSREG_ADDR      0x4e
#define NVIDIA_HDA_ENABLE_COHBITS     0x0f
#define NVIDIA_HDA_ISTRM_COH          0x4d
#define NVIDIA_HDA_OSTRM_COH          0x4c
#define NVIDIA_HDA_ENABLE_COHBIT      0x01

/* Defines for Intel SCH HDA snoop control */
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#define INTEL_HDA_CGCTL	 0x48
#define INTEL_HDA_CGCTL_MISCBDCGE        (0x1 << 6)
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#define INTEL_SCH_HDA_DEVC      0x78
#define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)

/* Define IN stream 0 FIFO size offset in VIA controller */
#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET	0x90
/* Define VIA HD Audio Device ID*/
#define VIA_HDAC_DEVICE_ID		0x3288

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/* max number of SDs */
/* ICH, ATI and VIA have 4 playback and 4 capture */
#define ICH6_NUM_CAPTURE	4
#define ICH6_NUM_PLAYBACK	4

/* ULI has 6 playback and 5 capture */
#define ULI_NUM_CAPTURE		5
#define ULI_NUM_PLAYBACK	6

/* ATI HDMI may have up to 8 playbacks and 0 capture */
#define ATIHDMI_NUM_CAPTURE	0
#define ATIHDMI_NUM_PLAYBACK	8

/* TERA has 4 playback and 3 capture */
#define TERA_NUM_CAPTURE	3
#define TERA_NUM_PLAYBACK	4

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static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
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static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
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static char *model[SNDRV_CARDS];
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static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
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static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
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static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
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static int probe_only[SNDRV_CARDS];
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static int jackpoll_ms[SNDRV_CARDS];
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static int single_cmd = -1;
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static int enable_msi = -1;
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#ifdef CONFIG_SND_HDA_PATCH_LOADER
static char *patch[SNDRV_CARDS];
#endif
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#ifdef CONFIG_SND_HDA_INPUT_BEEP
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static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
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					CONFIG_SND_HDA_INPUT_BEEP_MODE};
#endif
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module_param_array(index, int, NULL, 0444);
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MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
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module_param_array(id, charp, NULL, 0444);
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MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
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module_param_array(enable, bool, NULL, 0444);
MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
module_param_array(model, charp, NULL, 0444);
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MODULE_PARM_DESC(model, "Use the given board model.");
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module_param_array(position_fix, int, NULL, 0444);
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MODULE_PARM_DESC(position_fix, "DMA pointer read method."
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		 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+).");
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module_param_array(bdl_pos_adj, int, NULL, 0644);
MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
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module_param_array(probe_mask, int, NULL, 0444);
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MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
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module_param_array(probe_only, int, NULL, 0444);
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MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
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module_param_array(jackpoll_ms, int, NULL, 0444);
MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
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module_param(single_cmd, bint, 0444);
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MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
		 "(for debugging only).");
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module_param(enable_msi, bint, 0444);
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MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
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#ifdef CONFIG_SND_HDA_PATCH_LOADER
module_param_array(patch, charp, NULL, 0444);
MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
#endif
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#ifdef CONFIG_SND_HDA_INPUT_BEEP
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module_param_array(beep_mode, bool, NULL, 0444);
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MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
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			    "(0=off, 1=on) (default=1).");
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#endif
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#ifdef CONFIG_PM
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static int param_set_xint(const char *val, const struct kernel_param *kp);
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static const struct kernel_param_ops param_ops_xint = {
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	.set = param_set_xint,
	.get = param_get_int,
};
#define param_check_xint param_check_int

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static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
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module_param(power_save, xint, 0644);
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MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
		 "(in second, 0 = disable).");
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static bool pm_blacklist = true;
module_param(pm_blacklist, bool, 0644);
MODULE_PARM_DESC(pm_blacklist, "Enable power-management blacklist");

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/* reset the HD-audio controller in power save mode.
 * this may give more power-saving, but will take longer time to
 * wake up.
 */
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static bool power_save_controller = 1;
module_param(power_save_controller, bool, 0644);
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MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
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#else
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#define power_save	0
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#endif /* CONFIG_PM */
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static int align_buffer_size = -1;
module_param(align_buffer_size, bint, 0644);
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MODULE_PARM_DESC(align_buffer_size,
		"Force buffer and period sizes to be multiple of 128 bytes.");

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#ifdef CONFIG_X86
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static int hda_snoop = -1;
module_param_named(snoop, hda_snoop, bint, 0444);
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MODULE_PARM_DESC(snoop, "Enable/disable snooping");
#else
#define hda_snoop		true
#endif


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MODULE_LICENSE("GPL");
MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
			 "{Intel, ICH6M},"
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			 "{Intel, ICH7},"
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			 "{Intel, ESB2},"
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			 "{Intel, ICH8},"
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			 "{Intel, ICH9},"
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			 "{Intel, ICH10},"
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			 "{Intel, PCH},"
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			 "{Intel, CPT},"
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			 "{Intel, PPT},"
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			 "{Intel, LPT},"
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			 "{Intel, LPT_LP},"
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			 "{Intel, WPT_LP},"
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			 "{Intel, SPT},"
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			 "{Intel, SPT_LP},"
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			 "{Intel, HPT},"
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			 "{Intel, PBG},"
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			 "{Intel, SCH},"
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			 "{ATI, SB450},"
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			 "{ATI, SB600},"
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			 "{ATI, RS600},"
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			 "{ATI, RS690},"
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			 "{ATI, RS780},"
			 "{ATI, R600},"
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			 "{ATI, RV630},"
			 "{ATI, RV610},"
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			 "{ATI, RV670},"
			 "{ATI, RV635},"
			 "{ATI, RV620},"
			 "{ATI, RV770},"
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			 "{VIA, VT8251},"
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			 "{VIA, VT8237A},"
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			 "{SiS, SIS966},"
			 "{ULI, M5461}}");
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MODULE_DESCRIPTION("Intel HDA driver");

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#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
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#if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
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#define SUPPORT_VGA_SWITCHEROO
#endif
#endif


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/*
 */

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/* driver types */
enum {
	AZX_DRIVER_ICH,
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	AZX_DRIVER_PCH,
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	AZX_DRIVER_SCH,
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	AZX_DRIVER_SKL,
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	AZX_DRIVER_HDMI,
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	AZX_DRIVER_ATI,
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	AZX_DRIVER_ATIHDMI,
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	AZX_DRIVER_ATIHDMI_NS,
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	AZX_DRIVER_VIA,
	AZX_DRIVER_SIS,
	AZX_DRIVER_ULI,
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	AZX_DRIVER_NVIDIA,
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	AZX_DRIVER_TERA,
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	AZX_DRIVER_CTX,
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	AZX_DRIVER_CTHDA,
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	AZX_DRIVER_CMEDIA,
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	AZX_DRIVER_GENERIC,
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	AZX_NUM_DRIVERS, /* keep this as last entry */
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};

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#define azx_get_snoop_type(chip) \
	(((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
#define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)

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/* quirks for old Intel chipsets */
#define AZX_DCAPS_INTEL_ICH \
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	(AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
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/* quirks for Intel PCH */
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#define AZX_DCAPS_INTEL_PCH_BASE \
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	(AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
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	 AZX_DCAPS_SNOOP_TYPE(SCH))
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/* PCH up to IVB; no runtime PM; bind with i915 gfx */
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#define AZX_DCAPS_INTEL_PCH_NOPM \
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	(AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
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/* PCH for HSW/BDW; with runtime PM */
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/* no i915 binding for this as HSW/BDW has another controller for HDMI */
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#define AZX_DCAPS_INTEL_PCH \
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	(AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
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/* HSW HDMI */
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#define AZX_DCAPS_INTEL_HASWELL \
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	(/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
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	 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
	 AZX_DCAPS_I915_POWERWELL | AZX_DCAPS_SNOOP_TYPE(SCH))
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/* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
#define AZX_DCAPS_INTEL_BROADWELL \
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	(/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
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	 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
	 AZX_DCAPS_I915_POWERWELL | AZX_DCAPS_SNOOP_TYPE(SCH))
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#define AZX_DCAPS_INTEL_BAYTRAIL \
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	(AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT |\
	 AZX_DCAPS_I915_POWERWELL)
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#define AZX_DCAPS_INTEL_BRASWELL \
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	(AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
	 AZX_DCAPS_I915_COMPONENT | AZX_DCAPS_I915_POWERWELL)
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#define AZX_DCAPS_INTEL_SKYLAKE \
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	(AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
	 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT |\
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	 AZX_DCAPS_I915_POWERWELL)
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#define AZX_DCAPS_INTEL_BROXTON \
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	(AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
	 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT |\
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	 AZX_DCAPS_I915_POWERWELL)

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/* quirks for ATI SB / AMD Hudson */
#define AZX_DCAPS_PRESET_ATI_SB \
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	(AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
	 AZX_DCAPS_SNOOP_TYPE(ATI))
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/* quirks for ATI/AMD HDMI */
#define AZX_DCAPS_PRESET_ATI_HDMI \
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	(AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
	 AZX_DCAPS_NO_MSI64)
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/* quirks for ATI HDMI with snoop off */
#define AZX_DCAPS_PRESET_ATI_HDMI_NS \
	(AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)

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/* quirks for Nvidia */
#define AZX_DCAPS_PRESET_NVIDIA \
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	(AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
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	 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
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#define AZX_DCAPS_PRESET_CTHDA \
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	(AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
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	 AZX_DCAPS_NO_64BIT |\
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	 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
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/*
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 * vga_switcheroo support
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 */
#ifdef SUPPORT_VGA_SWITCHEROO
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#define use_vga_switcheroo(chip)	((chip)->use_vga_switcheroo)
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#define needs_eld_notify_link(chip)	((chip)->need_eld_notify_link)
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#else
#define use_vga_switcheroo(chip)	0
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#define needs_eld_notify_link(chip)	false
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#endif

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#define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
					((pci)->device == 0x0c0c) || \
					((pci)->device == 0x0d0c) || \
					((pci)->device == 0x160c))

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#define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
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#define IS_CFL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa348)
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static char *driver_short_names[] = {
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	[AZX_DRIVER_ICH] = "HDA Intel",
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	[AZX_DRIVER_PCH] = "HDA Intel PCH",
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	[AZX_DRIVER_SCH] = "HDA Intel MID",
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	[AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
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	[AZX_DRIVER_HDMI] = "HDA Intel HDMI",
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	[AZX_DRIVER_ATI] = "HDA ATI SB",
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	[AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
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	[AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
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	[AZX_DRIVER_VIA] = "HDA VIA VT82xx",
	[AZX_DRIVER_SIS] = "HDA SIS966",
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	[AZX_DRIVER_ULI] = "HDA ULI M5461",
	[AZX_DRIVER_NVIDIA] = "HDA NVidia",
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	[AZX_DRIVER_TERA] = "HDA Teradici", 
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	[AZX_DRIVER_CTX] = "HDA Creative", 
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	[AZX_DRIVER_CTHDA] = "HDA Creative",
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	[AZX_DRIVER_CMEDIA] = "HDA C-Media",
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	[AZX_DRIVER_GENERIC] = "HD-Audio Generic",
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};

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static int azx_acquire_irq(struct azx *chip, int do_disconnect);
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static void set_default_power_save(struct azx *chip);
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/*
 * initialize the PCI registers
 */
/* update bits in a PCI register byte */
static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
			    unsigned char mask, unsigned char val)
{
	unsigned char data;

	pci_read_config_byte(pci, reg, &data);
	data &= ~mask;
	data |= (val & mask);
	pci_write_config_byte(pci, reg, data);
}

static void azx_init_pci(struct azx *chip)
{
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	int snoop_type = azx_get_snoop_type(chip);

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	/* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
	 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
	 * Ensuring these bits are 0 clears playback static on some HD Audio
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	 * codecs.
	 * The PCI register TCSEL is defined in the Intel manuals.
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	 */
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	if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
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		dev_dbg(chip->card->dev, "Clearing TCSEL\n");
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		update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
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	}
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	/* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
	 * we need to enable snoop.
	 */
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	if (snoop_type == AZX_SNOOP_TYPE_ATI) {
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		dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
			azx_snoop(chip));
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		update_pci_byte(chip->pci,
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				ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
				azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
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	}

	/* For NVIDIA HDA, enable snoop */
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	if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
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		dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
			azx_snoop(chip));
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		update_pci_byte(chip->pci,
				NVIDIA_HDA_TRANSREG_ADDR,
				0x0f, NVIDIA_HDA_ENABLE_COHBITS);
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		update_pci_byte(chip->pci,
				NVIDIA_HDA_ISTRM_COH,
				0x01, NVIDIA_HDA_ENABLE_COHBIT);
		update_pci_byte(chip->pci,
				NVIDIA_HDA_OSTRM_COH,
				0x01, NVIDIA_HDA_ENABLE_COHBIT);
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	}

	/* Enable SCH/PCH snoop if needed */
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	if (snoop_type == AZX_SNOOP_TYPE_SCH) {
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		unsigned short snoop;
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		pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
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		if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
		    (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
			snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
			if (!azx_snoop(chip))
				snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
			pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
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			pci_read_config_word(chip->pci,
				INTEL_SCH_HDA_DEVC, &snoop);
		}
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		dev_dbg(chip->card->dev, "SCH snoop: %s\n",
			(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
			"Disabled" : "Enabled");
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        }
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}

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/*
 * In BXT-P A0, HD-Audio DMA requests is later than expected,
 * and makes an audio stream sensitive to system latencies when
 * 24/32 bits are playing.
 * Adjusting threshold of DMA fifo to force the DMA request
 * sooner to improve latency tolerance at the expense of power.
 */
static void bxt_reduce_dma_latency(struct azx *chip)
{
	u32 val;

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	val = azx_readl(chip, VS_EM4L);
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	val &= (0x3 << 20);
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	azx_writel(chip, VS_EM4L, val);
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}

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/*
 * ML_LCAP bits:
 *  bit 0: 6 MHz Supported
 *  bit 1: 12 MHz Supported
 *  bit 2: 24 MHz Supported
 *  bit 3: 48 MHz Supported
 *  bit 4: 96 MHz Supported
 *  bit 5: 192 MHz Supported
 */
static int intel_get_lctl_scf(struct azx *chip)
{
	struct hdac_bus *bus = azx_bus(chip);
	static int preferred_bits[] = { 2, 3, 1, 4, 5 };
	u32 val, t;
	int i;

	val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);

	for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
		t = preferred_bits[i];
		if (val & (1 << t))
			return t;
	}

	dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
	return 0;
}

static int intel_ml_lctl_set_power(struct azx *chip, int state)
{
	struct hdac_bus *bus = azx_bus(chip);
	u32 val;
	int timeout;

	/*
	 * the codecs are sharing the first link setting by default
	 * If other links are enabled for stream, they need similar fix
	 */
	val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
	val &= ~AZX_MLCTL_SPA;
	val |= state << AZX_MLCTL_SPA_SHIFT;
	writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
	/* wait for CPA */
	timeout = 50;
	while (timeout) {
		if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
		    AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
			return 0;
		timeout--;
		udelay(10);
	}

	return -1;
}

static void intel_init_lctl(struct azx *chip)
{
	struct hdac_bus *bus = azx_bus(chip);
	u32 val;
	int ret;

	/* 0. check lctl register value is correct or not */
	val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
	/* if SCF is already set, let's use it */
	if ((val & ML_LCTL_SCF_MASK) != 0)
		return;

	/*
	 * Before operating on SPA, CPA must match SPA.
	 * Any deviation may result in undefined behavior.
	 */
	if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
		((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
		return;

	/* 1. turn link down: set SPA to 0 and wait CPA to 0 */
	ret = intel_ml_lctl_set_power(chip, 0);
	udelay(100);
	if (ret)
		goto set_spa;

	/* 2. update SCF to select a properly audio clock*/
	val &= ~ML_LCTL_SCF_MASK;
	val |= intel_get_lctl_scf(chip);
	writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);

set_spa:
	/* 4. turn link up: set SPA to 1 and wait CPA to 1 */
	intel_ml_lctl_set_power(chip, 1);
	udelay(100);
}

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static void hda_intel_init_chip(struct azx *chip, bool full_reset)
{
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	struct hdac_bus *bus = azx_bus(chip);
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	struct pci_dev *pci = chip->pci;
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	u32 val;
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	if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
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		snd_hdac_set_codec_wakeup(bus, true);
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	if (chip->driver_type == AZX_DRIVER_SKL) {
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		pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
		val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
		pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
	}
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	azx_init_chip(chip, full_reset);
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	if (chip->driver_type == AZX_DRIVER_SKL) {
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		pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
		val = val | INTEL_HDA_CGCTL_MISCBDCGE;
		pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
	}
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	if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
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		snd_hdac_set_codec_wakeup(bus, false);
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	/* reduce dma latency to avoid noise */
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	if (IS_BXT(pci))
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		bxt_reduce_dma_latency(chip);
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	if (bus->mlcap != NULL)
		intel_init_lctl(chip);
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}

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/* calculate runtime delay from LPIB */
static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
				   unsigned int pos)
{
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	struct snd_pcm_substream *substream = azx_dev->core.substream;
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	int stream = substream->stream;
	unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
	int delay;

	if (stream == SNDRV_PCM_STREAM_PLAYBACK)
		delay = pos - lpib_pos;
	else
		delay = lpib_pos - pos;
	if (delay < 0) {
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		if (delay >= azx_dev->core.delay_negative_threshold)
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			delay = 0;
		else
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			delay += azx_dev->core.bufsize;
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	}

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	if (delay >= azx_dev->core.period_bytes) {
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		dev_info(chip->card->dev,
			 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
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			 delay, azx_dev->core.period_bytes);
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		delay = 0;
		chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
		chip->get_delay[stream] = NULL;
	}

	return bytes_to_frames(substream->runtime, delay);
}

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static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);

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/* called from IRQ */
static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
{
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	struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
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	int ok;

	ok = azx_position_ok(chip, azx_dev);
	if (ok == 1) {
		azx_dev->irq_pending = 0;
		return ok;
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	} else if (ok == 0) {
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		/* bogus IRQ, process it later */
		azx_dev->irq_pending = 1;
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		schedule_work(&hda->irq_pending_work);
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	}
	return 0;
}

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/* Enable/disable i915 display power for the link */
static int azx_intel_link_power(struct azx *chip, bool enable)
{
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	struct hdac_bus *bus = azx_bus(chip);
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	return snd_hdac_display_power(bus, enable);
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}

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/*
 * Check whether the current DMA position is acceptable for updating
 * periods.  Returns non-zero if it's OK.
 *
 * Many HD-audio controllers appear pretty inaccurate about
 * the update-IRQ timing.  The IRQ is issued before actually the
 * data is processed.  So, we need to process it afterwords in a
 * workqueue.
 */
static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
{
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	struct snd_pcm_substream *substream = azx_dev->core.substream;
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	int stream = substream->stream;
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	u32 wallclk;
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	unsigned int pos;

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	wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
	if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
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		return -1;	/* bogus (too early) interrupt */

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	if (chip->get_position[stream])
		pos = chip->get_position[stream](chip, azx_dev);
	else { /* use the position buffer as default */
		pos = azx_get_pos_posbuf(chip, azx_dev);
		if (!pos || pos == (u32)-1) {
			dev_info(chip->card->dev,
				 "Invalid position buffer, using LPIB read method instead.\n");
			chip->get_position[stream] = azx_get_pos_lpib;
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			if (chip->get_position[0] == azx_get_pos_lpib &&
			    chip->get_position[1] == azx_get_pos_lpib)
				azx_bus(chip)->use_posbuf = false;
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			pos = azx_get_pos_lpib(chip, azx_dev);
			chip->get_delay[stream] = NULL;
		} else {
			chip->get_position[stream] = azx_get_pos_posbuf;
			if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
				chip->get_delay[stream] = azx_get_delay_from_lpib;
		}
	}

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	if (pos >= azx_dev->core.bufsize)
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		pos = 0;
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	if (WARN_ONCE(!azx_dev->core.period_bytes,
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		      "hda-intel: zero azx_dev->period_bytes"))
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		return -1; /* this shouldn't happen! */
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	if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
	    pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
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		/* NG - it's below the first next period boundary */
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		return chip->bdl_pos_adj ? 0 : -1;
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	azx_dev->core.start_wallclk += wallclk;
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	return 1; /* OK, it's fine */
}

/*
 * The work for pending PCM period updates.
 */
static void azx_irq_pending_work(struct work_struct *work)
{
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	struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
	struct azx *chip = &hda->chip;
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	struct hdac_bus *bus = azx_bus(chip);
	struct hdac_stream *s;
	int pending, ok;
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	if (!hda->irq_pending_warned) {
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		dev_info(chip->card->dev,
			 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
			 chip->card->number);
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		hda->irq_pending_warned = 1;
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	}

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	for (;;) {
		pending = 0;
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		spin_lock_irq(&bus->reg_lock);
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		list_for_each_entry(s, &bus->stream_list, list) {
			struct azx_dev *azx_dev = stream_to_azx_dev(s);
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			if (!azx_dev->irq_pending ||
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			    !s->substream ||
			    !s->running)
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				continue;
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			ok = azx_position_ok(chip, azx_dev);
			if (ok > 0) {
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				azx_dev->irq_pending = 0;
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				spin_unlock(&bus->reg_lock);
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				snd_pcm_period_elapsed(s->substream);
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				spin_lock(&bus->reg_lock);
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			} else if (ok < 0) {
				pending = 0;	/* too early */
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			} else
				pending++;
		}
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		spin_unlock_irq(&bus->reg_lock);
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		if (!pending)
			return;
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		msleep(1);
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	}
}

/* clear irq_pending flags and assure no on-going workq */
static void azx_clear_irq_pending(struct azx *chip)
{
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	struct hdac_bus *bus = azx_bus(chip);
	struct hdac_stream *s;
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	spin_lock_irq(&bus->reg_lock);
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	list_for_each_entry(s, &bus->stream_list, list) {
		struct azx_dev *azx_dev = stream_to_azx_dev(s);
		azx_dev->irq_pending = 0;
	}
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	spin_unlock_irq(&bus->reg_lock);
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}

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static int azx_acquire_irq(struct azx *chip, int do_disconnect)
{
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	struct hdac_bus *bus = azx_bus(chip);

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	if (request_irq(chip->pci->irq, azx_interrupt,
			chip->msi ? 0 : IRQF_SHARED,
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			chip->card->irq_descr, chip)) {
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		dev_err(chip->card->dev,
			"unable to grab IRQ %d, disabling device\n",
			chip->pci->irq);
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		if (do_disconnect)
			snd_card_disconnect(chip->card);
		return -1;
	}
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	bus->irq = chip->pci->irq;
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	pci_intx(chip->pci, !chip->msi);
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	return 0;
}

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/* get the current DMA position with correction on VIA chips */
static unsigned int azx_via_get_position(struct azx *chip,
					 struct azx_dev *azx_dev)
{
	unsigned int link_pos, mini_pos, bound_pos;
	unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
	unsigned int fifo_size;

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	link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
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	if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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		/* Playback, no problem using link position */
		return link_pos;
	}

	/* Capture */
	/* For new chipset,
	 * use mod to get the DMA position just like old chipset
	 */
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	mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
	mod_dma_pos %= azx_dev->core.period_bytes;
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	/* azx_dev->fifo_size can't get FIFO size of in stream.
	 * Get from base address + offset.
	 */
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	fifo_size = readw(azx_bus(chip)->remap_addr +
			  VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
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	if (azx_dev->insufficient) {
		/* Link position never gather than FIFO size */
		if (link_pos <= fifo_size)
			return 0;

		azx_dev->insufficient = 0;
	}

	if (link_pos <= fifo_size)
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		mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
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	else
		mini_pos = link_pos - fifo_size;

	/* Find nearest previous boudary */
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	mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
	mod_link_pos = link_pos % azx_dev->core.period_bytes;
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	if (mod_link_pos >= fifo_size)
		bound_pos = link_pos - mod_link_pos;
	else if (mod_dma_pos >= mod_mini_pos)
		bound_pos = mini_pos - mod_mini_pos;
	else {
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		bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
		if (bound_pos >= azx_dev->core.bufsize)
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			bound_pos = 0;
	}

	/* Calculate real DMA position we want */
	return bound_pos + mod_dma_pos;
}

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static unsigned int azx_skl_get_dpib_pos(struct azx *chip,
					 struct azx_dev *azx_dev)
{
	return _snd_hdac_chip_readl(azx_bus(chip),
				    AZX_REG_VS_SDXDPIB_XBASE +
				    (AZX_REG_VS_SDXDPIB_XINTERVAL *
				     azx_dev->core.index));
}

/* get the current DMA position with correction on SKL+ chips */
static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev)
{
	/* DPIB register gives a more accurate position for playback */
	if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		return azx_skl_get_dpib_pos(chip, azx_dev);

	/* For capture, we need to read posbuf, but it requires a delay
	 * for the possible boundary overlap; the read of DPIB fetches the
	 * actual posbuf
	 */
	udelay(20);
	azx_skl_get_dpib_pos(chip, azx_dev);
	return azx_get_pos_posbuf(chip, azx_dev);
}

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#ifdef CONFIG_PM
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static DEFINE_MUTEX(card_list_lock);
static LIST_HEAD(card_list);

static void azx_add_card_list(struct azx *chip)
{
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	struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
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	mutex_lock(&card_list_lock);
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	list_add(&hda->list, &card_list);
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	mutex_unlock(&card_list_lock);
}

static void azx_del_card_list(struct azx *chip)
{