gtt.c 59.9 KB
Newer Older
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
/*
 * GTT virtualization
 *
 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 *
 * Authors:
 *    Zhi Wang <zhi.a.wang@intel.com>
 *    Zhenyu Wang <zhenyuw@linux.intel.com>
 *    Xiao Zheng <xiao.zheng@intel.com>
 *
 * Contributors:
 *    Min He <min.he@intel.com>
 *    Bing Niu <bing.niu@intel.com>
 *
 */

#include "i915_drv.h"
37 38
#include "gvt.h"
#include "i915_pvinfo.h"
39 40
#include "trace.h"

41 42 43 44 45 46
#if defined(VERBOSE_DEBUG)
#define gvt_vdbg_mm(fmt, args...) gvt_dbg_mm(fmt, ##args)
#else
#define gvt_vdbg_mm(fmt, args...)
#endif

47 48 49 50 51 52 53 54 55 56 57
static bool enable_out_of_sync = false;
static int preallocated_oos_pages = 8192;

/*
 * validate a gm address and related range size,
 * translate it to host gm address
 */
bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size)
{
	if ((!vgpu_gmadr_is_valid(vgpu, addr)) || (size
			&& !vgpu_gmadr_is_valid(vgpu, addr + size - 1))) {
58 59
		gvt_vgpu_err("invalid range gmadr 0x%llx size 0x%x\n",
				addr, size);
60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102
		return false;
	}
	return true;
}

/* translate a guest gmadr to host gmadr */
int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr)
{
	if (WARN(!vgpu_gmadr_is_valid(vgpu, g_addr),
		 "invalid guest gmadr %llx\n", g_addr))
		return -EACCES;

	if (vgpu_gmadr_is_aperture(vgpu, g_addr))
		*h_addr = vgpu_aperture_gmadr_base(vgpu)
			  + (g_addr - vgpu_aperture_offset(vgpu));
	else
		*h_addr = vgpu_hidden_gmadr_base(vgpu)
			  + (g_addr - vgpu_hidden_offset(vgpu));
	return 0;
}

/* translate a host gmadr to guest gmadr */
int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr)
{
	if (WARN(!gvt_gmadr_is_valid(vgpu->gvt, h_addr),
		 "invalid host gmadr %llx\n", h_addr))
		return -EACCES;

	if (gvt_gmadr_is_aperture(vgpu->gvt, h_addr))
		*g_addr = vgpu_aperture_gmadr_base(vgpu)
			+ (h_addr - gvt_aperture_gmadr_base(vgpu->gvt));
	else
		*g_addr = vgpu_hidden_gmadr_base(vgpu)
			+ (h_addr - gvt_hidden_gmadr_base(vgpu->gvt));
	return 0;
}

int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu, unsigned long g_index,
			     unsigned long *h_index)
{
	u64 h_addr;
	int ret;

103
	ret = intel_gvt_ggtt_gmadr_g2h(vgpu, g_index << I915_GTT_PAGE_SHIFT,
104 105 106 107
				       &h_addr);
	if (ret)
		return ret;

108
	*h_index = h_addr >> I915_GTT_PAGE_SHIFT;
109 110 111 112 113 114 115 116 117
	return 0;
}

int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index,
			     unsigned long *g_index)
{
	u64 g_addr;
	int ret;

118
	ret = intel_gvt_ggtt_gmadr_h2g(vgpu, h_index << I915_GTT_PAGE_SHIFT,
119 120 121 122
				       &g_addr);
	if (ret)
		return ret;

123
	*g_index = g_addr >> I915_GTT_PAGE_SHIFT;
124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164
	return 0;
}

#define gtt_type_is_entry(type) \
	(type > GTT_TYPE_INVALID && type < GTT_TYPE_PPGTT_ENTRY \
	 && type != GTT_TYPE_PPGTT_PTE_ENTRY \
	 && type != GTT_TYPE_PPGTT_ROOT_ENTRY)

#define gtt_type_is_pt(type) \
	(type >= GTT_TYPE_PPGTT_PTE_PT && type < GTT_TYPE_MAX)

#define gtt_type_is_pte_pt(type) \
	(type == GTT_TYPE_PPGTT_PTE_PT)

#define gtt_type_is_root_pointer(type) \
	(gtt_type_is_entry(type) && type > GTT_TYPE_PPGTT_ROOT_ENTRY)

#define gtt_init_entry(e, t, p, v) do { \
	(e)->type = t; \
	(e)->pdev = p; \
	memcpy(&(e)->val64, &v, sizeof(v)); \
} while (0)

/*
 * Mappings between GTT_TYPE* enumerations.
 * Following information can be found according to the given type:
 * - type of next level page table
 * - type of entry inside this level page table
 * - type of entry with PSE set
 *
 * If the given type doesn't have such a kind of information,
 * e.g. give a l4 root entry type, then request to get its PSE type,
 * give a PTE page table type, then request to get its next level page
 * table type, as we know l4 root entry doesn't have a PSE bit,
 * and a PTE page table doesn't have a next level page table type,
 * GTT_TYPE_INVALID will be returned. This is useful when traversing a
 * page table.
 */

struct gtt_type_table_entry {
	int entry_type;
165
	int pt_type;
166 167 168 169
	int next_pt_type;
	int pse_entry_type;
};

170
#define GTT_TYPE_TABLE_ENTRY(type, e_type, cpt_type, npt_type, pse_type) \
171 172
	[type] = { \
		.entry_type = e_type, \
173
		.pt_type = cpt_type, \
174 175 176 177 178 179 180
		.next_pt_type = npt_type, \
		.pse_entry_type = pse_type, \
	}

static struct gtt_type_table_entry gtt_type_table[] = {
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_ROOT_L4_ENTRY,
			GTT_TYPE_PPGTT_ROOT_L4_ENTRY,
181
			GTT_TYPE_INVALID,
182 183 184 185
			GTT_TYPE_PPGTT_PML4_PT,
			GTT_TYPE_INVALID),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PML4_PT,
			GTT_TYPE_PPGTT_PML4_ENTRY,
186
			GTT_TYPE_PPGTT_PML4_PT,
187 188 189 190
			GTT_TYPE_PPGTT_PDP_PT,
			GTT_TYPE_INVALID),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PML4_ENTRY,
			GTT_TYPE_PPGTT_PML4_ENTRY,
191
			GTT_TYPE_PPGTT_PML4_PT,
192 193 194 195
			GTT_TYPE_PPGTT_PDP_PT,
			GTT_TYPE_INVALID),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDP_PT,
			GTT_TYPE_PPGTT_PDP_ENTRY,
196
			GTT_TYPE_PPGTT_PDP_PT,
197 198 199 200
			GTT_TYPE_PPGTT_PDE_PT,
			GTT_TYPE_PPGTT_PTE_1G_ENTRY),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_ROOT_L3_ENTRY,
			GTT_TYPE_PPGTT_ROOT_L3_ENTRY,
201
			GTT_TYPE_INVALID,
202 203 204 205
			GTT_TYPE_PPGTT_PDE_PT,
			GTT_TYPE_PPGTT_PTE_1G_ENTRY),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDP_ENTRY,
			GTT_TYPE_PPGTT_PDP_ENTRY,
206
			GTT_TYPE_PPGTT_PDP_PT,
207 208 209 210
			GTT_TYPE_PPGTT_PDE_PT,
			GTT_TYPE_PPGTT_PTE_1G_ENTRY),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDE_PT,
			GTT_TYPE_PPGTT_PDE_ENTRY,
211
			GTT_TYPE_PPGTT_PDE_PT,
212 213 214 215
			GTT_TYPE_PPGTT_PTE_PT,
			GTT_TYPE_PPGTT_PTE_2M_ENTRY),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDE_ENTRY,
			GTT_TYPE_PPGTT_PDE_ENTRY,
216
			GTT_TYPE_PPGTT_PDE_PT,
217 218 219 220
			GTT_TYPE_PPGTT_PTE_PT,
			GTT_TYPE_PPGTT_PTE_2M_ENTRY),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_PT,
			GTT_TYPE_PPGTT_PTE_4K_ENTRY,
221
			GTT_TYPE_PPGTT_PTE_PT,
222 223 224 225
			GTT_TYPE_INVALID,
			GTT_TYPE_INVALID),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_4K_ENTRY,
			GTT_TYPE_PPGTT_PTE_4K_ENTRY,
226
			GTT_TYPE_PPGTT_PTE_PT,
227 228 229 230
			GTT_TYPE_INVALID,
			GTT_TYPE_INVALID),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_2M_ENTRY,
			GTT_TYPE_PPGTT_PDE_ENTRY,
231
			GTT_TYPE_PPGTT_PDE_PT,
232 233 234 235
			GTT_TYPE_INVALID,
			GTT_TYPE_PPGTT_PTE_2M_ENTRY),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_1G_ENTRY,
			GTT_TYPE_PPGTT_PDP_ENTRY,
236
			GTT_TYPE_PPGTT_PDP_PT,
237 238 239 240 241
			GTT_TYPE_INVALID,
			GTT_TYPE_PPGTT_PTE_1G_ENTRY),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_GGTT_PTE,
			GTT_TYPE_GGTT_PTE,
			GTT_TYPE_INVALID,
242
			GTT_TYPE_INVALID,
243 244 245 246 247 248 249 250
			GTT_TYPE_INVALID),
};

static inline int get_next_pt_type(int type)
{
	return gtt_type_table[type].next_pt_type;
}

251 252 253 254 255
static inline int get_pt_type(int type)
{
	return gtt_type_table[type].pt_type;
}

256 257 258 259 260 261 262 263 264 265 266 267
static inline int get_entry_type(int type)
{
	return gtt_type_table[type].entry_type;
}

static inline int get_pse_type(int type)
{
	return gtt_type_table[type].pse_entry_type;
}

static u64 read_pte64(struct drm_i915_private *dev_priv, unsigned long index)
{
268
	void __iomem *addr = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + index;
269 270

	return readq(addr);
271 272
}

273
static void ggtt_invalidate(struct drm_i915_private *dev_priv)
274 275 276 277 278 279
{
	mmio_hw_access_pre(dev_priv);
	I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
	mmio_hw_access_post(dev_priv);
}

280 281 282
static void write_pte64(struct drm_i915_private *dev_priv,
		unsigned long index, u64 pte)
{
283
	void __iomem *addr = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + index;
284 285 286 287

	writeq(pte, addr);
}

288
static inline int gtt_get_entry64(void *pt,
289 290 291 292 293 294 295 296
		struct intel_gvt_gtt_entry *e,
		unsigned long index, bool hypervisor_access, unsigned long gpa,
		struct intel_vgpu *vgpu)
{
	const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
	int ret;

	if (WARN_ON(info->gtt_entry_size != 8))
297
		return -EINVAL;
298 299 300 301 302

	if (hypervisor_access) {
		ret = intel_gvt_hypervisor_read_gpa(vgpu, gpa +
				(index << info->gtt_entry_size_shift),
				&e->val64, 8);
303 304
		if (WARN_ON(ret))
			return ret;
305 306 307 308 309
	} else if (!pt) {
		e->val64 = read_pte64(vgpu->gvt->dev_priv, index);
	} else {
		e->val64 = *((u64 *)pt + index);
	}
310
	return 0;
311 312
}

313
static inline int gtt_set_entry64(void *pt,
314 315 316 317 318 319 320 321
		struct intel_gvt_gtt_entry *e,
		unsigned long index, bool hypervisor_access, unsigned long gpa,
		struct intel_vgpu *vgpu)
{
	const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
	int ret;

	if (WARN_ON(info->gtt_entry_size != 8))
322
		return -EINVAL;
323 324 325 326 327

	if (hypervisor_access) {
		ret = intel_gvt_hypervisor_write_gpa(vgpu, gpa +
				(index << info->gtt_entry_size_shift),
				&e->val64, 8);
328 329
		if (WARN_ON(ret))
			return ret;
330 331 332 333 334
	} else if (!pt) {
		write_pte64(vgpu->gvt->dev_priv, index, e->val64);
	} else {
		*((u64 *)pt + index) = e->val64;
	}
335
	return 0;
336 337 338 339
}

#define GTT_HAW 46

340 341 342
#define ADDR_1G_MASK	GENMASK_ULL(GTT_HAW - 1, 30)
#define ADDR_2M_MASK	GENMASK_ULL(GTT_HAW - 1, 21)
#define ADDR_4K_MASK	GENMASK_ULL(GTT_HAW - 1, 12)
343 344 345 346 347 348

static unsigned long gen8_gtt_get_pfn(struct intel_gvt_gtt_entry *e)
{
	unsigned long pfn;

	if (e->type == GTT_TYPE_PPGTT_PTE_1G_ENTRY)
349
		pfn = (e->val64 & ADDR_1G_MASK) >> PAGE_SHIFT;
350
	else if (e->type == GTT_TYPE_PPGTT_PTE_2M_ENTRY)
351
		pfn = (e->val64 & ADDR_2M_MASK) >> PAGE_SHIFT;
352
	else
353
		pfn = (e->val64 & ADDR_4K_MASK) >> PAGE_SHIFT;
354 355 356 357 358 359 360
	return pfn;
}

static void gen8_gtt_set_pfn(struct intel_gvt_gtt_entry *e, unsigned long pfn)
{
	if (e->type == GTT_TYPE_PPGTT_PTE_1G_ENTRY) {
		e->val64 &= ~ADDR_1G_MASK;
361
		pfn &= (ADDR_1G_MASK >> PAGE_SHIFT);
362 363
	} else if (e->type == GTT_TYPE_PPGTT_PTE_2M_ENTRY) {
		e->val64 &= ~ADDR_2M_MASK;
364
		pfn &= (ADDR_2M_MASK >> PAGE_SHIFT);
365 366
	} else {
		e->val64 &= ~ADDR_4K_MASK;
367
		pfn &= (ADDR_4K_MASK >> PAGE_SHIFT);
368 369
	}

370
	e->val64 |= (pfn << PAGE_SHIFT);
371 372 373 374 375 376 377 378 379
}

static bool gen8_gtt_test_pse(struct intel_gvt_gtt_entry *e)
{
	/* Entry doesn't have PSE bit. */
	if (get_pse_type(e->type) == GTT_TYPE_INVALID)
		return false;

	e->type = get_entry_type(e->type);
380
	if (!(e->val64 & _PAGE_PSE))
381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397
		return false;

	e->type = get_pse_type(e->type);
	return true;
}

static bool gen8_gtt_test_present(struct intel_gvt_gtt_entry *e)
{
	/*
	 * i915 writes PDP root pointer registers without present bit,
	 * it also works, so we need to treat root pointer entry
	 * specifically.
	 */
	if (e->type == GTT_TYPE_PPGTT_ROOT_L3_ENTRY
			|| e->type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY)
		return (e->val64 != 0);
	else
398
		return (e->val64 & _PAGE_PRESENT);
399 400 401 402
}

static void gtt_entry_clear_present(struct intel_gvt_gtt_entry *e)
{
403
	e->val64 &= ~_PAGE_PRESENT;
404 405
}

406 407
static void gtt_entry_set_present(struct intel_gvt_gtt_entry *e)
{
408
	e->val64 |= _PAGE_PRESENT;
409 410 411 412 413 414 415
}

/*
 * Per-platform GMA routines.
 */
static unsigned long gma_to_ggtt_pte_index(unsigned long gma)
{
416
	unsigned long x = (gma >> I915_GTT_PAGE_SHIFT);
417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439

	trace_gma_index(__func__, gma, x);
	return x;
}

#define DEFINE_PPGTT_GMA_TO_INDEX(prefix, ename, exp) \
static unsigned long prefix##_gma_to_##ename##_index(unsigned long gma) \
{ \
	unsigned long x = (exp); \
	trace_gma_index(__func__, gma, x); \
	return x; \
}

DEFINE_PPGTT_GMA_TO_INDEX(gen8, pte, (gma >> 12 & 0x1ff));
DEFINE_PPGTT_GMA_TO_INDEX(gen8, pde, (gma >> 21 & 0x1ff));
DEFINE_PPGTT_GMA_TO_INDEX(gen8, l3_pdp, (gma >> 30 & 0x3));
DEFINE_PPGTT_GMA_TO_INDEX(gen8, l4_pdp, (gma >> 30 & 0x1ff));
DEFINE_PPGTT_GMA_TO_INDEX(gen8, pml4, (gma >> 39 & 0x1ff));

static struct intel_gvt_gtt_pte_ops gen8_gtt_pte_ops = {
	.get_entry = gtt_get_entry64,
	.set_entry = gtt_set_entry64,
	.clear_present = gtt_entry_clear_present,
440
	.set_present = gtt_entry_set_present,
441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458
	.test_present = gen8_gtt_test_present,
	.test_pse = gen8_gtt_test_pse,
	.get_pfn = gen8_gtt_get_pfn,
	.set_pfn = gen8_gtt_set_pfn,
};

static struct intel_gvt_gtt_gma_ops gen8_gtt_gma_ops = {
	.gma_to_ggtt_pte_index = gma_to_ggtt_pte_index,
	.gma_to_pte_index = gen8_gma_to_pte_index,
	.gma_to_pde_index = gen8_gma_to_pde_index,
	.gma_to_l3_pdp_index = gen8_gma_to_l3_pdp_index,
	.gma_to_l4_pdp_index = gen8_gma_to_l4_pdp_index,
	.gma_to_pml4_index = gen8_gma_to_pml4_index,
};

/*
 * MM helpers.
 */
459 460 461
static void _ppgtt_get_root_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index,
		bool guest)
462
{
463
	struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
464

465
	GEM_BUG_ON(mm->type != INTEL_GVT_MM_PPGTT);
466

467 468 469 470
	entry->type = mm->ppgtt_mm.root_entry_type;
	pte_ops->get_entry(guest ? mm->ppgtt_mm.guest_pdps :
			   mm->ppgtt_mm.shadow_pdps,
			   entry, index, false, 0, mm->vgpu);
471

472
	pte_ops->test_pse(entry);
473 474
}

475 476
static inline void ppgtt_get_guest_root_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index)
477
{
478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538
	_ppgtt_get_root_entry(mm, entry, index, true);
}

static inline void ppgtt_get_shadow_root_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index)
{
	_ppgtt_get_root_entry(mm, entry, index, false);
}

static void _ppgtt_set_root_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index,
		bool guest)
{
	struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;

	pte_ops->set_entry(guest ? mm->ppgtt_mm.guest_pdps :
			   mm->ppgtt_mm.shadow_pdps,
			   entry, index, false, 0, mm->vgpu);
}

static inline void ppgtt_set_guest_root_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index)
{
	_ppgtt_set_root_entry(mm, entry, index, true);
}

static inline void ppgtt_set_shadow_root_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index)
{
	_ppgtt_set_root_entry(mm, entry, index, false);
}

static void ggtt_get_guest_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index)
{
	struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;

	GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);

	entry->type = GTT_TYPE_GGTT_PTE;
	pte_ops->get_entry(mm->ggtt_mm.virtual_ggtt, entry, index,
			   false, 0, mm->vgpu);
}

static void ggtt_set_guest_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index)
{
	struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;

	GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);

	pte_ops->set_entry(mm->ggtt_mm.virtual_ggtt, entry, index,
			   false, 0, mm->vgpu);
}

static void ggtt_set_host_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index)
{
	struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;

	GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);
539

540
	pte_ops->set_entry(NULL, entry, index, false, 0, mm->vgpu);
541 542 543 544 545
}

/*
 * PPGTT shadow page table helpers.
 */
546
static inline int ppgtt_spt_get_entry(
547 548 549 550 551 552 553
		struct intel_vgpu_ppgtt_spt *spt,
		void *page_table, int type,
		struct intel_gvt_gtt_entry *e, unsigned long index,
		bool guest)
{
	struct intel_gvt *gvt = spt->vgpu->gvt;
	struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
554
	int ret;
555 556 557 558

	e->type = get_entry_type(type);

	if (WARN(!gtt_type_is_entry(e->type), "invalid entry type\n"))
559
		return -EINVAL;
560

561
	ret = ops->get_entry(page_table, e, index, guest,
562
			spt->guest_page.gfn << I915_GTT_PAGE_SHIFT,
563
			spt->vgpu);
564 565 566
	if (ret)
		return ret;

567
	ops->test_pse(e);
568 569 570

	gvt_vdbg_mm("read ppgtt entry, spt type %d, entry type %d, index %lu, value %llx\n",
		    type, e->type, index, e->val64);
571
	return 0;
572 573
}

574
static inline int ppgtt_spt_set_entry(
575 576 577 578 579 580 581 582 583
		struct intel_vgpu_ppgtt_spt *spt,
		void *page_table, int type,
		struct intel_gvt_gtt_entry *e, unsigned long index,
		bool guest)
{
	struct intel_gvt *gvt = spt->vgpu->gvt;
	struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;

	if (WARN(!gtt_type_is_entry(e->type), "invalid entry type\n"))
584
		return -EINVAL;
585

586 587 588
	gvt_vdbg_mm("set ppgtt entry, spt type %d, entry type %d, index %lu, value %llx\n",
		    type, e->type, index, e->val64);

589
	return ops->set_entry(page_table, e, index, guest,
590
			spt->guest_page.gfn << I915_GTT_PAGE_SHIFT,
591 592 593 594 595
			spt->vgpu);
}

#define ppgtt_get_guest_entry(spt, e, index) \
	ppgtt_spt_get_entry(spt, NULL, \
596
		spt->guest_page.type, e, index, true)
597 598 599

#define ppgtt_set_guest_entry(spt, e, index) \
	ppgtt_spt_set_entry(spt, NULL, \
600
		spt->guest_page.type, e, index, true)
601 602 603 604 605 606 607 608 609

#define ppgtt_get_shadow_entry(spt, e, index) \
	ppgtt_spt_get_entry(spt, spt->shadow_page.vaddr, \
		spt->shadow_page.type, e, index, false)

#define ppgtt_set_shadow_entry(spt, e, index) \
	ppgtt_spt_set_entry(spt, spt->shadow_page.vaddr, \
		spt->shadow_page.type, e, index, false)

610
static void *alloc_spt(gfp_t gfp_mask)
611
{
612
	struct intel_vgpu_ppgtt_spt *spt;
613

614 615 616
	spt = kzalloc(sizeof(*spt), gfp_mask);
	if (!spt)
		return NULL;
617

618 619 620 621 622 623
	spt->shadow_page.page = alloc_page(gfp_mask);
	if (!spt->shadow_page.page) {
		kfree(spt);
		return NULL;
	}
	return spt;
624 625
}

626
static void free_spt(struct intel_vgpu_ppgtt_spt *spt)
627
{
628 629
	__free_page(spt->shadow_page.page);
	kfree(spt);
630 631
}

632 633 634
static int detach_oos_page(struct intel_vgpu *vgpu,
		struct intel_vgpu_oos_page *oos_page);

635
static void ppgtt_free_spt(struct intel_vgpu_ppgtt_spt *spt)
636
{
637
	struct device *kdev = &spt->vgpu->gvt->dev_priv->drm.pdev->dev;
638

639
	trace_spt_free(spt->vgpu->id, spt, spt->guest_page.type);
640

641 642
	dma_unmap_page(kdev, spt->shadow_page.mfn << I915_GTT_PAGE_SHIFT, 4096,
		       PCI_DMA_BIDIRECTIONAL);
643 644

	radix_tree_delete(&spt->vgpu->gtt.spt_tree, spt->shadow_page.mfn);
645

646 647
	if (spt->guest_page.oos_page)
		detach_oos_page(spt->vgpu, spt->guest_page.oos_page);
648

649
	intel_vgpu_unregister_page_track(spt->vgpu, spt->guest_page.gfn);
650 651 652 653 654

	list_del_init(&spt->post_shadow_list);
	free_spt(spt);
}

655
static void ppgtt_free_all_spt(struct intel_vgpu *vgpu)
656
{
657
	struct intel_vgpu_ppgtt_spt *spt;
658 659
	struct radix_tree_iter iter;
	void **slot;
660

661 662
	radix_tree_for_each_slot(slot, &vgpu->gtt.spt_tree, &iter, 0) {
		spt = radix_tree_deref_slot(slot);
663
		ppgtt_free_spt(spt);
664
	}
665 666
}

667
static int ppgtt_handle_guest_write_page_table_bytes(
668
		struct intel_vgpu_ppgtt_spt *spt,
669 670
		u64 pa, void *p_data, int bytes);

671 672 673
static int ppgtt_write_protection_handler(
		struct intel_vgpu_page_track *page_track,
		u64 gpa, void *data, int bytes)
674
{
675 676
	struct intel_vgpu_ppgtt_spt *spt = page_track->priv_data;

677 678 679 680 681
	int ret;

	if (bytes != 4 && bytes != 8)
		return -EINVAL;

682
	ret = ppgtt_handle_guest_write_page_table_bytes(spt, gpa, data, bytes);
683 684 685 686 687
	if (ret)
		return ret;
	return ret;
}

688 689 690 691 692 693
/* Find a spt by guest gfn. */
static struct intel_vgpu_ppgtt_spt *intel_vgpu_find_spt_by_gfn(
		struct intel_vgpu *vgpu, unsigned long gfn)
{
	struct intel_vgpu_page_track *track;

694 695 696
	track = intel_vgpu_find_page_track(vgpu, gfn);
	if (track && track->handler == ppgtt_write_protection_handler)
		return track->priv_data;
697 698 699 700 701

	return NULL;
}

/* Find the spt by shadow page mfn. */
702
static inline struct intel_vgpu_ppgtt_spt *intel_vgpu_find_spt_by_mfn(
703 704
		struct intel_vgpu *vgpu, unsigned long mfn)
{
705
	return radix_tree_lookup(&vgpu->gtt.spt_tree, mfn);
706 707
}

708
static int reclaim_one_ppgtt_mm(struct intel_gvt *gvt);
709

710
static struct intel_vgpu_ppgtt_spt *ppgtt_alloc_spt(
711 712
		struct intel_vgpu *vgpu, int type, unsigned long gfn)
{
713
	struct device *kdev = &vgpu->gvt->dev_priv->drm.pdev->dev;
714
	struct intel_vgpu_ppgtt_spt *spt = NULL;
715
	dma_addr_t daddr;
716
	int ret;
717 718 719 720

retry:
	spt = alloc_spt(GFP_KERNEL | __GFP_ZERO);
	if (!spt) {
721
		if (reclaim_one_ppgtt_mm(vgpu->gvt))
722 723
			goto retry;

724
		gvt_vgpu_err("fail to allocate ppgtt shadow page\n");
725 726 727 728 729 730 731 732
		return ERR_PTR(-ENOMEM);
	}

	spt->vgpu = vgpu;
	atomic_set(&spt->refcount, 1);
	INIT_LIST_HEAD(&spt->post_shadow_list);

	/*
733
	 * Init shadow_page.
734
	 */
735 736 737 738 739
	spt->shadow_page.type = type;
	daddr = dma_map_page(kdev, spt->shadow_page.page,
			     0, 4096, PCI_DMA_BIDIRECTIONAL);
	if (dma_mapping_error(kdev, daddr)) {
		gvt_vgpu_err("fail to map dma addr\n");
740 741
		ret = -EINVAL;
		goto err_free_spt;
742
	}
743 744
	spt->shadow_page.vaddr = page_address(spt->shadow_page.page);
	spt->shadow_page.mfn = daddr >> I915_GTT_PAGE_SHIFT;
745

746 747 748 749 750
	/*
	 * Init guest_page.
	 */
	spt->guest_page.type = type;
	spt->guest_page.gfn = gfn;
751

752 753
	ret = intel_vgpu_register_page_track(vgpu, spt->guest_page.gfn,
					ppgtt_write_protection_handler, spt);
754 755
	if (ret)
		goto err_unmap_dma;
756

757 758 759
	ret = radix_tree_insert(&vgpu->gtt.spt_tree, spt->shadow_page.mfn, spt);
	if (ret)
		goto err_unreg_page_track;
760

761 762
	trace_spt_alloc(vgpu->id, spt, type, spt->shadow_page.mfn, gfn);
	return spt;
763 764 765 766 767 768 769 770

err_unreg_page_track:
	intel_vgpu_unregister_page_track(vgpu, spt->guest_page.gfn);
err_unmap_dma:
	dma_unmap_page(kdev, daddr, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
err_free_spt:
	free_spt(spt);
	return ERR_PTR(ret);
771 772 773 774 775 776
}

#define pt_entry_size_shift(spt) \
	((spt)->vgpu->gvt->device_info.gtt_entry_size_shift)

#define pt_entries(spt) \
777
	(I915_GTT_PAGE_SIZE >> pt_entry_size_shift(spt))
778 779 780

#define for_each_present_guest_entry(spt, e, i) \
	for (i = 0; i < pt_entries(spt); i++) \
781 782
		if (!ppgtt_get_guest_entry(spt, e, i) && \
		    spt->vgpu->gvt->gtt.pte_ops->test_present(e))
783 784 785

#define for_each_present_shadow_entry(spt, e, i) \
	for (i = 0; i < pt_entries(spt); i++) \
786 787
		if (!ppgtt_get_shadow_entry(spt, e, i) && \
		    spt->vgpu->gvt->gtt.pte_ops->test_present(e))
788

789
static void ppgtt_get_spt(struct intel_vgpu_ppgtt_spt *spt)
790 791 792 793 794 795 796 797
{
	int v = atomic_read(&spt->refcount);

	trace_spt_refcount(spt->vgpu->id, "inc", spt, v, (v + 1));

	atomic_inc(&spt->refcount);
}

798
static int ppgtt_invalidate_spt(struct intel_vgpu_ppgtt_spt *spt);
799

800
static int ppgtt_invalidate_spt_by_shadow_entry(struct intel_vgpu *vgpu,
801 802 803 804
		struct intel_gvt_gtt_entry *e)
{
	struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
	struct intel_vgpu_ppgtt_spt *s;
805
	intel_gvt_gtt_type_t cur_pt_type;
806

807
	GEM_BUG_ON(!gtt_type_is_pt(get_next_pt_type(e->type)));
808

809 810 811 812 813 814 815
	if (e->type != GTT_TYPE_PPGTT_ROOT_L3_ENTRY
		&& e->type != GTT_TYPE_PPGTT_ROOT_L4_ENTRY) {
		cur_pt_type = get_next_pt_type(e->type) + 1;
		if (ops->get_pfn(e) ==
			vgpu->gtt.scratch_pt[cur_pt_type].page_mfn)
			return 0;
	}
816
	s = intel_vgpu_find_spt_by_mfn(vgpu, ops->get_pfn(e));
817
	if (!s) {
818 819
		gvt_vgpu_err("fail to find shadow page: mfn: 0x%lx\n",
				ops->get_pfn(e));
820 821
		return -ENXIO;
	}
822
	return ppgtt_invalidate_spt(s);
823 824
}

825
static int ppgtt_invalidate_spt(struct intel_vgpu_ppgtt_spt *spt)
826
{
827
	struct intel_vgpu *vgpu = spt->vgpu;
828 829 830 831 832 833
	struct intel_gvt_gtt_entry e;
	unsigned long index;
	int ret;
	int v = atomic_read(&spt->refcount);

	trace_spt_change(spt->vgpu->id, "die", spt,
834
			spt->guest_page.gfn, spt->shadow_page.type);
835 836 837 838 839 840 841 842 843 844

	trace_spt_refcount(spt->vgpu->id, "dec", spt, v, (v - 1));

	if (atomic_dec_return(&spt->refcount) > 0)
		return 0;

	if (gtt_type_is_pte_pt(spt->shadow_page.type))
		goto release;

	for_each_present_shadow_entry(spt, &e, index) {
845 846 847 848 849 850 851 852 853 854 855 856
		switch (e.type) {
		case GTT_TYPE_PPGTT_PTE_4K_ENTRY:
			gvt_vdbg_mm("invalidate 4K entry\n");
			continue;
		case GTT_TYPE_PPGTT_PTE_2M_ENTRY:
		case GTT_TYPE_PPGTT_PTE_1G_ENTRY:
			WARN(1, "GVT doesn't support 2M/1GB page\n");
			continue;
		case GTT_TYPE_PPGTT_PML4_ENTRY:
		case GTT_TYPE_PPGTT_PDP_ENTRY:
		case GTT_TYPE_PPGTT_PDE_ENTRY:
			gvt_vdbg_mm("invalidate PMUL4/PDP/PDE entry\n");
857
			ret = ppgtt_invalidate_spt_by_shadow_entry(
858 859 860 861 862 863
					spt->vgpu, &e);
			if (ret)
				goto fail;
			break;
		default:
			GEM_BUG_ON(1);
864 865 866 867
		}
	}
release:
	trace_spt_change(spt->vgpu->id, "release", spt,
868
			 spt->guest_page.gfn, spt->shadow_page.type);
869
	ppgtt_free_spt(spt);
870 871
	return 0;
fail:
872 873
	gvt_vgpu_err("fail: shadow page %p shadow entry 0x%llx type %d\n",
			spt, e.val64, e.type);
874 875 876
	return ret;
}

877
static int ppgtt_populate_spt(struct intel_vgpu_ppgtt_spt *spt);
878

879
static struct intel_vgpu_ppgtt_spt *ppgtt_populate_spt_by_guest_entry(
880 881 882
		struct intel_vgpu *vgpu, struct intel_gvt_gtt_entry *we)
{
	struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
883
	struct intel_vgpu_ppgtt_spt *spt = NULL;
884 885
	int ret;

886
	GEM_BUG_ON(!gtt_type_is_pt(get_next_pt_type(we->type)));
887

888 889
	spt = intel_vgpu_find_spt_by_gfn(vgpu, ops->get_pfn(we));
	if (spt)
890
		ppgtt_get_spt(spt);
891
	else {
892 893
		int type = get_next_pt_type(we->type);

894
		spt = ppgtt_alloc_spt(vgpu, type, ops->get_pfn(we));
895 896
		if (IS_ERR(spt)) {
			ret = PTR_ERR(spt);
897 898 899
			goto fail;
		}

900
		ret = intel_vgpu_enable_page_track(vgpu, spt->guest_page.gfn);
901 902 903
		if (ret)
			goto fail;

904
		ret = ppgtt_populate_spt(spt);
905 906 907
		if (ret)
			goto fail;

908 909
		trace_spt_change(vgpu->id, "new", spt, spt->guest_page.gfn,
				 spt->shadow_page.type);
910
	}
911
	return spt;
912
fail:
913
	gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n",
914
		     spt, we->val64, we->type);
915 916 917 918 919 920 921 922 923 924 925 926 927 928
	return ERR_PTR(ret);
}

static inline void ppgtt_generate_shadow_entry(struct intel_gvt_gtt_entry *se,
		struct intel_vgpu_ppgtt_spt *s, struct intel_gvt_gtt_entry *ge)
{
	struct intel_gvt_gtt_pte_ops *ops = s->vgpu->gvt->gtt.pte_ops;

	se->type = ge->type;
	se->val64 = ge->val64;

	ops->set_pfn(se, s->shadow_page.mfn);
}

929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963
static int ppgtt_populate_shadow_entry(struct intel_vgpu *vgpu,
	struct intel_vgpu_ppgtt_spt *spt, unsigned long index,
	struct intel_gvt_gtt_entry *ge)
{
	struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
	struct intel_gvt_gtt_entry se = *ge;
	unsigned long gfn, mfn;

	if (!pte_ops->test_present(ge))
		return 0;

	gfn = pte_ops->get_pfn(ge);

	switch (ge->type) {
	case GTT_TYPE_PPGTT_PTE_4K_ENTRY:
		gvt_vdbg_mm("shadow 4K gtt entry\n");
		break;
	case GTT_TYPE_PPGTT_PTE_2M_ENTRY:
	case GTT_TYPE_PPGTT_PTE_1G_ENTRY:
		gvt_vgpu_err("GVT doesn't support 2M/1GB entry\n");
		return -EINVAL;
	default:
		GEM_BUG_ON(1);
	};

	/* direct shadow */
	mfn = intel_gvt_hypervisor_gfn_to_mfn(vgpu, gfn);
	if (mfn == INTEL_GVT_INVALID_ADDR)
		return -ENXIO;

	pte_ops->set_pfn(&se, mfn);
	ppgtt_set_shadow_entry(spt, &se, index);
	return 0;
}

964
static int ppgtt_populate_spt(struct intel_vgpu_ppgtt_spt *spt)
965 966
{
	struct intel_vgpu *vgpu = spt->vgpu;
967 968
	struct intel_gvt *gvt = vgpu->gvt;
	struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
969 970
	struct intel_vgpu_ppgtt_spt *s;
	struct intel_gvt_gtt_entry se, ge;
971
	unsigned long gfn, i;
972 973 974
	int ret;

	trace_spt_change(spt->vgpu->id, "born", spt,
975
			 spt->guest_page.gfn, spt->shadow_page.type);
976

977 978
	for_each_present_guest_entry(spt, &ge, i) {
		if (gtt_type_is_pt(get_next_pt_type(ge.type))) {
979
			s = ppgtt_populate_spt_by_guest_entry(vgpu, &ge);
980 981 982 983 984 985 986 987
			if (IS_ERR(s)) {
				ret = PTR_ERR(s);
				goto fail;
			}
			ppgtt_get_shadow_entry(spt, &se, i);
			ppgtt_generate_shadow_entry(&se, s, &ge);
			ppgtt_set_shadow_entry(spt, &se, i);
		} else {
988
			gfn = ops->get_pfn(&ge);
989
			if (!intel_gvt_hypervisor_is_valid_gfn(vgpu, gfn)) {
990
				ops->set_pfn(&se, gvt->gtt.scratch_mfn);
991 992 993
				ppgtt_set_shadow_entry(spt, &se, i);
				continue;
			}
994

995 996 997
			ret = ppgtt_populate_shadow_entry(vgpu, spt, i, &ge);
			if (ret)
				goto fail;
998 999 1000 1001
		}
	}
	return 0;
fail:
1002 1003
	gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n",
			spt, ge.val64, ge.type);
1004 1005 1006
	return ret;
}

1007
static int ppgtt_handle_guest_entry_removal(struct intel_vgpu_ppgtt_spt *spt,
1008
		struct intel_gvt_gtt_entry *se, unsigned long index)
1009 1010 1011 1012 1013
{
	struct intel_vgpu *vgpu = spt->vgpu;
	struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
	int ret;

1014 1015
	trace_spt_guest_change(spt->vgpu->id, "remove", spt,
			       spt->shadow_page.type, se->val64, index);
1016

1017 1018 1019
	gvt_vdbg_mm("destroy old shadow entry, type %d, index %lu, value %llx\n",
		    se->type, index, se->val64);

1020
	if (!ops->test_present(se))
1021 1022
		return 0;

1023 1024
	if (ops->get_pfn(se) ==
	    vgpu->gtt.scratch_pt[spt->shadow_page.type].page_mfn)
1025 1026
		return 0;

1027
	if (gtt_type_is_pt(get_next_pt_type(se->type))) {
1028
		struct intel_vgpu_ppgtt_spt *s =
1029
			intel_vgpu_find_spt_by_mfn(vgpu, ops->get_pfn(se));
1030
		if (!s) {
1031
			gvt_vgpu_err("fail to find guest page\n");
1032 1033 1034
			ret = -ENXIO;
			goto fail;
		}
1035
		ret = ppgtt_invalidate_spt(s);
1036 1037 1038 1039 1040
		if (ret)
			goto fail;
	}
	return 0;
fail:
1041
	gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n",
1042
			spt, se->val64, se->type);
1043 1044 1045
	return ret;
}

1046
static int ppgtt_handle_guest_entry_add(struct intel_vgpu_ppgtt_spt *spt,
1047 1048 1049 1050 1051 1052 1053
		struct intel_gvt_gtt_entry *we, unsigned long index)
{
	struct intel_vgpu *vgpu = spt->vgpu;
	struct intel_gvt_gtt_entry m;
	struct intel_vgpu_ppgtt_spt *s;
	int ret;

1054 1055
	trace_spt_guest_change(spt->vgpu->id, "add", spt, spt->shadow_page.type,
			       we->val64, index);
1056

1057 1058 1059
	gvt_vdbg_mm("add shadow entry: type %d, index %lu, value %llx\n",
		    we->type, index, we->val64);

1060
	if (gtt_type_is_pt(get_next_pt_type(we->type))) {
1061
		s = ppgtt_populate_spt_by_guest_entry(vgpu, we);
1062 1063 1064 1065 1066 1067 1068 1069
		if (IS_ERR(s)) {
			ret = PTR_ERR(s);
			goto fail;
		}
		ppgtt_get_shadow_entry(spt, &m, index);
		ppgtt_generate_shadow_entry(&m, s, we);
		ppgtt_set_shadow_entry(spt, &m, index);
	} else {
1070
		ret = ppgtt_populate_shadow_entry(vgpu, spt, index, we);
1071 1072 1073 1074 1075
		if (ret)
			goto fail;
	}
	return 0;
fail:
1076 1077
	gvt_vgpu_err("fail: spt %p guest entry 0x%llx type %d\n",
		spt, we->val64, we->type);
1078 1079 1080 1081 1082 1083 1084 1085 1086
	return ret;
}

static int sync_oos_page(struct intel_vgpu *vgpu,
		struct intel_vgpu_oos_page *oos_page)
{
	const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
	struct intel_gvt *gvt = vgpu->gvt;
	struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
1087
	struct intel_vgpu_ppgtt_spt *spt = oos_page->spt;
1088
	struct intel_gvt_gtt_entry old, new;
1089 1090 1091 1092
	int index;
	int ret;

	trace_oos_change(vgpu->id, "sync", oos_page->id,
1093
			 spt, spt->guest_page.type);