wss_lib.c 64.5 KB
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/*
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 *  Copyright (c) by Jaroslav Kysela <perex@perex.cz>
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 *  Routines for control of CS4231(A)/CS4232/InterWave & compatible chips
 *
 *  Bugs:
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 *     - sometimes record brokes playback with WSS portion of
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 *       Yamaha OPL3-SA3 chip
 *     - CS4231 (GUS MAX) - still trouble with occasional noises
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 *			  - broken initialization?
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 *
 *   This program is free software; you can redistribute it and/or modify
 *   it under the terms of the GNU General Public License as published by
 *   the Free Software Foundation; either version 2 of the License, or
 *   (at your option) any later version.
 *
 *   This program is distributed in the hope that it will be useful,
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *   GNU General Public License for more details.
 *
 *   You should have received a copy of the GNU General Public License
 *   along with this program; if not, write to the Free Software
 *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 *
 */

#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/slab.h>
#include <linux/ioport.h>
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#include <linux/module.h>
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#include <sound/core.h>
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#include <sound/wss.h>
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#include <sound/pcm_params.h>
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#include <sound/tlv.h>
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#include <asm/io.h>
#include <asm/dma.h>
#include <asm/irq.h>

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MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
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MODULE_DESCRIPTION("Routines for control of CS4231(A)/CS4232/InterWave & compatible chips");
MODULE_LICENSE("GPL");

#if 0
#define SNDRV_DEBUG_MCE
#endif

/*
 *  Some variables
 */

static unsigned char freq_bits[14] = {
	/* 5510 */	0x00 | CS4231_XTAL2,
	/* 6620 */	0x0E | CS4231_XTAL2,
	/* 8000 */	0x00 | CS4231_XTAL1,
	/* 9600 */	0x0E | CS4231_XTAL1,
	/* 11025 */	0x02 | CS4231_XTAL2,
	/* 16000 */	0x02 | CS4231_XTAL1,
	/* 18900 */	0x04 | CS4231_XTAL2,
	/* 22050 */	0x06 | CS4231_XTAL2,
	/* 27042 */	0x04 | CS4231_XTAL1,
	/* 32000 */	0x06 | CS4231_XTAL1,
	/* 33075 */	0x0C | CS4231_XTAL2,
	/* 37800 */	0x08 | CS4231_XTAL2,
	/* 44100 */	0x0A | CS4231_XTAL2,
	/* 48000 */	0x0C | CS4231_XTAL1
};

static unsigned int rates[14] = {
	5510, 6620, 8000, 9600, 11025, 16000, 18900, 22050,
	27042, 32000, 33075, 37800, 44100, 48000
};

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static struct snd_pcm_hw_constraint_list hw_constraints_rates = {
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	.count = ARRAY_SIZE(rates),
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	.list = rates,
	.mask = 0,
};

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static int snd_wss_xrate(struct snd_pcm_runtime *runtime)
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{
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	return snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
					  &hw_constraints_rates);
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}

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static unsigned char snd_wss_original_image[32] =
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{
	0x00,			/* 00/00 - lic */
	0x00,			/* 01/01 - ric */
	0x9f,			/* 02/02 - la1ic */
	0x9f,			/* 03/03 - ra1ic */
	0x9f,			/* 04/04 - la2ic */
	0x9f,			/* 05/05 - ra2ic */
	0xbf,			/* 06/06 - loc */
	0xbf,			/* 07/07 - roc */
	0x20,			/* 08/08 - pdfr */
	CS4231_AUTOCALIB,	/* 09/09 - ic */
	0x00,			/* 0a/10 - pc */
	0x00,			/* 0b/11 - ti */
	CS4231_MODE2,		/* 0c/12 - mi */
	0xfc,			/* 0d/13 - lbc */
	0x00,			/* 0e/14 - pbru */
	0x00,			/* 0f/15 - pbrl */
	0x80,			/* 10/16 - afei */
	0x01,			/* 11/17 - afeii */
	0x9f,			/* 12/18 - llic */
	0x9f,			/* 13/19 - rlic */
	0x00,			/* 14/20 - tlb */
	0x00,			/* 15/21 - thb */
	0x00,			/* 16/22 - la3mic/reserved */
	0x00,			/* 17/23 - ra3mic/reserved */
	0x00,			/* 18/24 - afs */
	0x00,			/* 19/25 - lamoc/version */
	0xcf,			/* 1a/26 - mioc */
	0x00,			/* 1b/27 - ramoc/reserved */
	0x20,			/* 1c/28 - cdfr */
	0x00,			/* 1d/29 - res4 */
	0x00,			/* 1e/30 - cbru */
	0x00,			/* 1f/31 - cbrl */
};

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static unsigned char snd_opti93x_original_image[32] =
{
	0x00,		/* 00/00 - l_mixout_outctrl */
	0x00,		/* 01/01 - r_mixout_outctrl */
	0x88,		/* 02/02 - l_cd_inctrl */
	0x88,		/* 03/03 - r_cd_inctrl */
	0x88,		/* 04/04 - l_a1/fm_inctrl */
	0x88,		/* 05/05 - r_a1/fm_inctrl */
	0x80,		/* 06/06 - l_dac_inctrl */
	0x80,		/* 07/07 - r_dac_inctrl */
	0x00,		/* 08/08 - ply_dataform_reg */
	0x00,		/* 09/09 - if_conf */
	0x00,		/* 0a/10 - pin_ctrl */
	0x00,		/* 0b/11 - err_init_reg */
	0x0a,		/* 0c/12 - id_reg */
	0x00,		/* 0d/13 - reserved */
	0x00,		/* 0e/14 - ply_upcount_reg */
	0x00,		/* 0f/15 - ply_lowcount_reg */
	0x88,		/* 10/16 - reserved/l_a1_inctrl */
	0x88,		/* 11/17 - reserved/r_a1_inctrl */
	0x88,		/* 12/18 - l_line_inctrl */
	0x88,		/* 13/19 - r_line_inctrl */
	0x88,		/* 14/20 - l_mic_inctrl */
	0x88,		/* 15/21 - r_mic_inctrl */
	0x80,		/* 16/22 - l_out_outctrl */
	0x80,		/* 17/23 - r_out_outctrl */
	0x00,		/* 18/24 - reserved */
	0x00,		/* 19/25 - reserved */
	0x00,		/* 1a/26 - reserved */
	0x00,		/* 1b/27 - reserved */
	0x00,		/* 1c/28 - cap_dataform_reg */
	0x00,		/* 1d/29 - reserved */
	0x00,		/* 1e/30 - cap_upcount_reg */
	0x00		/* 1f/31 - cap_lowcount_reg */
};

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/*
 *  Basic I/O functions
 */

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static inline void wss_outb(struct snd_wss *chip, u8 offset, u8 val)
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{
	outb(val, chip->port + offset);
}

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static inline u8 wss_inb(struct snd_wss *chip, u8 offset)
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{
	return inb(chip->port + offset);
}

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static void snd_wss_wait(struct snd_wss *chip)
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{
	int timeout;

	for (timeout = 250;
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	     timeout > 0 && (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);
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	     timeout--)
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		udelay(100);
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}

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static void snd_wss_dout(struct snd_wss *chip, unsigned char reg,
			 unsigned char value)
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{
	int timeout;

	for (timeout = 250;
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	     timeout > 0 && (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);
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	     timeout--)
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		udelay(10);
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	wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
	wss_outb(chip, CS4231P(REG), value);
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	mb();
}

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void snd_wss_out(struct snd_wss *chip, unsigned char reg, unsigned char value)
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{
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	snd_wss_wait(chip);
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#ifdef CONFIG_SND_DEBUG
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	if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
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		snd_printk(KERN_DEBUG "out: auto calibration time out "
			   "- reg = 0x%x, value = 0x%x\n", reg, value);
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#endif
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	wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
	wss_outb(chip, CS4231P(REG), value);
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	chip->image[reg] = value;
	mb();
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	snd_printdd("codec out - reg 0x%x = 0x%x\n",
			chip->mce_bit | reg, value);
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}
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EXPORT_SYMBOL(snd_wss_out);
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unsigned char snd_wss_in(struct snd_wss *chip, unsigned char reg)
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{
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	snd_wss_wait(chip);
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#ifdef CONFIG_SND_DEBUG
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	if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
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		snd_printk(KERN_DEBUG "in: auto calibration time out "
			   "- reg = 0x%x\n", reg);
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#endif
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	wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
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	mb();
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	return wss_inb(chip, CS4231P(REG));
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}
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EXPORT_SYMBOL(snd_wss_in);
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void snd_cs4236_ext_out(struct snd_wss *chip, unsigned char reg,
			unsigned char val)
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{
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	wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | 0x17);
	wss_outb(chip, CS4231P(REG),
		 reg | (chip->image[CS4236_EXT_REG] & 0x01));
	wss_outb(chip, CS4231P(REG), val);
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	chip->eimage[CS4236_REG(reg)] = val;
#if 0
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	printk(KERN_DEBUG "ext out : reg = 0x%x, val = 0x%x\n", reg, val);
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#endif
}
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EXPORT_SYMBOL(snd_cs4236_ext_out);
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unsigned char snd_cs4236_ext_in(struct snd_wss *chip, unsigned char reg)
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{
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	wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | 0x17);
	wss_outb(chip, CS4231P(REG),
		 reg | (chip->image[CS4236_EXT_REG] & 0x01));
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#if 1
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	return wss_inb(chip, CS4231P(REG));
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#else
	{
		unsigned char res;
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		res = wss_inb(chip, CS4231P(REG));
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		printk(KERN_DEBUG "ext in : reg = 0x%x, val = 0x%x\n",
		       reg, res);
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		return res;
	}
#endif
}
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EXPORT_SYMBOL(snd_cs4236_ext_in);
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#if 0

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static void snd_wss_debug(struct snd_wss *chip)
{
	printk(KERN_DEBUG
		"CS4231 REGS:      INDEX = 0x%02x  "
		"                 STATUS = 0x%02x\n",
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					wss_inb(chip, CS4231P(REGSEL)),
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					wss_inb(chip, CS4231P(STATUS)));
	printk(KERN_DEBUG
		"  0x00: left input      = 0x%02x  "
		"  0x10: alt 1 (CFIG 2)  = 0x%02x\n",
					snd_wss_in(chip, 0x00),
					snd_wss_in(chip, 0x10));
	printk(KERN_DEBUG
		"  0x01: right input     = 0x%02x  "
		"  0x11: alt 2 (CFIG 3)  = 0x%02x\n",
					snd_wss_in(chip, 0x01),
					snd_wss_in(chip, 0x11));
	printk(KERN_DEBUG
		"  0x02: GF1 left input  = 0x%02x  "
		"  0x12: left line in    = 0x%02x\n",
					snd_wss_in(chip, 0x02),
					snd_wss_in(chip, 0x12));
	printk(KERN_DEBUG
		"  0x03: GF1 right input = 0x%02x  "
		"  0x13: right line in   = 0x%02x\n",
					snd_wss_in(chip, 0x03),
					snd_wss_in(chip, 0x13));
	printk(KERN_DEBUG
		"  0x04: CD left input   = 0x%02x  "
		"  0x14: timer low       = 0x%02x\n",
					snd_wss_in(chip, 0x04),
					snd_wss_in(chip, 0x14));
	printk(KERN_DEBUG
		"  0x05: CD right input  = 0x%02x  "
		"  0x15: timer high      = 0x%02x\n",
					snd_wss_in(chip, 0x05),
					snd_wss_in(chip, 0x15));
	printk(KERN_DEBUG
		"  0x06: left output     = 0x%02x  "
		"  0x16: left MIC (PnP)  = 0x%02x\n",
					snd_wss_in(chip, 0x06),
					snd_wss_in(chip, 0x16));
	printk(KERN_DEBUG
		"  0x07: right output    = 0x%02x  "
		"  0x17: right MIC (PnP) = 0x%02x\n",
					snd_wss_in(chip, 0x07),
					snd_wss_in(chip, 0x17));
	printk(KERN_DEBUG
		"  0x08: playback format = 0x%02x  "
		"  0x18: IRQ status      = 0x%02x\n",
					snd_wss_in(chip, 0x08),
					snd_wss_in(chip, 0x18));
	printk(KERN_DEBUG
		"  0x09: iface (CFIG 1)  = 0x%02x  "
		"  0x19: left line out   = 0x%02x\n",
					snd_wss_in(chip, 0x09),
					snd_wss_in(chip, 0x19));
	printk(KERN_DEBUG
		"  0x0a: pin control     = 0x%02x  "
		"  0x1a: mono control    = 0x%02x\n",
					snd_wss_in(chip, 0x0a),
					snd_wss_in(chip, 0x1a));
	printk(KERN_DEBUG
		"  0x0b: init & status   = 0x%02x  "
		"  0x1b: right line out  = 0x%02x\n",
					snd_wss_in(chip, 0x0b),
					snd_wss_in(chip, 0x1b));
	printk(KERN_DEBUG
		"  0x0c: revision & mode = 0x%02x  "
		"  0x1c: record format   = 0x%02x\n",
					snd_wss_in(chip, 0x0c),
					snd_wss_in(chip, 0x1c));
	printk(KERN_DEBUG
		"  0x0d: loopback        = 0x%02x  "
		"  0x1d: var freq (PnP)  = 0x%02x\n",
					snd_wss_in(chip, 0x0d),
					snd_wss_in(chip, 0x1d));
	printk(KERN_DEBUG
		"  0x0e: ply upr count   = 0x%02x  "
		"  0x1e: ply lwr count   = 0x%02x\n",
					snd_wss_in(chip, 0x0e),
					snd_wss_in(chip, 0x1e));
	printk(KERN_DEBUG
		"  0x0f: rec upr count   = 0x%02x  "
		"  0x1f: rec lwr count   = 0x%02x\n",
					snd_wss_in(chip, 0x0f),
					snd_wss_in(chip, 0x1f));
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}

#endif

/*
 *  CS4231 detection / MCE routines
 */

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static void snd_wss_busy_wait(struct snd_wss *chip)
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{
	int timeout;

	/* huh.. looks like this sequence is proper for CS4231A chip (GUS MAX) */
	for (timeout = 5; timeout > 0; timeout--)
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		wss_inb(chip, CS4231P(REGSEL));
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	/* end of cleanup sequence */
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	for (timeout = 25000;
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	     timeout > 0 && (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);
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	     timeout--)
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		udelay(10);
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}

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void snd_wss_mce_up(struct snd_wss *chip)
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{
	unsigned long flags;
	int timeout;

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	snd_wss_wait(chip);
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#ifdef CONFIG_SND_DEBUG
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	if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
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		snd_printk(KERN_DEBUG
			   "mce_up - auto calibration time out (0)\n");
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#endif
	spin_lock_irqsave(&chip->reg_lock, flags);
	chip->mce_bit |= CS4231_MCE;
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	timeout = wss_inb(chip, CS4231P(REGSEL));
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	if (timeout == 0x80)
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		snd_printk(KERN_DEBUG "mce_up [0x%lx]: "
			   "serious init problem - codec still busy\n",
			   chip->port);
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	if (!(timeout & CS4231_MCE))
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		wss_outb(chip, CS4231P(REGSEL),
			 chip->mce_bit | (timeout & 0x1f));
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	spin_unlock_irqrestore(&chip->reg_lock, flags);
}
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EXPORT_SYMBOL(snd_wss_mce_up);
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void snd_wss_mce_down(struct snd_wss *chip)
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{
	unsigned long flags;
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	unsigned long end_time;
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	int timeout;
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	int hw_mask = WSS_HW_CS4231_MASK | WSS_HW_CS4232_MASK | WSS_HW_AD1848;
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	snd_wss_busy_wait(chip);
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#ifdef CONFIG_SND_DEBUG
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	if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
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		snd_printk(KERN_DEBUG "mce_down [0x%lx] - "
			   "auto calibration time out (0)\n",
			   (long)CS4231P(REGSEL));
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#endif
	spin_lock_irqsave(&chip->reg_lock, flags);
	chip->mce_bit &= ~CS4231_MCE;
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	timeout = wss_inb(chip, CS4231P(REGSEL));
	wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | (timeout & 0x1f));
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	spin_unlock_irqrestore(&chip->reg_lock, flags);
	if (timeout == 0x80)
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		snd_printk(KERN_DEBUG "mce_down [0x%lx]: "
			   "serious init problem - codec still busy\n",
			   chip->port);
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	if ((timeout & CS4231_MCE) == 0 || !(chip->hardware & hw_mask))
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		return;

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	/*
	 * Wait for (possible -- during init auto-calibration may not be set)
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	 * calibration process to start. Needs up to 5 sample periods on AD1848
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	 * which at the slowest possible rate of 5.5125 kHz means 907 us.
	 */
	msleep(1);
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	snd_printdd("(1) jiffies = %lu\n", jiffies);

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	/* check condition up to 250 ms */
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	end_time = jiffies + msecs_to_jiffies(250);
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	while (snd_wss_in(chip, CS4231_TEST_INIT) &
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		CS4231_CALIB_IN_PROGRESS) {

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		if (time_after(jiffies, end_time)) {
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			snd_printk(KERN_ERR "mce_down - "
					"auto calibration time out (2)\n");
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			return;
		}
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		msleep(1);
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	}
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	snd_printdd("(2) jiffies = %lu\n", jiffies);

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	/* check condition up to 100 ms */
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	end_time = jiffies + msecs_to_jiffies(100);
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	while (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT) {
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		if (time_after(jiffies, end_time)) {
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			snd_printk(KERN_ERR "mce_down - auto calibration time out (3)\n");
			return;
		}
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		msleep(1);
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	}
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	snd_printdd("(3) jiffies = %lu\n", jiffies);
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	snd_printd("mce_down - exit = 0x%x\n", wss_inb(chip, CS4231P(REGSEL)));
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}
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EXPORT_SYMBOL(snd_wss_mce_down);
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static unsigned int snd_wss_get_count(unsigned char format, unsigned int size)
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{
	switch (format & 0xe0) {
	case CS4231_LINEAR_16:
	case CS4231_LINEAR_16_BIG:
		size >>= 1;
		break;
	case CS4231_ADPCM_16:
		return size >> 2;
	}
	if (format & CS4231_STEREO)
		size >>= 1;
	return size;
}

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static int snd_wss_trigger(struct snd_pcm_substream *substream,
			   int cmd)
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{
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	struct snd_wss *chip = snd_pcm_substream_chip(substream);
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	int result = 0;
	unsigned int what;
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	struct snd_pcm_substream *s;
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	int do_start;

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_RESUME:
		do_start = 1; break;
	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
		do_start = 0; break;
	default:
		return -EINVAL;
	}

	what = 0;
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	snd_pcm_group_for_each_entry(s, substream) {
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		if (s == chip->playback_substream) {
			what |= CS4231_PLAYBACK_ENABLE;
			snd_pcm_trigger_done(s, substream);
		} else if (s == chip->capture_substream) {
			what |= CS4231_RECORD_ENABLE;
			snd_pcm_trigger_done(s, substream);
		}
	}
	spin_lock(&chip->reg_lock);
	if (do_start) {
		chip->image[CS4231_IFACE_CTRL] |= what;
		if (chip->trigger)
			chip->trigger(chip, what, 1);
	} else {
		chip->image[CS4231_IFACE_CTRL] &= ~what;
		if (chip->trigger)
			chip->trigger(chip, what, 0);
	}
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	snd_wss_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
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	spin_unlock(&chip->reg_lock);
#if 0
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	snd_wss_debug(chip);
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#endif
	return result;
}

/*
 *  CODEC I/O
 */

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static unsigned char snd_wss_get_rate(unsigned int rate)
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{
	int i;

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	for (i = 0; i < ARRAY_SIZE(rates); i++)
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		if (rate == rates[i])
			return freq_bits[i];
	// snd_BUG();
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	return freq_bits[ARRAY_SIZE(rates) - 1];
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}

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static unsigned char snd_wss_get_format(struct snd_wss *chip,
					int format,
					int channels)
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{
	unsigned char rformat;

	rformat = CS4231_LINEAR_8;
	switch (format) {
	case SNDRV_PCM_FORMAT_MU_LAW:	rformat = CS4231_ULAW_8; break;
	case SNDRV_PCM_FORMAT_A_LAW:	rformat = CS4231_ALAW_8; break;
	case SNDRV_PCM_FORMAT_S16_LE:	rformat = CS4231_LINEAR_16; break;
	case SNDRV_PCM_FORMAT_S16_BE:	rformat = CS4231_LINEAR_16_BIG; break;
	case SNDRV_PCM_FORMAT_IMA_ADPCM:	rformat = CS4231_ADPCM_16; break;
	}
	if (channels > 1)
		rformat |= CS4231_STEREO;
#if 0
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	snd_printk(KERN_DEBUG "get_format: 0x%x (mode=0x%x)\n", format, mode);
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#endif
	return rformat;
}

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static void snd_wss_calibrate_mute(struct snd_wss *chip, int mute)
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{
	unsigned long flags;

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	mute = mute ? 0x80 : 0;
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	spin_lock_irqsave(&chip->reg_lock, flags);
	if (chip->calibrate_mute == mute) {
		spin_unlock_irqrestore(&chip->reg_lock, flags);
		return;
	}
	if (!mute) {
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		snd_wss_dout(chip, CS4231_LEFT_INPUT,
			     chip->image[CS4231_LEFT_INPUT]);
		snd_wss_dout(chip, CS4231_RIGHT_INPUT,
			     chip->image[CS4231_RIGHT_INPUT]);
		snd_wss_dout(chip, CS4231_LOOPBACK,
			     chip->image[CS4231_LOOPBACK]);
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	} else {
		snd_wss_dout(chip, CS4231_LEFT_INPUT,
			     0);
		snd_wss_dout(chip, CS4231_RIGHT_INPUT,
			     0);
		snd_wss_dout(chip, CS4231_LOOPBACK,
			     0xfd);
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	}
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	snd_wss_dout(chip, CS4231_AUX1_LEFT_INPUT,
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		     mute | chip->image[CS4231_AUX1_LEFT_INPUT]);
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	snd_wss_dout(chip, CS4231_AUX1_RIGHT_INPUT,
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		     mute | chip->image[CS4231_AUX1_RIGHT_INPUT]);
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	snd_wss_dout(chip, CS4231_AUX2_LEFT_INPUT,
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		     mute | chip->image[CS4231_AUX2_LEFT_INPUT]);
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	snd_wss_dout(chip, CS4231_AUX2_RIGHT_INPUT,
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		     mute | chip->image[CS4231_AUX2_RIGHT_INPUT]);
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	snd_wss_dout(chip, CS4231_LEFT_OUTPUT,
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		     mute | chip->image[CS4231_LEFT_OUTPUT]);
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	snd_wss_dout(chip, CS4231_RIGHT_OUTPUT,
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		     mute | chip->image[CS4231_RIGHT_OUTPUT]);
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	if (!(chip->hardware & WSS_HW_AD1848_MASK)) {
		snd_wss_dout(chip, CS4231_LEFT_LINE_IN,
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			     mute | chip->image[CS4231_LEFT_LINE_IN]);
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		snd_wss_dout(chip, CS4231_RIGHT_LINE_IN,
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			     mute | chip->image[CS4231_RIGHT_LINE_IN]);
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		snd_wss_dout(chip, CS4231_MONO_CTRL,
			     mute ? 0xc0 : chip->image[CS4231_MONO_CTRL]);
	}
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	if (chip->hardware == WSS_HW_INTERWAVE) {
		snd_wss_dout(chip, CS4231_LEFT_MIC_INPUT,
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			     mute | chip->image[CS4231_LEFT_MIC_INPUT]);
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		snd_wss_dout(chip, CS4231_RIGHT_MIC_INPUT,
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			     mute | chip->image[CS4231_RIGHT_MIC_INPUT]);
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		snd_wss_dout(chip, CS4231_LINE_LEFT_OUTPUT,
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			     mute | chip->image[CS4231_LINE_LEFT_OUTPUT]);
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		snd_wss_dout(chip, CS4231_LINE_RIGHT_OUTPUT,
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			     mute | chip->image[CS4231_LINE_RIGHT_OUTPUT]);
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	}
	chip->calibrate_mute = mute;
	spin_unlock_irqrestore(&chip->reg_lock, flags);
}

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static void snd_wss_playback_format(struct snd_wss *chip,
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				       struct snd_pcm_hw_params *params,
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				       unsigned char pdfr)
{
	unsigned long flags;
	int full_calib = 1;

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	mutex_lock(&chip->mce_mutex);
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	if (chip->hardware == WSS_HW_CS4231A ||
	    (chip->hardware & WSS_HW_CS4232_MASK)) {
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		spin_lock_irqsave(&chip->reg_lock, flags);
		if ((chip->image[CS4231_PLAYBK_FORMAT] & 0x0f) == (pdfr & 0x0f)) {	/* rate is same? */
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			snd_wss_out(chip, CS4231_ALT_FEATURE_1,
				    chip->image[CS4231_ALT_FEATURE_1] | 0x10);
			chip->image[CS4231_PLAYBK_FORMAT] = pdfr;
			snd_wss_out(chip, CS4231_PLAYBK_FORMAT,
				    chip->image[CS4231_PLAYBK_FORMAT]);
			snd_wss_out(chip, CS4231_ALT_FEATURE_1,
				    chip->image[CS4231_ALT_FEATURE_1] &= ~0x10);
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			udelay(100); /* Fixes audible clicks at least on GUS MAX */
			full_calib = 0;
		}
		spin_unlock_irqrestore(&chip->reg_lock, flags);
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	} else if (chip->hardware == WSS_HW_AD1845) {
		unsigned rate = params_rate(params);

		/*
		 * Program the AD1845 correctly for the playback stream.
		 * Note that we do NOT need to toggle the MCE bit because
		 * the PLAYBACK_ENABLE bit of the Interface Configuration
		 * register is set.
		 *
		 * NOTE: We seem to need to write to the MSB before the LSB
		 *       to get the correct sample frequency.
		 */
		spin_lock_irqsave(&chip->reg_lock, flags);
		snd_wss_out(chip, CS4231_PLAYBK_FORMAT, (pdfr & 0xf0));
		snd_wss_out(chip, AD1845_UPR_FREQ_SEL, (rate >> 8) & 0xff);
		snd_wss_out(chip, AD1845_LWR_FREQ_SEL, rate & 0xff);
		full_calib = 0;
		spin_unlock_irqrestore(&chip->reg_lock, flags);
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	}
	if (full_calib) {
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		snd_wss_mce_up(chip);
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		spin_lock_irqsave(&chip->reg_lock, flags);
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		if (chip->hardware != WSS_HW_INTERWAVE && !chip->single_dma) {
			if (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE)
				pdfr = (pdfr & 0xf0) |
				       (chip->image[CS4231_REC_FORMAT] & 0x0f);
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		} else {
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			chip->image[CS4231_PLAYBK_FORMAT] = pdfr;
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		}
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		snd_wss_out(chip, CS4231_PLAYBK_FORMAT, pdfr);
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		spin_unlock_irqrestore(&chip->reg_lock, flags);
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		if (chip->hardware == WSS_HW_OPL3SA2)
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			udelay(100);	/* this seems to help */
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		snd_wss_mce_down(chip);
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	}
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	mutex_unlock(&chip->mce_mutex);
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}

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static void snd_wss_capture_format(struct snd_wss *chip,
				   struct snd_pcm_hw_params *params,
				   unsigned char cdfr)
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{
	unsigned long flags;
	int full_calib = 1;

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	mutex_lock(&chip->mce_mutex);
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	if (chip->hardware == WSS_HW_CS4231A ||
	    (chip->hardware & WSS_HW_CS4232_MASK)) {
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		spin_lock_irqsave(&chip->reg_lock, flags);
		if ((chip->image[CS4231_PLAYBK_FORMAT] & 0x0f) == (cdfr & 0x0f) ||	/* rate is same? */
		    (chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) {
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			snd_wss_out(chip, CS4231_ALT_FEATURE_1,
				chip->image[CS4231_ALT_FEATURE_1] | 0x20);
			snd_wss_out(chip, CS4231_REC_FORMAT,
				chip->image[CS4231_REC_FORMAT] = cdfr);
			snd_wss_out(chip, CS4231_ALT_FEATURE_1,
				chip->image[CS4231_ALT_FEATURE_1] &= ~0x20);
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			full_calib = 0;
		}
		spin_unlock_irqrestore(&chip->reg_lock, flags);
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	} else if (chip->hardware == WSS_HW_AD1845) {
		unsigned rate = params_rate(params);

		/*
		 * Program the AD1845 correctly for the capture stream.
		 * Note that we do NOT need to toggle the MCE bit because
		 * the PLAYBACK_ENABLE bit of the Interface Configuration
		 * register is set.
		 *
		 * NOTE: We seem to need to write to the MSB before the LSB
		 *       to get the correct sample frequency.
		 */
		spin_lock_irqsave(&chip->reg_lock, flags);
		snd_wss_out(chip, CS4231_REC_FORMAT, (cdfr & 0xf0));
		snd_wss_out(chip, AD1845_UPR_FREQ_SEL, (rate >> 8) & 0xff);
		snd_wss_out(chip, AD1845_LWR_FREQ_SEL, rate & 0xff);
		full_calib = 0;
		spin_unlock_irqrestore(&chip->reg_lock, flags);
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	}
	if (full_calib) {
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		snd_wss_mce_up(chip);
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		spin_lock_irqsave(&chip->reg_lock, flags);
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		if (chip->hardware != WSS_HW_INTERWAVE &&
		    !(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) {
			if (chip->single_dma)
				snd_wss_out(chip, CS4231_PLAYBK_FORMAT, cdfr);
			else
				snd_wss_out(chip, CS4231_PLAYBK_FORMAT,
				   (chip->image[CS4231_PLAYBK_FORMAT] & 0xf0) |
				   (cdfr & 0x0f));
			spin_unlock_irqrestore(&chip->reg_lock, flags);
			snd_wss_mce_down(chip);
			snd_wss_mce_up(chip);
			spin_lock_irqsave(&chip->reg_lock, flags);
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		}
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		if (chip->hardware & WSS_HW_AD1848_MASK)
			snd_wss_out(chip, CS4231_PLAYBK_FORMAT, cdfr);
		else
			snd_wss_out(chip, CS4231_REC_FORMAT, cdfr);
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		spin_unlock_irqrestore(&chip->reg_lock, flags);
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		snd_wss_mce_down(chip);
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	}
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	mutex_unlock(&chip->mce_mutex);
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}

/*
 *  Timer interface
 */

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static unsigned long snd_wss_timer_resolution(struct snd_timer *timer)
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{
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	struct snd_wss *chip = snd_timer_chip(timer);
	if (chip->hardware & WSS_HW_CS4236B_MASK)
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		return 14467;
	else
		return chip->image[CS4231_PLAYBK_FORMAT] & 1 ? 9969 : 9920;
}

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static int snd_wss_timer_start(struct snd_timer *timer)
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{
	unsigned long flags;
	unsigned int ticks;
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	struct snd_wss *chip = snd_timer_chip(timer);
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	spin_lock_irqsave(&chip->reg_lock, flags);
	ticks = timer->sticks;
	if ((chip->image[CS4231_ALT_FEATURE_1] & CS4231_TIMER_ENABLE) == 0 ||
	    (unsigned char)(ticks >> 8) != chip->image[CS4231_TIMER_HIGH] ||
	    (unsigned char)ticks != chip->image[CS4231_TIMER_LOW]) {
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		chip->image[CS4231_TIMER_HIGH] = (unsigned char) (ticks >> 8);
		snd_wss_out(chip, CS4231_TIMER_HIGH,
			    chip->image[CS4231_TIMER_HIGH]);
		chip->image[CS4231_TIMER_LOW] = (unsigned char) ticks;
		snd_wss_out(chip, CS4231_TIMER_LOW,
			    chip->image[CS4231_TIMER_LOW]);
		snd_wss_out(chip, CS4231_ALT_FEATURE_1,
			    chip->image[CS4231_ALT_FEATURE_1] |
			    CS4231_TIMER_ENABLE);
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	}
	spin_unlock_irqrestore(&chip->reg_lock, flags);
	return 0;
}

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static int snd_wss_timer_stop(struct snd_timer *timer)
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{
	unsigned long flags;
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	struct snd_wss *chip = snd_timer_chip(timer);
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	spin_lock_irqsave(&chip->reg_lock, flags);
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	chip->image[CS4231_ALT_FEATURE_1] &= ~CS4231_TIMER_ENABLE;
	snd_wss_out(chip, CS4231_ALT_FEATURE_1,
		    chip->image[CS4231_ALT_FEATURE_1]);
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	spin_unlock_irqrestore(&chip->reg_lock, flags);
	return 0;
}

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static void snd_wss_init(struct snd_wss *chip)
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{
	unsigned long flags;

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	snd_wss_calibrate_mute(chip, 1);
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	snd_wss_mce_down(chip);
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#ifdef SNDRV_DEBUG_MCE
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	snd_printk(KERN_DEBUG "init: (1)\n");
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#endif
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	snd_wss_mce_up(chip);
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	spin_lock_irqsave(&chip->reg_lock, flags);
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	chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE |
					    CS4231_PLAYBACK_PIO |
					    CS4231_RECORD_ENABLE |
					    CS4231_RECORD_PIO |
					    CS4231_CALIB_MODE);
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	chip->image[CS4231_IFACE_CTRL] |= CS4231_AUTOCALIB;
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	snd_wss_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
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	spin_unlock_irqrestore(&chip->reg_lock, flags);
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	snd_wss_mce_down(chip);
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#ifdef SNDRV_DEBUG_MCE
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	snd_printk(KERN_DEBUG "init: (2)\n");
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#endif

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	snd_wss_mce_up(chip);
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	spin_lock_irqsave(&chip->reg_lock, flags);
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	chip->image[CS4231_IFACE_CTRL] &= ~CS4231_AUTOCALIB;
	snd_wss_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
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	snd_wss_out(chip,
		    CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1]);
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	spin_unlock_irqrestore(&chip->reg_lock, flags);
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	snd_wss_mce_down(chip);
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#ifdef SNDRV_DEBUG_MCE
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	snd_printk(KERN_DEBUG "init: (3) - afei = 0x%x\n",
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		   chip->image[CS4231_ALT_FEATURE_1]);
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#endif

	spin_lock_irqsave(&chip->reg_lock, flags);
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	snd_wss_out(chip, CS4231_ALT_FEATURE_2,
		    chip->image[CS4231_ALT_FEATURE_2]);
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	spin_unlock_irqrestore(&chip->reg_lock, flags);

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	snd_wss_mce_up(chip);
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	spin_lock_irqsave(&chip->reg_lock, flags);
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	snd_wss_out(chip, CS4231_PLAYBK_FORMAT,
		    chip->image[CS4231_PLAYBK_FORMAT]);
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	spin_unlock_irqrestore(&chip->reg_lock, flags);
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	snd_wss_mce_down(chip);
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#ifdef SNDRV_DEBUG_MCE
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	snd_printk(KERN_DEBUG "init: (4)\n");
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#endif

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	snd_wss_mce_up(chip);
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	spin_lock_irqsave(&chip->reg_lock, flags);
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	if (!(chip->hardware & WSS_HW_AD1848_MASK))
		snd_wss_out(chip, CS4231_REC_FORMAT,
			    chip->image[CS4231_REC_FORMAT]);
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	spin_unlock_irqrestore(&chip->reg_lock, flags);
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	snd_wss_mce_down(chip);
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	snd_wss_calibrate_mute(chip, 0);
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#ifdef SNDRV_DEBUG_MCE
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	snd_printk(KERN_DEBUG "init: (5)\n");
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#endif
}

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static int snd_wss_open(struct snd_wss *chip, unsigned int mode)
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{
	unsigned long flags;

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	mutex_lock(&chip->open_mutex);
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	if ((chip->mode & mode) ||
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	    ((chip->mode & WSS_MODE_OPEN) && chip->single_dma)) {
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		mutex_unlock(&chip->open_mutex);
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		return -EAGAIN;
	}
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	if (chip->mode & WSS_MODE_OPEN) {
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		chip->mode |= mode;
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		mutex_unlock(&chip->open_mutex);
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		return 0;
	}
	/* ok. now enable and ack CODEC IRQ */
	spin_lock_irqsave(&chip->reg_lock, flags);
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	if (!(chip->hardware & WSS_HW_AD1848_MASK)) {
		snd_wss_out(chip, CS4231_IRQ_STATUS,
			    CS4231_PLAYBACK_IRQ |
			    CS4231_RECORD_IRQ |
			    CS4231_TIMER_IRQ);
		snd_wss_out(chip, CS4231_IRQ_STATUS, 0);
	}
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	wss_outb(chip, CS4231P(STATUS), 0);	/* clear IRQ */
	wss_outb(chip, CS4231P(STATUS), 0);	/* clear IRQ */
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	chip->image[CS4231_PIN_CTRL] |= CS4231_IRQ_ENABLE;
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	snd_wss_out(chip, CS4231_PIN_CTRL, chip->image[CS4231_PIN_CTRL]);
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	if (!(chip->hardware & WSS_HW_AD1848_MASK)) {
		snd_wss_out(chip, CS4231_IRQ_STATUS,
			    CS4231_PLAYBACK_IRQ |
			    CS4231_RECORD_IRQ |
			    CS4231_TIMER_IRQ);
		snd_wss_out(chip, CS4231_IRQ_STATUS, 0);
	}
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	spin_unlock_irqrestore(&chip->reg_lock, flags);

	chip->mode = mode;
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	mutex_unlock(&chip->open_mutex);
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	return 0;
}

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static void snd_wss_close(struct snd_wss *chip, unsigned int mode)
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{
	unsigned long flags;

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	mutex_lock(&chip->open_mutex);
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	chip->mode &= ~mode;
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	if (chip->mode & WSS_MODE_OPEN) {
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		mutex_unlock(&chip->open_mutex);
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		return;
	}
	/* disable IRQ */
	spin_lock_irqsave(&chip->reg_lock, flags);
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	if (!(chip->hardware & WSS_HW_AD1848_MASK))
		snd_wss_out(chip, CS4231_IRQ_STATUS, 0);
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	wss_outb(chip, CS4231P(STATUS), 0);	/* clear IRQ */
	wss_outb(chip, CS4231P(STATUS), 0);	/* clear IRQ */
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	chip->image[CS4231_PIN_CTRL] &= ~CS4231_IRQ_ENABLE;
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	snd_wss_out(chip, CS4231_PIN_CTRL, chip->image[CS4231_PIN_CTRL]);
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	/* now disable record & playback */

	if (chip->image[CS4231_IFACE_CTRL] & (CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
					       CS4231_RECORD_ENABLE | CS4231_RECORD_PIO)) {
		spin_unlock_irqrestore(&chip->reg_lock, flags);
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		snd_wss_mce_up(chip);
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		spin_lock_irqsave(&chip->reg_lock, flags);
		chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
						     CS4231_RECORD_ENABLE | CS4231_RECORD_PIO);
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		snd_wss_out(chip, CS4231_IFACE_CTRL,
			    chip->image[CS4231_IFACE_CTRL]);
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		spin_unlock_irqrestore(&chip->reg_lock, flags);
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		snd_wss_mce_down(chip);
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		spin_lock_irqsave(&chip->reg_lock, flags);
	}

	/* clear IRQ again */
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	if (!(chip->hardware & WSS_HW_AD1848_MASK))
		snd_wss_out(chip, CS4231_IRQ_STATUS, 0);
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	wss_outb(chip, CS4231P(STATUS), 0);	/* clear IRQ */
	wss_outb(chip, CS4231P(STATUS), 0);	/* clear IRQ */
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	spin_unlock_irqrestore(&chip->reg_lock, flags);

	chip->mode = 0;
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	mutex_unlock(&chip->open_mutex);
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}

/*
 *  timer open/close
 */

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static int snd_wss_timer_open(struct snd_timer *timer)
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{
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	struct snd_wss *chip = snd_timer_chip(timer);
	snd_wss_open(chip, WSS_MODE_TIMER);
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	return 0;
}

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static int snd_wss_timer_close(struct snd_timer *timer)
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{
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	struct snd_wss *chip = snd_timer_chip(timer);
	snd_wss_close(chip, WSS_MODE_TIMER);
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	return 0;
}

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static struct snd_timer_hardware snd_wss_timer_table =
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{
	.flags =	SNDRV_TIMER_HW_AUTO,
	.resolution =	9945,
	.ticks =	65535,
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	.open =		snd_wss_timer_open,
	.close =	snd_wss_timer_close,
	.c_resolution = snd_wss_timer_resolution,
	.start =	snd_wss_timer_start,
	.stop =		snd_wss_timer_stop,
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};

/*
 *  ok.. exported functions..
 */

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static int snd_wss_playback_hw_params(struct snd_pcm_substream *substream,
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					 struct snd_pcm_hw_params *hw_params)
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{
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	struct snd_wss *chip = snd_pcm_substream_chip(substream);
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	unsigned char new_pdfr;
	int err;

	if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
		return err;
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	new_pdfr = snd_wss_get_format(chip, params_format(hw_params),
				params_channels(hw_params)) |
				snd_wss_get_rate(params_rate(hw_params));
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	chip->set_playback_format(chip, hw_params, new_pdfr);
	return 0;
}

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static int snd_wss_playback_hw_free(struct snd_pcm_substream *substream)
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{
	return snd_pcm_lib_free_pages(substream);
}

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static int snd_wss_playback_prepare(struct snd_pcm_substream *substream)
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{
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	struct snd_wss *chip = snd_pcm_substream_chip(substream);
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	struct snd_pcm_runtime *runtime = substream->runtime;
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	unsigned long flags;
	unsigned int size = snd_pcm_lib_buffer_bytes(substream);
	unsigned int count = snd_pcm_lib_period_bytes(substream);

	spin_lock_irqsave(&chip->reg_lock, flags);
	chip->p_dma_size = size;
	chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO);
	snd_dma_program(chip->dma1, runtime->dma_addr, size, DMA_MODE_WRITE | DMA_AUTOINIT);
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	count = snd_wss_get_count(chip->image[CS4231_PLAYBK_FORMAT], count) - 1;