gtt.c 62.6 KB
Newer Older
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
/*
 * GTT virtualization
 *
 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 *
 * Authors:
 *    Zhi Wang <zhi.a.wang@intel.com>
 *    Zhenyu Wang <zhenyuw@linux.intel.com>
 *    Xiao Zheng <xiao.zheng@intel.com>
 *
 * Contributors:
 *    Min He <min.he@intel.com>
 *    Bing Niu <bing.niu@intel.com>
 *
 */

#include "i915_drv.h"
37 38
#include "gvt.h"
#include "i915_pvinfo.h"
39 40
#include "trace.h"

41 42 43 44 45 46
#if defined(VERBOSE_DEBUG)
#define gvt_vdbg_mm(fmt, args...) gvt_dbg_mm(fmt, ##args)
#else
#define gvt_vdbg_mm(fmt, args...)
#endif

47 48 49 50 51 52 53 54 55 56 57
static bool enable_out_of_sync = false;
static int preallocated_oos_pages = 8192;

/*
 * validate a gm address and related range size,
 * translate it to host gm address
 */
bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size)
{
	if ((!vgpu_gmadr_is_valid(vgpu, addr)) || (size
			&& !vgpu_gmadr_is_valid(vgpu, addr + size - 1))) {
58 59
		gvt_vgpu_err("invalid range gmadr 0x%llx size 0x%x\n",
				addr, size);
60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102
		return false;
	}
	return true;
}

/* translate a guest gmadr to host gmadr */
int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr)
{
	if (WARN(!vgpu_gmadr_is_valid(vgpu, g_addr),
		 "invalid guest gmadr %llx\n", g_addr))
		return -EACCES;

	if (vgpu_gmadr_is_aperture(vgpu, g_addr))
		*h_addr = vgpu_aperture_gmadr_base(vgpu)
			  + (g_addr - vgpu_aperture_offset(vgpu));
	else
		*h_addr = vgpu_hidden_gmadr_base(vgpu)
			  + (g_addr - vgpu_hidden_offset(vgpu));
	return 0;
}

/* translate a host gmadr to guest gmadr */
int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr)
{
	if (WARN(!gvt_gmadr_is_valid(vgpu->gvt, h_addr),
		 "invalid host gmadr %llx\n", h_addr))
		return -EACCES;

	if (gvt_gmadr_is_aperture(vgpu->gvt, h_addr))
		*g_addr = vgpu_aperture_gmadr_base(vgpu)
			+ (h_addr - gvt_aperture_gmadr_base(vgpu->gvt));
	else
		*g_addr = vgpu_hidden_gmadr_base(vgpu)
			+ (h_addr - gvt_hidden_gmadr_base(vgpu->gvt));
	return 0;
}

int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu, unsigned long g_index,
			     unsigned long *h_index)
{
	u64 h_addr;
	int ret;

103
	ret = intel_gvt_ggtt_gmadr_g2h(vgpu, g_index << I915_GTT_PAGE_SHIFT,
104 105 106 107
				       &h_addr);
	if (ret)
		return ret;

108
	*h_index = h_addr >> I915_GTT_PAGE_SHIFT;
109 110 111 112 113 114 115 116 117
	return 0;
}

int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index,
			     unsigned long *g_index)
{
	u64 g_addr;
	int ret;

118
	ret = intel_gvt_ggtt_gmadr_h2g(vgpu, h_index << I915_GTT_PAGE_SHIFT,
119 120 121 122
				       &g_addr);
	if (ret)
		return ret;

123
	*g_index = g_addr >> I915_GTT_PAGE_SHIFT;
124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164
	return 0;
}

#define gtt_type_is_entry(type) \
	(type > GTT_TYPE_INVALID && type < GTT_TYPE_PPGTT_ENTRY \
	 && type != GTT_TYPE_PPGTT_PTE_ENTRY \
	 && type != GTT_TYPE_PPGTT_ROOT_ENTRY)

#define gtt_type_is_pt(type) \
	(type >= GTT_TYPE_PPGTT_PTE_PT && type < GTT_TYPE_MAX)

#define gtt_type_is_pte_pt(type) \
	(type == GTT_TYPE_PPGTT_PTE_PT)

#define gtt_type_is_root_pointer(type) \
	(gtt_type_is_entry(type) && type > GTT_TYPE_PPGTT_ROOT_ENTRY)

#define gtt_init_entry(e, t, p, v) do { \
	(e)->type = t; \
	(e)->pdev = p; \
	memcpy(&(e)->val64, &v, sizeof(v)); \
} while (0)

/*
 * Mappings between GTT_TYPE* enumerations.
 * Following information can be found according to the given type:
 * - type of next level page table
 * - type of entry inside this level page table
 * - type of entry with PSE set
 *
 * If the given type doesn't have such a kind of information,
 * e.g. give a l4 root entry type, then request to get its PSE type,
 * give a PTE page table type, then request to get its next level page
 * table type, as we know l4 root entry doesn't have a PSE bit,
 * and a PTE page table doesn't have a next level page table type,
 * GTT_TYPE_INVALID will be returned. This is useful when traversing a
 * page table.
 */

struct gtt_type_table_entry {
	int entry_type;
165
	int pt_type;
166 167 168 169
	int next_pt_type;
	int pse_entry_type;
};

170
#define GTT_TYPE_TABLE_ENTRY(type, e_type, cpt_type, npt_type, pse_type) \
171 172
	[type] = { \
		.entry_type = e_type, \
173
		.pt_type = cpt_type, \
174 175 176 177 178 179 180
		.next_pt_type = npt_type, \
		.pse_entry_type = pse_type, \
	}

static struct gtt_type_table_entry gtt_type_table[] = {
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_ROOT_L4_ENTRY,
			GTT_TYPE_PPGTT_ROOT_L4_ENTRY,
181
			GTT_TYPE_INVALID,
182 183 184 185
			GTT_TYPE_PPGTT_PML4_PT,
			GTT_TYPE_INVALID),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PML4_PT,
			GTT_TYPE_PPGTT_PML4_ENTRY,
186
			GTT_TYPE_PPGTT_PML4_PT,
187 188 189 190
			GTT_TYPE_PPGTT_PDP_PT,
			GTT_TYPE_INVALID),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PML4_ENTRY,
			GTT_TYPE_PPGTT_PML4_ENTRY,
191
			GTT_TYPE_PPGTT_PML4_PT,
192 193 194 195
			GTT_TYPE_PPGTT_PDP_PT,
			GTT_TYPE_INVALID),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDP_PT,
			GTT_TYPE_PPGTT_PDP_ENTRY,
196
			GTT_TYPE_PPGTT_PDP_PT,
197 198 199 200
			GTT_TYPE_PPGTT_PDE_PT,
			GTT_TYPE_PPGTT_PTE_1G_ENTRY),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_ROOT_L3_ENTRY,
			GTT_TYPE_PPGTT_ROOT_L3_ENTRY,
201
			GTT_TYPE_INVALID,
202 203 204 205
			GTT_TYPE_PPGTT_PDE_PT,
			GTT_TYPE_PPGTT_PTE_1G_ENTRY),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDP_ENTRY,
			GTT_TYPE_PPGTT_PDP_ENTRY,
206
			GTT_TYPE_PPGTT_PDP_PT,
207 208 209 210
			GTT_TYPE_PPGTT_PDE_PT,
			GTT_TYPE_PPGTT_PTE_1G_ENTRY),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDE_PT,
			GTT_TYPE_PPGTT_PDE_ENTRY,
211
			GTT_TYPE_PPGTT_PDE_PT,
212 213 214 215
			GTT_TYPE_PPGTT_PTE_PT,
			GTT_TYPE_PPGTT_PTE_2M_ENTRY),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDE_ENTRY,
			GTT_TYPE_PPGTT_PDE_ENTRY,
216
			GTT_TYPE_PPGTT_PDE_PT,
217 218
			GTT_TYPE_PPGTT_PTE_PT,
			GTT_TYPE_PPGTT_PTE_2M_ENTRY),
219
	/* We take IPS bit as 'PSE' for PTE level. */
220 221
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_PT,
			GTT_TYPE_PPGTT_PTE_4K_ENTRY,
222
			GTT_TYPE_PPGTT_PTE_PT,
223
			GTT_TYPE_INVALID,
224
			GTT_TYPE_PPGTT_PTE_64K_ENTRY),
225 226
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_4K_ENTRY,
			GTT_TYPE_PPGTT_PTE_4K_ENTRY,
227
			GTT_TYPE_PPGTT_PTE_PT,
228
			GTT_TYPE_INVALID,
229 230 231 232 233 234
			GTT_TYPE_PPGTT_PTE_64K_ENTRY),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_64K_ENTRY,
			GTT_TYPE_PPGTT_PTE_4K_ENTRY,
			GTT_TYPE_PPGTT_PTE_PT,
			GTT_TYPE_INVALID,
			GTT_TYPE_PPGTT_PTE_64K_ENTRY),
235 236
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_2M_ENTRY,
			GTT_TYPE_PPGTT_PDE_ENTRY,
237
			GTT_TYPE_PPGTT_PDE_PT,
238 239 240 241
			GTT_TYPE_INVALID,
			GTT_TYPE_PPGTT_PTE_2M_ENTRY),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_1G_ENTRY,
			GTT_TYPE_PPGTT_PDP_ENTRY,
242
			GTT_TYPE_PPGTT_PDP_PT,
243 244 245 246 247
			GTT_TYPE_INVALID,
			GTT_TYPE_PPGTT_PTE_1G_ENTRY),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_GGTT_PTE,
			GTT_TYPE_GGTT_PTE,
			GTT_TYPE_INVALID,
248
			GTT_TYPE_INVALID,
249 250 251 252 253 254 255 256
			GTT_TYPE_INVALID),
};

static inline int get_next_pt_type(int type)
{
	return gtt_type_table[type].next_pt_type;
}

257 258 259 260 261
static inline int get_pt_type(int type)
{
	return gtt_type_table[type].pt_type;
}

262 263 264 265 266 267 268 269 270 271 272 273
static inline int get_entry_type(int type)
{
	return gtt_type_table[type].entry_type;
}

static inline int get_pse_type(int type)
{
	return gtt_type_table[type].pse_entry_type;
}

static u64 read_pte64(struct drm_i915_private *dev_priv, unsigned long index)
{
274
	void __iomem *addr = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + index;
275 276

	return readq(addr);
277 278
}

279
static void ggtt_invalidate(struct drm_i915_private *dev_priv)
280 281 282 283 284 285
{
	mmio_hw_access_pre(dev_priv);
	I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
	mmio_hw_access_post(dev_priv);
}

286 287 288
static void write_pte64(struct drm_i915_private *dev_priv,
		unsigned long index, u64 pte)
{
289
	void __iomem *addr = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + index;
290 291 292 293

	writeq(pte, addr);
}

294
static inline int gtt_get_entry64(void *pt,
295 296 297 298 299 300 301 302
		struct intel_gvt_gtt_entry *e,
		unsigned long index, bool hypervisor_access, unsigned long gpa,
		struct intel_vgpu *vgpu)
{
	const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
	int ret;

	if (WARN_ON(info->gtt_entry_size != 8))
303
		return -EINVAL;
304 305 306 307 308

	if (hypervisor_access) {
		ret = intel_gvt_hypervisor_read_gpa(vgpu, gpa +
				(index << info->gtt_entry_size_shift),
				&e->val64, 8);
309 310
		if (WARN_ON(ret))
			return ret;
311 312 313 314 315
	} else if (!pt) {
		e->val64 = read_pte64(vgpu->gvt->dev_priv, index);
	} else {
		e->val64 = *((u64 *)pt + index);
	}
316
	return 0;
317 318
}

319
static inline int gtt_set_entry64(void *pt,
320 321 322 323 324 325 326 327
		struct intel_gvt_gtt_entry *e,
		unsigned long index, bool hypervisor_access, unsigned long gpa,
		struct intel_vgpu *vgpu)
{
	const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
	int ret;

	if (WARN_ON(info->gtt_entry_size != 8))
328
		return -EINVAL;
329 330 331 332 333

	if (hypervisor_access) {
		ret = intel_gvt_hypervisor_write_gpa(vgpu, gpa +
				(index << info->gtt_entry_size_shift),
				&e->val64, 8);
334 335
		if (WARN_ON(ret))
			return ret;
336 337 338 339 340
	} else if (!pt) {
		write_pte64(vgpu->gvt->dev_priv, index, e->val64);
	} else {
		*((u64 *)pt + index) = e->val64;
	}
341
	return 0;
342 343 344 345
}

#define GTT_HAW 46

346 347
#define ADDR_1G_MASK	GENMASK_ULL(GTT_HAW - 1, 30)
#define ADDR_2M_MASK	GENMASK_ULL(GTT_HAW - 1, 21)
348
#define ADDR_64K_MASK	GENMASK_ULL(GTT_HAW - 1, 16)
349
#define ADDR_4K_MASK	GENMASK_ULL(GTT_HAW - 1, 12)
350 351 352 353 354 355

static unsigned long gen8_gtt_get_pfn(struct intel_gvt_gtt_entry *e)
{
	unsigned long pfn;

	if (e->type == GTT_TYPE_PPGTT_PTE_1G_ENTRY)
356
		pfn = (e->val64 & ADDR_1G_MASK) >> PAGE_SHIFT;
357
	else if (e->type == GTT_TYPE_PPGTT_PTE_2M_ENTRY)
358
		pfn = (e->val64 & ADDR_2M_MASK) >> PAGE_SHIFT;
359 360
	else if (e->type == GTT_TYPE_PPGTT_PTE_64K_ENTRY)
		pfn = (e->val64 & ADDR_64K_MASK) >> PAGE_SHIFT;
361
	else
362
		pfn = (e->val64 & ADDR_4K_MASK) >> PAGE_SHIFT;
363 364 365 366 367 368 369
	return pfn;
}

static void gen8_gtt_set_pfn(struct intel_gvt_gtt_entry *e, unsigned long pfn)
{
	if (e->type == GTT_TYPE_PPGTT_PTE_1G_ENTRY) {
		e->val64 &= ~ADDR_1G_MASK;
370
		pfn &= (ADDR_1G_MASK >> PAGE_SHIFT);
371 372
	} else if (e->type == GTT_TYPE_PPGTT_PTE_2M_ENTRY) {
		e->val64 &= ~ADDR_2M_MASK;
373
		pfn &= (ADDR_2M_MASK >> PAGE_SHIFT);
374 375 376
	} else if (e->type == GTT_TYPE_PPGTT_PTE_64K_ENTRY) {
		e->val64 &= ~ADDR_64K_MASK;
		pfn &= (ADDR_64K_MASK >> PAGE_SHIFT);
377 378
	} else {
		e->val64 &= ~ADDR_4K_MASK;
379
		pfn &= (ADDR_4K_MASK >> PAGE_SHIFT);
380 381
	}

382
	e->val64 |= (pfn << PAGE_SHIFT);
383 384 385 386 387 388 389 390 391
}

static bool gen8_gtt_test_pse(struct intel_gvt_gtt_entry *e)
{
	/* Entry doesn't have PSE bit. */
	if (get_pse_type(e->type) == GTT_TYPE_INVALID)
		return false;

	e->type = get_entry_type(e->type);
392
	if (!(e->val64 & _PAGE_PSE))
393 394
		return false;

395 396 397 398
	/* We don't support 64K entry yet, will remove this later. */
	if (get_pse_type(e->type) == GTT_TYPE_PPGTT_PTE_64K_ENTRY)
		return false;

399 400 401 402 403 404 405 406 407 408 409 410 411 412 413
	e->type = get_pse_type(e->type);
	return true;
}

static bool gen8_gtt_test_present(struct intel_gvt_gtt_entry *e)
{
	/*
	 * i915 writes PDP root pointer registers without present bit,
	 * it also works, so we need to treat root pointer entry
	 * specifically.
	 */
	if (e->type == GTT_TYPE_PPGTT_ROOT_L3_ENTRY
			|| e->type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY)
		return (e->val64 != 0);
	else
414
		return (e->val64 & _PAGE_PRESENT);
415 416 417 418
}

static void gtt_entry_clear_present(struct intel_gvt_gtt_entry *e)
{
419
	e->val64 &= ~_PAGE_PRESENT;
420 421
}

422 423
static void gtt_entry_set_present(struct intel_gvt_gtt_entry *e)
{
424
	e->val64 |= _PAGE_PRESENT;
425 426 427 428 429 430 431
}

/*
 * Per-platform GMA routines.
 */
static unsigned long gma_to_ggtt_pte_index(unsigned long gma)
{
432
	unsigned long x = (gma >> I915_GTT_PAGE_SHIFT);
433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455

	trace_gma_index(__func__, gma, x);
	return x;
}

#define DEFINE_PPGTT_GMA_TO_INDEX(prefix, ename, exp) \
static unsigned long prefix##_gma_to_##ename##_index(unsigned long gma) \
{ \
	unsigned long x = (exp); \
	trace_gma_index(__func__, gma, x); \
	return x; \
}

DEFINE_PPGTT_GMA_TO_INDEX(gen8, pte, (gma >> 12 & 0x1ff));
DEFINE_PPGTT_GMA_TO_INDEX(gen8, pde, (gma >> 21 & 0x1ff));
DEFINE_PPGTT_GMA_TO_INDEX(gen8, l3_pdp, (gma >> 30 & 0x3));
DEFINE_PPGTT_GMA_TO_INDEX(gen8, l4_pdp, (gma >> 30 & 0x1ff));
DEFINE_PPGTT_GMA_TO_INDEX(gen8, pml4, (gma >> 39 & 0x1ff));

static struct intel_gvt_gtt_pte_ops gen8_gtt_pte_ops = {
	.get_entry = gtt_get_entry64,
	.set_entry = gtt_set_entry64,
	.clear_present = gtt_entry_clear_present,
456
	.set_present = gtt_entry_set_present,
457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474
	.test_present = gen8_gtt_test_present,
	.test_pse = gen8_gtt_test_pse,
	.get_pfn = gen8_gtt_get_pfn,
	.set_pfn = gen8_gtt_set_pfn,
};

static struct intel_gvt_gtt_gma_ops gen8_gtt_gma_ops = {
	.gma_to_ggtt_pte_index = gma_to_ggtt_pte_index,
	.gma_to_pte_index = gen8_gma_to_pte_index,
	.gma_to_pde_index = gen8_gma_to_pde_index,
	.gma_to_l3_pdp_index = gen8_gma_to_l3_pdp_index,
	.gma_to_l4_pdp_index = gen8_gma_to_l4_pdp_index,
	.gma_to_pml4_index = gen8_gma_to_pml4_index,
};

/*
 * MM helpers.
 */
475 476 477
static void _ppgtt_get_root_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index,
		bool guest)
478
{
479
	struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
480

481
	GEM_BUG_ON(mm->type != INTEL_GVT_MM_PPGTT);
482

483 484 485 486
	entry->type = mm->ppgtt_mm.root_entry_type;
	pte_ops->get_entry(guest ? mm->ppgtt_mm.guest_pdps :
			   mm->ppgtt_mm.shadow_pdps,
			   entry, index, false, 0, mm->vgpu);
487

488
	pte_ops->test_pse(entry);
489 490
}

491 492
static inline void ppgtt_get_guest_root_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index)
493
{
494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548
	_ppgtt_get_root_entry(mm, entry, index, true);
}

static inline void ppgtt_get_shadow_root_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index)
{
	_ppgtt_get_root_entry(mm, entry, index, false);
}

static void _ppgtt_set_root_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index,
		bool guest)
{
	struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;

	pte_ops->set_entry(guest ? mm->ppgtt_mm.guest_pdps :
			   mm->ppgtt_mm.shadow_pdps,
			   entry, index, false, 0, mm->vgpu);
}

static inline void ppgtt_set_guest_root_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index)
{
	_ppgtt_set_root_entry(mm, entry, index, true);
}

static inline void ppgtt_set_shadow_root_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index)
{
	_ppgtt_set_root_entry(mm, entry, index, false);
}

static void ggtt_get_guest_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index)
{
	struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;

	GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);

	entry->type = GTT_TYPE_GGTT_PTE;
	pte_ops->get_entry(mm->ggtt_mm.virtual_ggtt, entry, index,
			   false, 0, mm->vgpu);
}

static void ggtt_set_guest_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index)
{
	struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;

	GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);

	pte_ops->set_entry(mm->ggtt_mm.virtual_ggtt, entry, index,
			   false, 0, mm->vgpu);
}

549 550 551 552 553 554 555 556 557 558
static void ggtt_get_host_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index)
{
	struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;

	GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);

	pte_ops->get_entry(NULL, entry, index, false, 0, mm->vgpu);
}

559 560 561 562 563 564
static void ggtt_set_host_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index)
{
	struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;

	GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);
565

566
	pte_ops->set_entry(NULL, entry, index, false, 0, mm->vgpu);
567 568 569 570 571
}

/*
 * PPGTT shadow page table helpers.
 */
572
static inline int ppgtt_spt_get_entry(
573 574 575 576 577 578 579
		struct intel_vgpu_ppgtt_spt *spt,
		void *page_table, int type,
		struct intel_gvt_gtt_entry *e, unsigned long index,
		bool guest)
{
	struct intel_gvt *gvt = spt->vgpu->gvt;
	struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
580
	int ret;
581 582 583 584

	e->type = get_entry_type(type);

	if (WARN(!gtt_type_is_entry(e->type), "invalid entry type\n"))
585
		return -EINVAL;
586

587
	ret = ops->get_entry(page_table, e, index, guest,
588
			spt->guest_page.gfn << I915_GTT_PAGE_SHIFT,
589
			spt->vgpu);
590 591 592
	if (ret)
		return ret;

593
	ops->test_pse(e);
594 595 596

	gvt_vdbg_mm("read ppgtt entry, spt type %d, entry type %d, index %lu, value %llx\n",
		    type, e->type, index, e->val64);
597
	return 0;
598 599
}

600
static inline int ppgtt_spt_set_entry(
601 602 603 604 605 606 607 608 609
		struct intel_vgpu_ppgtt_spt *spt,
		void *page_table, int type,
		struct intel_gvt_gtt_entry *e, unsigned long index,
		bool guest)
{
	struct intel_gvt *gvt = spt->vgpu->gvt;
	struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;

	if (WARN(!gtt_type_is_entry(e->type), "invalid entry type\n"))
610
		return -EINVAL;
611

612 613 614
	gvt_vdbg_mm("set ppgtt entry, spt type %d, entry type %d, index %lu, value %llx\n",
		    type, e->type, index, e->val64);

615
	return ops->set_entry(page_table, e, index, guest,
616
			spt->guest_page.gfn << I915_GTT_PAGE_SHIFT,
617 618 619 620 621
			spt->vgpu);
}

#define ppgtt_get_guest_entry(spt, e, index) \
	ppgtt_spt_get_entry(spt, NULL, \
622
		spt->guest_page.type, e, index, true)
623 624 625

#define ppgtt_set_guest_entry(spt, e, index) \
	ppgtt_spt_set_entry(spt, NULL, \
626
		spt->guest_page.type, e, index, true)
627 628 629 630 631 632 633 634 635

#define ppgtt_get_shadow_entry(spt, e, index) \
	ppgtt_spt_get_entry(spt, spt->shadow_page.vaddr, \
		spt->shadow_page.type, e, index, false)

#define ppgtt_set_shadow_entry(spt, e, index) \
	ppgtt_spt_set_entry(spt, spt->shadow_page.vaddr, \
		spt->shadow_page.type, e, index, false)

636
static void *alloc_spt(gfp_t gfp_mask)
637
{
638
	struct intel_vgpu_ppgtt_spt *spt;
639

640 641 642
	spt = kzalloc(sizeof(*spt), gfp_mask);
	if (!spt)
		return NULL;
643

644 645 646 647 648 649
	spt->shadow_page.page = alloc_page(gfp_mask);
	if (!spt->shadow_page.page) {
		kfree(spt);
		return NULL;
	}
	return spt;
650 651
}

652
static void free_spt(struct intel_vgpu_ppgtt_spt *spt)
653
{
654 655
	__free_page(spt->shadow_page.page);
	kfree(spt);
656 657
}

658 659 660
static int detach_oos_page(struct intel_vgpu *vgpu,
		struct intel_vgpu_oos_page *oos_page);

661
static void ppgtt_free_spt(struct intel_vgpu_ppgtt_spt *spt)
662
{
663
	struct device *kdev = &spt->vgpu->gvt->dev_priv->drm.pdev->dev;
664

665
	trace_spt_free(spt->vgpu->id, spt, spt->guest_page.type);
666

667 668
	dma_unmap_page(kdev, spt->shadow_page.mfn << I915_GTT_PAGE_SHIFT, 4096,
		       PCI_DMA_BIDIRECTIONAL);
669 670

	radix_tree_delete(&spt->vgpu->gtt.spt_tree, spt->shadow_page.mfn);
671

672 673
	if (spt->guest_page.oos_page)
		detach_oos_page(spt->vgpu, spt->guest_page.oos_page);
674

675
	intel_vgpu_unregister_page_track(spt->vgpu, spt->guest_page.gfn);
676 677 678 679 680

	list_del_init(&spt->post_shadow_list);
	free_spt(spt);
}

681
static void ppgtt_free_all_spt(struct intel_vgpu *vgpu)
682
{
683
	struct intel_vgpu_ppgtt_spt *spt;
684 685
	struct radix_tree_iter iter;
	void **slot;
686

687 688
	radix_tree_for_each_slot(slot, &vgpu->gtt.spt_tree, &iter, 0) {
		spt = radix_tree_deref_slot(slot);
689
		ppgtt_free_spt(spt);
690
	}
691 692
}

693
static int ppgtt_handle_guest_write_page_table_bytes(
694
		struct intel_vgpu_ppgtt_spt *spt,
695 696
		u64 pa, void *p_data, int bytes);

697 698 699
static int ppgtt_write_protection_handler(
		struct intel_vgpu_page_track *page_track,
		u64 gpa, void *data, int bytes)
700
{
701 702
	struct intel_vgpu_ppgtt_spt *spt = page_track->priv_data;

703 704 705 706 707
	int ret;

	if (bytes != 4 && bytes != 8)
		return -EINVAL;

708
	ret = ppgtt_handle_guest_write_page_table_bytes(spt, gpa, data, bytes);
709 710 711 712 713
	if (ret)
		return ret;
	return ret;
}

714 715 716 717 718 719
/* Find a spt by guest gfn. */
static struct intel_vgpu_ppgtt_spt *intel_vgpu_find_spt_by_gfn(
		struct intel_vgpu *vgpu, unsigned long gfn)
{
	struct intel_vgpu_page_track *track;

720 721 722
	track = intel_vgpu_find_page_track(vgpu, gfn);
	if (track && track->handler == ppgtt_write_protection_handler)
		return track->priv_data;
723 724 725 726 727

	return NULL;
}

/* Find the spt by shadow page mfn. */
728
static inline struct intel_vgpu_ppgtt_spt *intel_vgpu_find_spt_by_mfn(
729 730
		struct intel_vgpu *vgpu, unsigned long mfn)
{
731
	return radix_tree_lookup(&vgpu->gtt.spt_tree, mfn);
732 733
}

734
static int reclaim_one_ppgtt_mm(struct intel_gvt *gvt);
735

736
static struct intel_vgpu_ppgtt_spt *ppgtt_alloc_spt(
737 738
		struct intel_vgpu *vgpu, int type, unsigned long gfn)
{
739
	struct device *kdev = &vgpu->gvt->dev_priv->drm.pdev->dev;
740
	struct intel_vgpu_ppgtt_spt *spt = NULL;
741
	dma_addr_t daddr;
742
	int ret;
743 744 745 746

retry:
	spt = alloc_spt(GFP_KERNEL | __GFP_ZERO);
	if (!spt) {
747
		if (reclaim_one_ppgtt_mm(vgpu->gvt))
748 749
			goto retry;

750
		gvt_vgpu_err("fail to allocate ppgtt shadow page\n");
751 752 753 754 755 756 757 758
		return ERR_PTR(-ENOMEM);
	}

	spt->vgpu = vgpu;
	atomic_set(&spt->refcount, 1);
	INIT_LIST_HEAD(&spt->post_shadow_list);

	/*
759
	 * Init shadow_page.
760
	 */
761 762 763 764 765
	spt->shadow_page.type = type;
	daddr = dma_map_page(kdev, spt->shadow_page.page,
			     0, 4096, PCI_DMA_BIDIRECTIONAL);
	if (dma_mapping_error(kdev, daddr)) {
		gvt_vgpu_err("fail to map dma addr\n");
766 767
		ret = -EINVAL;
		goto err_free_spt;
768
	}
769 770
	spt->shadow_page.vaddr = page_address(spt->shadow_page.page);
	spt->shadow_page.mfn = daddr >> I915_GTT_PAGE_SHIFT;
771

772 773 774 775 776
	/*
	 * Init guest_page.
	 */
	spt->guest_page.type = type;
	spt->guest_page.gfn = gfn;
777

778 779
	ret = intel_vgpu_register_page_track(vgpu, spt->guest_page.gfn,
					ppgtt_write_protection_handler, spt);
780 781
	if (ret)
		goto err_unmap_dma;
782

783 784 785
	ret = radix_tree_insert(&vgpu->gtt.spt_tree, spt->shadow_page.mfn, spt);
	if (ret)
		goto err_unreg_page_track;
786

787 788
	trace_spt_alloc(vgpu->id, spt, type, spt->shadow_page.mfn, gfn);
	return spt;
789 790 791 792 793 794 795 796

err_unreg_page_track:
	intel_vgpu_unregister_page_track(vgpu, spt->guest_page.gfn);
err_unmap_dma:
	dma_unmap_page(kdev, daddr, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
err_free_spt:
	free_spt(spt);
	return ERR_PTR(ret);
797 798 799 800 801 802
}

#define pt_entry_size_shift(spt) \
	((spt)->vgpu->gvt->device_info.gtt_entry_size_shift)

#define pt_entries(spt) \
803
	(I915_GTT_PAGE_SIZE >> pt_entry_size_shift(spt))
804 805 806

#define for_each_present_guest_entry(spt, e, i) \
	for (i = 0; i < pt_entries(spt); i++) \
807 808
		if (!ppgtt_get_guest_entry(spt, e, i) && \
		    spt->vgpu->gvt->gtt.pte_ops->test_present(e))
809 810 811

#define for_each_present_shadow_entry(spt, e, i) \
	for (i = 0; i < pt_entries(spt); i++) \
812 813
		if (!ppgtt_get_shadow_entry(spt, e, i) && \
		    spt->vgpu->gvt->gtt.pte_ops->test_present(e))
814

815
static void ppgtt_get_spt(struct intel_vgpu_ppgtt_spt *spt)
816 817 818 819 820 821 822 823
{
	int v = atomic_read(&spt->refcount);

	trace_spt_refcount(spt->vgpu->id, "inc", spt, v, (v + 1));

	atomic_inc(&spt->refcount);
}

824
static int ppgtt_invalidate_spt(struct intel_vgpu_ppgtt_spt *spt);
825

826
static int ppgtt_invalidate_spt_by_shadow_entry(struct intel_vgpu *vgpu,
827 828 829 830
		struct intel_gvt_gtt_entry *e)
{
	struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
	struct intel_vgpu_ppgtt_spt *s;
831
	intel_gvt_gtt_type_t cur_pt_type;
832

833
	GEM_BUG_ON(!gtt_type_is_pt(get_next_pt_type(e->type)));
834

835 836 837 838 839 840 841
	if (e->type != GTT_TYPE_PPGTT_ROOT_L3_ENTRY
		&& e->type != GTT_TYPE_PPGTT_ROOT_L4_ENTRY) {
		cur_pt_type = get_next_pt_type(e->type) + 1;
		if (ops->get_pfn(e) ==
			vgpu->gtt.scratch_pt[cur_pt_type].page_mfn)
			return 0;
	}
842
	s = intel_vgpu_find_spt_by_mfn(vgpu, ops->get_pfn(e));
843
	if (!s) {
844 845
		gvt_vgpu_err("fail to find shadow page: mfn: 0x%lx\n",
				ops->get_pfn(e));
846 847
		return -ENXIO;
	}
848
	return ppgtt_invalidate_spt(s);
849 850
}

851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867
static inline void ppgtt_invalidate_pte(struct intel_vgpu_ppgtt_spt *spt,
		struct intel_gvt_gtt_entry *entry)
{
	struct intel_vgpu *vgpu = spt->vgpu;
	struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
	unsigned long pfn;
	int type;

	pfn = ops->get_pfn(entry);
	type = spt->shadow_page.type;

	if (pfn == vgpu->gtt.scratch_pt[type].page_mfn)
		return;

	intel_gvt_hypervisor_dma_unmap_guest_page(vgpu, pfn << PAGE_SHIFT);
}

868
static int ppgtt_invalidate_spt(struct intel_vgpu_ppgtt_spt *spt)
869
{
870
	struct intel_vgpu *vgpu = spt->vgpu;
871 872 873 874 875 876
	struct intel_gvt_gtt_entry e;
	unsigned long index;
	int ret;
	int v = atomic_read(&spt->refcount);

	trace_spt_change(spt->vgpu->id, "die", spt,
877
			spt->guest_page.gfn, spt->shadow_page.type);
878 879 880 881 882 883 884

	trace_spt_refcount(spt->vgpu->id, "dec", spt, v, (v - 1));

	if (atomic_dec_return(&spt->refcount) > 0)
		return 0;

	for_each_present_shadow_entry(spt, &e, index) {
885 886 887
		switch (e.type) {
		case GTT_TYPE_PPGTT_PTE_4K_ENTRY:
			gvt_vdbg_mm("invalidate 4K entry\n");
888 889
			ppgtt_invalidate_pte(spt, &e);
			break;
890
		case GTT_TYPE_PPGTT_PTE_64K_ENTRY:
891 892
		case GTT_TYPE_PPGTT_PTE_2M_ENTRY:
		case GTT_TYPE_PPGTT_PTE_1G_ENTRY:
893
			WARN(1, "GVT doesn't support 64K/2M/1GB page\n");
894 895 896 897 898
			continue;
		case GTT_TYPE_PPGTT_PML4_ENTRY:
		case GTT_TYPE_PPGTT_PDP_ENTRY:
		case GTT_TYPE_PPGTT_PDE_ENTRY:
			gvt_vdbg_mm("invalidate PMUL4/PDP/PDE entry\n");
899
			ret = ppgtt_invalidate_spt_by_shadow_entry(
900 901 902 903 904 905
					spt->vgpu, &e);
			if (ret)
				goto fail;
			break;
		default:
			GEM_BUG_ON(1);
906 907
		}
	}
908

909
	trace_spt_change(spt->vgpu->id, "release", spt,
910
			 spt->guest_page.gfn, spt->shadow_page.type);
911
	ppgtt_free_spt(spt);
912 913
	return 0;
fail:
914 915
	gvt_vgpu_err("fail: shadow page %p shadow entry 0x%llx type %d\n",
			spt, e.val64, e.type);
916 917 918
	return ret;
}

919
static int ppgtt_populate_spt(struct intel_vgpu_ppgtt_spt *spt);
920

921
static struct intel_vgpu_ppgtt_spt *ppgtt_populate_spt_by_guest_entry(
922 923 924
		struct intel_vgpu *vgpu, struct intel_gvt_gtt_entry *we)
{
	struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
925
	struct intel_vgpu_ppgtt_spt *spt = NULL;
926 927
	int ret;

928
	GEM_BUG_ON(!gtt_type_is_pt(get_next_pt_type(we->type)));
929

930 931
	spt = intel_vgpu_find_spt_by_gfn(vgpu, ops->get_pfn(we));
	if (spt)
932
		ppgtt_get_spt(spt);
933
	else {
934 935
		int type = get_next_pt_type(we->type);

936
		spt = ppgtt_alloc_spt(vgpu, type, ops->get_pfn(we));
937 938
		if (IS_ERR(spt)) {
			ret = PTR_ERR(spt);
939 940 941
			goto fail;
		}

942
		ret = intel_vgpu_enable_page_track(vgpu, spt->guest_page.gfn);
943 944 945
		if (ret)
			goto fail;

946
		ret = ppgtt_populate_spt(spt);
947 948 949
		if (ret)
			goto fail;

950 951
		trace_spt_change(vgpu->id, "new", spt, spt->guest_page.gfn,
				 spt->shadow_page.type);
952
	}
953
	return spt;
954
fail:
955
	gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n",
956
		     spt, we->val64, we->type);
957 958 959 960 961 962 963 964 965 966 967 968 969 970
	return ERR_PTR(ret);
}

static inline void ppgtt_generate_shadow_entry(struct intel_gvt_gtt_entry *se,
		struct intel_vgpu_ppgtt_spt *s, struct intel_gvt_gtt_entry *ge)
{
	struct intel_gvt_gtt_pte_ops *ops = s->vgpu->gvt->gtt.pte_ops;

	se->type = ge->type;
	se->val64 = ge->val64;

	ops->set_pfn(se, s->shadow_page.mfn);
}

971 972 973 974 975 976
static int ppgtt_populate_shadow_entry(struct intel_vgpu *vgpu,
	struct intel_vgpu_ppgtt_spt *spt, unsigned long index,
	struct intel_gvt_gtt_entry *ge)
{
	struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
	struct intel_gvt_gtt_entry se = *ge;
977 978 979
	unsigned long gfn;
	dma_addr_t dma_addr;
	int ret;
980 981 982 983 984 985 986 987 988 989

	if (!pte_ops->test_present(ge))
		return 0;

	gfn = pte_ops->get_pfn(ge);

	switch (ge->type) {
	case GTT_TYPE_PPGTT_PTE_4K_ENTRY:
		gvt_vdbg_mm("shadow 4K gtt entry\n");
		break;
990
	case GTT_TYPE_PPGTT_PTE_64K_ENTRY:
991 992
	case GTT_TYPE_PPGTT_PTE_2M_ENTRY:
	case GTT_TYPE_PPGTT_PTE_1G_ENTRY:
993
		gvt_vgpu_err("GVT doesn't support 64K/2M/1GB entry\n");
994 995 996 997 998 999
		return -EINVAL;
	default:
		GEM_BUG_ON(1);
	};

	/* direct shadow */
1000 1001
	ret = intel_gvt_hypervisor_dma_map_guest_page(vgpu, gfn, &dma_addr);
	if (ret)
1002 1003
		return -ENXIO;

1004
	pte_ops->set_pfn(&se, dma_addr >> PAGE_SHIFT);
1005 1006 1007 1008
	ppgtt_set_shadow_entry(spt, &se, index);
	return 0;
}

1009
static int ppgtt_populate_spt(struct intel_vgpu_ppgtt_spt *spt)
1010 1011
{
	struct intel_vgpu *vgpu = spt->vgpu;
1012 1013
	struct intel_gvt *gvt = vgpu->gvt;
	struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
1014 1015
	struct intel_vgpu_ppgtt_spt *s;
	struct intel_gvt_gtt_entry se, ge;
1016
	unsigned long gfn, i;
1017 1018 1019
	int ret;

	trace_spt_change(spt->vgpu->id, "born", spt,
1020
			 spt->guest_page.gfn, spt->shadow_page.type);
1021

1022 1023
	for_each_present_guest_entry(spt, &ge, i) {
		if (gtt_type_is_pt(get_next_pt_type(ge.type))) {
1024
			s = ppgtt_populate_spt_by_guest_entry(vgpu, &ge);
1025 1026 1027 1028 1029 1030 1031 1032
			if (IS_ERR(s)) {
				ret = PTR_ERR(s);
				goto fail;
			}
			ppgtt_get_shadow_entry(spt, &se, i);
			ppgtt_generate_shadow_entry(&se, s, &ge);
			ppgtt_set_shadow_entry(spt, &se, i);
		} else {
1033
			gfn = ops->get_pfn(&ge);
1034
			if (!intel_gvt_hypervisor_is_valid_gfn(vgpu, gfn)) {
1035
				ops->set_pfn(&se, gvt->gtt.scratch_mfn);
1036 1037 1038
				ppgtt_set_shadow_entry(spt, &se, i);
				continue;
			}
1039

1040 1041 1042
			ret = ppgtt_populate_shadow_entry(vgpu, spt, i, &ge);
			if (ret)
				goto fail;
1043 1044 1045 1046
		}
	}
	return 0;
fail:
1047 1048
	gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n",
			spt, ge.val64, ge.type);
1049 1050 1051
	return ret;
}

1052
static int ppgtt_handle_guest_entry_removal(struct intel_vgpu_ppgtt_spt *spt,
1053
		struct intel_gvt_gtt_entry *se, unsigned long index)
1054 1055 1056 1057 1058
{
	struct intel_vgpu *vgpu = spt->vgpu;
	struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
	int ret;

1059 1060
	trace_spt_guest_change(spt->vgpu->id, "remove", spt,
			       spt->shadow_page.type, se->val64, index);
1061

1062 1063 1064
	gvt_vdbg_mm("destroy old shadow entry, type %d, index %lu, value %llx\n",
		    se->type, index, se->val64);

1065
	if (!ops->test_present(se))
1066 1067
		return 0;

1068 1069
	if (ops->get_pfn(se) ==
	    vgpu->gtt.scratch_pt[spt->shadow_page.type].page_mfn)
1070 1071
		return 0;

1072
	if (gtt_type_is_pt(get_next_pt_type(se->type))) {