rcar_du_crtc.c 30.3 KB
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// SPDX-License-Identifier: GPL-2.0+
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/*
 * rcar_du_crtc.c  --  R-Car Display Unit CRTCs
 *
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 * Copyright (C) 2013-2015 Renesas Electronics Corporation
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 *
 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
 */

#include <linux/clk.h>
#include <linux/mutex.h>
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#include <linux/sys_soc.h>
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#include <drm/drmP.h>
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#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
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#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_fb_cma_helper.h>
#include <drm/drm_gem_cma_helper.h>
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#include <drm/drm_plane_helper.h>
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#include "rcar_du_crtc.h"
#include "rcar_du_drv.h"
#include "rcar_du_kms.h"
#include "rcar_du_plane.h"
#include "rcar_du_regs.h"
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#include "rcar_du_vsp.h"
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static u32 rcar_du_crtc_read(struct rcar_du_crtc *rcrtc, u32 reg)
{
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	struct rcar_du_device *rcdu = rcrtc->group->dev;
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	return rcar_du_read(rcdu, rcrtc->mmio_offset + reg);
}

static void rcar_du_crtc_write(struct rcar_du_crtc *rcrtc, u32 reg, u32 data)
{
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	struct rcar_du_device *rcdu = rcrtc->group->dev;
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	rcar_du_write(rcdu, rcrtc->mmio_offset + reg, data);
}

static void rcar_du_crtc_clr(struct rcar_du_crtc *rcrtc, u32 reg, u32 clr)
{
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	struct rcar_du_device *rcdu = rcrtc->group->dev;
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	rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
		      rcar_du_read(rcdu, rcrtc->mmio_offset + reg) & ~clr);
}

static void rcar_du_crtc_set(struct rcar_du_crtc *rcrtc, u32 reg, u32 set)
{
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	struct rcar_du_device *rcdu = rcrtc->group->dev;
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	rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
		      rcar_du_read(rcdu, rcrtc->mmio_offset + reg) | set);
}

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void rcar_du_crtc_dsysr_clr_set(struct rcar_du_crtc *rcrtc, u32 clr, u32 set)
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{
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	struct rcar_du_device *rcdu = rcrtc->group->dev;
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	rcrtc->dsysr = (rcrtc->dsysr & ~clr) | set;
	rcar_du_write(rcdu, rcrtc->mmio_offset + DSYSR, rcrtc->dsysr);
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}

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/* -----------------------------------------------------------------------------
 * Hardware Setup
 */

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struct dpll_info {
	unsigned int output;
	unsigned int fdpll;
	unsigned int n;
	unsigned int m;
};

static void rcar_du_dpll_divider(struct rcar_du_crtc *rcrtc,
				 struct dpll_info *dpll,
				 unsigned long input,
				 unsigned long target)
{
	unsigned long best_diff = (unsigned long)-1;
	unsigned long diff;
	unsigned int fdpll;
	unsigned int m;
	unsigned int n;

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	/*
	 *   fin                                 fvco        fout       fclkout
	 * in --> [1/M] --> |PD| -> [LPF] -> [VCO] -> [1/P] -+-> [1/FDPLL] -> out
	 *              +-> |  |                             |
	 *              |                                    |
	 *              +---------------- [1/N] <------------+
	 *
	 *	fclkout = fvco / P / FDPLL -- (1)
	 *
	 * fin/M = fvco/P/N
	 *
	 *	fvco = fin * P *  N / M -- (2)
	 *
	 * (1) + (2) indicates
	 *
	 *	fclkout = fin * N / M / FDPLL
	 *
	 * NOTES
	 *	N	: (n + 1)
	 *	M	: (m + 1)
	 *	FDPLL	: (fdpll + 1)
	 *	P	: 2
	 *	2kHz < fvco < 4096MHz
	 *
	 * To minimize the jitter,
	 * N : as large as possible
	 * M : as small as possible
	 */
	for (m = 0; m < 4; m++) {
		for (n = 119; n > 38; n--) {
			/*
			 * This code only runs on 64-bit architectures, the
			 * unsigned long type can thus be used for 64-bit
			 * computation. It will still compile without any
			 * warning on 32-bit architectures.
			 *
			 * To optimize calculations, use fout instead of fvco
			 * to verify the VCO frequency constraint.
			 */
			unsigned long fout = input * (n + 1) / (m + 1);

			if (fout < 1000 || fout > 2048 * 1000 * 1000U)
				continue;

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			for (fdpll = 1; fdpll < 32; fdpll++) {
				unsigned long output;

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				output = fout / (fdpll + 1);
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				if (output >= 400 * 1000 * 1000)
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					continue;

				diff = abs((long)output - (long)target);
				if (best_diff > diff) {
					best_diff = diff;
					dpll->n = n;
					dpll->m = m;
					dpll->fdpll = fdpll;
					dpll->output = output;
				}

				if (diff == 0)
					goto done;
			}
		}
	}

done:
	dev_dbg(rcrtc->group->dev->dev,
		"output:%u, fdpll:%u, n:%u, m:%u, diff:%lu\n",
		 dpll->output, dpll->fdpll, dpll->n, dpll->m,
		 best_diff);
}

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struct du_clk_params {
	struct clk *clk;
	unsigned long rate;
	unsigned long diff;
	u32 escr;
};

static void rcar_du_escr_divider(struct clk *clk, unsigned long target,
				 u32 escr, struct du_clk_params *params)
{
	unsigned long rate;
	unsigned long diff;
	u32 div;

	/*
	 * If the target rate has already been achieved perfectly we can't do
	 * better.
	 */
	if (params->diff == 0)
		return;

	/*
	 * Compute the input clock rate and internal divisor values to obtain
	 * the clock rate closest to the target frequency.
	 */
	rate = clk_round_rate(clk, target);
	div = clamp(DIV_ROUND_CLOSEST(rate, target), 1UL, 64UL) - 1;
	diff = abs(rate / (div + 1) - target);

	/*
	 * Store the parameters if the resulting frequency is better than any
	 * previously calculated value.
	 */
	if (diff < params->diff) {
		params->clk = clk;
		params->rate = rate;
		params->diff = diff;
		params->escr = escr | div;
	}
}

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static const struct soc_device_attribute rcar_du_r8a7795_es1[] = {
	{ .soc_id = "r8a7795", .revision = "ES1.*" },
	{ /* sentinel */ }
};

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static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
{
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	const struct drm_display_mode *mode = &rcrtc->crtc.state->adjusted_mode;
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	struct rcar_du_device *rcdu = rcrtc->group->dev;
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	unsigned long mode_clock = mode->clock * 1000;
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	u32 dsmr;
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	u32 escr;
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	if (rcdu->info->dpll_mask & (1 << rcrtc->index)) {
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		unsigned long target = mode_clock;
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		struct dpll_info dpll = { 0 };
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		unsigned long extclk;
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		u32 dpllcr;
		u32 div = 0;

		/*
		 * DU channels that have a display PLL can't use the internal
		 * system clock, and have no internal clock divider.
		 */

		if (WARN_ON(!rcrtc->extclock))
			return;

		/*
		 * The H3 ES1.x exhibits dot clock duty cycle stability issues.
		 * We can work around them by configuring the DPLL to twice the
		 * desired frequency, coupled with a /2 post-divider. Restrict
		 * the workaround to H3 ES1.x as ES2.0 and all other SoCs have
		 * no post-divider when a display PLL is present (as shown by
		 * the workaround breaking HDMI output on M3-W during testing).
		 */
		if (soc_device_match(rcar_du_r8a7795_es1)) {
			target *= 2;
			div = 1;
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		}

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		extclk = clk_get_rate(rcrtc->extclock);
		rcar_du_dpll_divider(rcrtc, &dpll, extclk, target);

		dpllcr = DPLLCR_CODE | DPLLCR_CLKE
		       | DPLLCR_FDPLL(dpll.fdpll)
		       | DPLLCR_N(dpll.n) | DPLLCR_M(dpll.m)
		       | DPLLCR_STBY;

		if (rcrtc->index == 1)
			dpllcr |= DPLLCR_PLCS1
			       |  DPLLCR_INCS_DOTCLKIN1;
		else
			dpllcr |= DPLLCR_PLCS0
			       |  DPLLCR_INCS_DOTCLKIN0;

		rcar_du_group_write(rcrtc->group, DPLLCR, dpllcr);

		escr = ESCR_DCLKSEL_DCLKIN | div;
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	} else if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index)) {
		/*
		 * Use the LVDS PLL output as the dot clock when outputting to
		 * the LVDS encoder on an SoC that supports this clock routing
		 * option. We use the clock directly in that case, without any
		 * additional divider.
		 */
		escr = ESCR_DCLKSEL_DCLKIN;
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	} else {
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		struct du_clk_params params = { .diff = (unsigned long)-1 };
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		rcar_du_escr_divider(rcrtc->clock, mode_clock,
				     ESCR_DCLKSEL_CLKS, &params);
		if (rcrtc->extclock)
			rcar_du_escr_divider(rcrtc->extclock, mode_clock,
					     ESCR_DCLKSEL_DCLKIN, &params);
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		dev_dbg(rcrtc->group->dev->dev,	"mode clock %lu %s rate %lu\n",
			mode_clock, params.clk == rcrtc->clock ? "cpg" : "ext",
			params.rate);
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		clk_set_rate(params.clk, params.rate);
		escr = params.escr;
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	}
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	dev_dbg(rcrtc->group->dev->dev, "%s: ESCR 0x%08x\n", __func__, escr);

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	rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? ESCR13 : ESCR02, escr);
	rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? OTAR13 : OTAR02, 0);
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	/* Signal polarities */
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	dsmr = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? DSMR_VSL : 0)
	     | ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? DSMR_HSL : 0)
	     | ((mode->flags & DRM_MODE_FLAG_INTERLACE) ? DSMR_ODEV : 0)
	     | DSMR_DIPM_DISP | DSMR_CSPM;
	rcar_du_crtc_write(rcrtc, DSMR, dsmr);
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	/* Display timings */
	rcar_du_crtc_write(rcrtc, HDSR, mode->htotal - mode->hsync_start - 19);
	rcar_du_crtc_write(rcrtc, HDER, mode->htotal - mode->hsync_start +
					mode->hdisplay - 19);
	rcar_du_crtc_write(rcrtc, HSWR, mode->hsync_end -
					mode->hsync_start - 1);
	rcar_du_crtc_write(rcrtc, HCR,  mode->htotal - 1);

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	rcar_du_crtc_write(rcrtc, VDSR, mode->crtc_vtotal -
					mode->crtc_vsync_end - 2);
	rcar_du_crtc_write(rcrtc, VDER, mode->crtc_vtotal -
					mode->crtc_vsync_end +
					mode->crtc_vdisplay - 2);
	rcar_du_crtc_write(rcrtc, VSPR, mode->crtc_vtotal -
					mode->crtc_vsync_end +
					mode->crtc_vsync_start - 1);
	rcar_du_crtc_write(rcrtc, VCR,  mode->crtc_vtotal - 1);
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	rcar_du_crtc_write(rcrtc, DESR,  mode->htotal - mode->hsync_start - 1);
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	rcar_du_crtc_write(rcrtc, DEWR,  mode->hdisplay);
}

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void rcar_du_crtc_route_output(struct drm_crtc *crtc,
			       enum rcar_du_output output)
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{
	struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
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	struct rcar_du_device *rcdu = rcrtc->group->dev;
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	/*
	 * Store the route from the CRTC output to the DU output. The DU will be
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	 * configured when starting the CRTC.
	 */
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	rcrtc->outputs |= BIT(output);
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	/*
	 * Store RGB routing to DPAD0, the hardware will be configured when
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	 * starting the CRTC.
	 */
	if (output == RCAR_DU_OUTPUT_DPAD0)
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		rcdu->dpad0_source = rcrtc->index;
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}

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static unsigned int plane_zpos(struct rcar_du_plane *plane)
{
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	return plane->plane.state->normalized_zpos;
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}

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static const struct rcar_du_format_info *
plane_format(struct rcar_du_plane *plane)
{
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	return to_rcar_plane_state(plane->plane.state)->format;
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}

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static void rcar_du_crtc_update_planes(struct rcar_du_crtc *rcrtc)
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{
	struct rcar_du_plane *planes[RCAR_DU_NUM_HW_PLANES];
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	struct rcar_du_device *rcdu = rcrtc->group->dev;
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	unsigned int num_planes = 0;
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	unsigned int dptsr_planes;
	unsigned int hwplanes = 0;
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	unsigned int prio = 0;
	unsigned int i;
	u32 dspr = 0;

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	for (i = 0; i < rcrtc->group->num_planes; ++i) {
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		struct rcar_du_plane *plane = &rcrtc->group->planes[i];
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		unsigned int j;

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		if (plane->plane.state->crtc != &rcrtc->crtc ||
		    !plane->plane.state->visible)
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			continue;

		/* Insert the plane in the sorted planes array. */
		for (j = num_planes++; j > 0; --j) {
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			if (plane_zpos(planes[j-1]) <= plane_zpos(plane))
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				break;
			planes[j] = planes[j-1];
		}

		planes[j] = plane;
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		prio += plane_format(plane)->planes * 4;
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	}

	for (i = 0; i < num_planes; ++i) {
		struct rcar_du_plane *plane = planes[i];
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		struct drm_plane_state *state = plane->plane.state;
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		unsigned int index = to_rcar_plane_state(state)->hwindex;
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		prio -= 4;
		dspr |= (index + 1) << prio;
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		hwplanes |= 1 << index;
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		if (plane_format(plane)->planes == 2) {
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			index = (index + 1) % 8;

			prio -= 4;
			dspr |= (index + 1) << prio;
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			hwplanes |= 1 << index;
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		}
	}

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	/* If VSP+DU integration is enabled the plane assignment is fixed. */
	if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE)) {
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		if (rcdu->info->gen < 3) {
			dspr = (rcrtc->index % 2) + 1;
			hwplanes = 1 << (rcrtc->index % 2);
		} else {
			dspr = (rcrtc->index % 2) ? 3 : 1;
			hwplanes = 1 << ((rcrtc->index % 2) ? 2 : 0);
		}
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	}

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	/*
	 * Update the planes to display timing and dot clock generator
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	 * associations.
	 *
	 * Updating the DPTSR register requires restarting the CRTC group,
	 * resulting in visible flicker. To mitigate the issue only update the
	 * association if needed by enabled planes. Planes being disabled will
	 * keep their current association.
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	 */
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	mutex_lock(&rcrtc->group->lock);

	dptsr_planes = rcrtc->index % 2 ? rcrtc->group->dptsr_planes | hwplanes
		     : rcrtc->group->dptsr_planes & ~hwplanes;

	if (dptsr_planes != rcrtc->group->dptsr_planes) {
		rcar_du_group_write(rcrtc->group, DPTSR,
				    (dptsr_planes << 16) | dptsr_planes);
		rcrtc->group->dptsr_planes = dptsr_planes;

		if (rcrtc->group->used_crtcs)
			rcar_du_group_restart(rcrtc->group);
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	}

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	/* Restart the group if plane sources have changed. */
	if (rcrtc->group->need_restart)
		rcar_du_group_restart(rcrtc->group);

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	mutex_unlock(&rcrtc->group->lock);

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	rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR,
			    dspr);
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}

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/* -----------------------------------------------------------------------------
 * Page Flip
 */

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void rcar_du_crtc_finish_page_flip(struct rcar_du_crtc *rcrtc)
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{
	struct drm_pending_vblank_event *event;
	struct drm_device *dev = rcrtc->crtc.dev;
	unsigned long flags;

	spin_lock_irqsave(&dev->event_lock, flags);
	event = rcrtc->event;
	rcrtc->event = NULL;
	spin_unlock_irqrestore(&dev->event_lock, flags);

	if (event == NULL)
		return;

	spin_lock_irqsave(&dev->event_lock, flags);
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	drm_crtc_send_vblank_event(&rcrtc->crtc, event);
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	wake_up(&rcrtc->flip_wait);
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	spin_unlock_irqrestore(&dev->event_lock, flags);

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	drm_crtc_vblank_put(&rcrtc->crtc);
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}

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static bool rcar_du_crtc_page_flip_pending(struct rcar_du_crtc *rcrtc)
{
	struct drm_device *dev = rcrtc->crtc.dev;
	unsigned long flags;
	bool pending;

	spin_lock_irqsave(&dev->event_lock, flags);
	pending = rcrtc->event != NULL;
	spin_unlock_irqrestore(&dev->event_lock, flags);

	return pending;
}

static void rcar_du_crtc_wait_page_flip(struct rcar_du_crtc *rcrtc)
{
	struct rcar_du_device *rcdu = rcrtc->group->dev;

	if (wait_event_timeout(rcrtc->flip_wait,
			       !rcar_du_crtc_page_flip_pending(rcrtc),
			       msecs_to_jiffies(50)))
		return;

	dev_warn(rcdu->dev, "page flip timeout\n");

	rcar_du_crtc_finish_page_flip(rcrtc);
}

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/* -----------------------------------------------------------------------------
 * Start/Stop and Suspend/Resume
 */

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static void rcar_du_crtc_setup(struct rcar_du_crtc *rcrtc)
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{
	/* Set display off and background to black */
	rcar_du_crtc_write(rcrtc, DOOR, DOOR_RGB(0, 0, 0));
	rcar_du_crtc_write(rcrtc, BPOR, BPOR_RGB(0, 0, 0));

	/* Configure display timings and output routing */
	rcar_du_crtc_set_display_timing(rcrtc);
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	rcar_du_group_set_routing(rcrtc->group);
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	/* Start with all planes disabled. */
	rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR, 0);
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	/* Enable the VSP compositor. */
	if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
		rcar_du_vsp_enable(rcrtc);

	/* Turn vertical blanking interrupt reporting on. */
	drm_crtc_vblank_on(&rcrtc->crtc);
}

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static int rcar_du_crtc_get(struct rcar_du_crtc *rcrtc)
{
	int ret;

	/*
	 * Guard against double-get, as the function is called from both the
	 * .atomic_enable() and .atomic_begin() handlers.
	 */
	if (rcrtc->initialized)
		return 0;

	ret = clk_prepare_enable(rcrtc->clock);
	if (ret < 0)
		return ret;

	ret = clk_prepare_enable(rcrtc->extclock);
	if (ret < 0)
		goto error_clock;

	ret = rcar_du_group_get(rcrtc->group);
	if (ret < 0)
		goto error_group;

	rcar_du_crtc_setup(rcrtc);
	rcrtc->initialized = true;

	return 0;

error_group:
	clk_disable_unprepare(rcrtc->extclock);
error_clock:
	clk_disable_unprepare(rcrtc->clock);
	return ret;
}

static void rcar_du_crtc_put(struct rcar_du_crtc *rcrtc)
{
	rcar_du_group_put(rcrtc->group);

	clk_disable_unprepare(rcrtc->extclock);
	clk_disable_unprepare(rcrtc->clock);

	rcrtc->initialized = false;
}

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static void rcar_du_crtc_start(struct rcar_du_crtc *rcrtc)
{
	bool interlaced;

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	/*
	 * Select master sync mode. This enables display operation in master
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	 * sync mode (with the HSYNC and VSYNC signals configured as outputs and
	 * actively driven).
	 */
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	interlaced = rcrtc->crtc.mode.flags & DRM_MODE_FLAG_INTERLACE;
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	rcar_du_crtc_dsysr_clr_set(rcrtc, DSYSR_TVM_MASK | DSYSR_SCM_MASK,
				   (interlaced ? DSYSR_SCM_INT_VIDEO : 0) |
				   DSYSR_TVM_MASTER);
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	rcar_du_group_start_stop(rcrtc->group, true);
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}

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static void rcar_du_crtc_disable_planes(struct rcar_du_crtc *rcrtc)
{
	struct rcar_du_device *rcdu = rcrtc->group->dev;
	struct drm_crtc *crtc = &rcrtc->crtc;
	u32 status;

	/* Make sure vblank interrupts are enabled. */
	drm_crtc_vblank_get(crtc);

	/*
	 * Disable planes and calculate how many vertical blanking interrupts we
	 * have to wait for. If a vertical blanking interrupt has been triggered
	 * but not processed yet, we don't know whether it occurred before or
	 * after the planes got disabled. We thus have to wait for two vblank
	 * interrupts in that case.
	 */
	spin_lock_irq(&rcrtc->vblank_lock);
	rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR, 0);
	status = rcar_du_crtc_read(rcrtc, DSSR);
	rcrtc->vblank_count = status & DSSR_VBK ? 2 : 1;
	spin_unlock_irq(&rcrtc->vblank_lock);

	if (!wait_event_timeout(rcrtc->vblank_wait, rcrtc->vblank_count == 0,
				msecs_to_jiffies(100)))
		dev_warn(rcdu->dev, "vertical blanking timeout\n");

	drm_crtc_vblank_put(crtc);
}

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static void rcar_du_crtc_stop(struct rcar_du_crtc *rcrtc)
{
	struct drm_crtc *crtc = &rcrtc->crtc;

618 619
	/*
	 * Disable all planes and wait for the change to take effect. This is
620 621 622 623
	 * required as the plane enable registers are updated on vblank, and no
	 * vblank will occur once the CRTC is stopped. Disabling planes when
	 * starting the CRTC thus wouldn't be enough as it would start scanning
	 * out immediately from old frame buffers until the next vblank.
624 625 626 627 628
	 *
	 * This increases the CRTC stop delay, especially when multiple CRTCs
	 * are stopped in one operation as we now wait for one vblank per CRTC.
	 * Whether this can be improved needs to be researched.
	 */
629
	rcar_du_crtc_disable_planes(rcrtc);
630

631 632
	/*
	 * Disable vertical blanking interrupt reporting. We first need to wait
633 634
	 * for page flip completion before stopping the CRTC as userspace
	 * expects page flips to eventually complete.
635 636
	 */
	rcar_du_crtc_wait_page_flip(rcrtc);
637
	drm_crtc_vblank_off(crtc);
638

639 640 641 642
	/* Disable the VSP compositor. */
	if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
		rcar_du_vsp_disable(rcrtc);

643 644
	/*
	 * Select switch sync mode. This stops display operation and configures
645 646
	 * the HSYNC and VSYNC signals as inputs.
	 */
647
	rcar_du_crtc_dsysr_clr_set(rcrtc, DSYSR_TVM_MASK, DSYSR_TVM_SWITCH);
648

649
	rcar_du_group_start_stop(rcrtc->group, false);
650 651
}

652 653 654 655
/* -----------------------------------------------------------------------------
 * CRTC Functions
 */

656 657
static void rcar_du_crtc_atomic_enable(struct drm_crtc *crtc,
				       struct drm_crtc_state *old_state)
658 659 660
{
	struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);

661
	rcar_du_crtc_get(rcrtc);
662 663 664
	rcar_du_crtc_start(rcrtc);
}

665 666
static void rcar_du_crtc_atomic_disable(struct drm_crtc *crtc,
					struct drm_crtc_state *old_state)
667 668
{
	struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
669

670 671
	rcar_du_crtc_stop(rcrtc);
	rcar_du_crtc_put(rcrtc);
672

673 674 675 676 677 678 679
	spin_lock_irq(&crtc->dev->event_lock);
	if (crtc->state->event) {
		drm_crtc_send_vblank_event(crtc, crtc->state->event);
		crtc->state->event = NULL;
	}
	spin_unlock_irq(&crtc->dev->event_lock);

680
	rcrtc->outputs = 0;
681 682
}

683 684
static void rcar_du_crtc_atomic_begin(struct drm_crtc *crtc,
				      struct drm_crtc_state *old_crtc_state)
685 686
{
	struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
687

688 689 690 691
	WARN_ON(!crtc->state->enable);

	/*
	 * If a mode set is in progress we can be called with the CRTC disabled.
692 693 694 695 696 697 698 699 700
	 * We thus need to first get and setup the CRTC in order to configure
	 * planes. We must *not* put the CRTC in .atomic_flush(), as it must be
	 * kept awake until the .atomic_enable() call that will follow. The get
	 * operation in .atomic_enable() will in that case be a no-op, and the
	 * CRTC will be put later in .atomic_disable().
	 *
	 * If a mode set is not in progress the CRTC is enabled, and the
	 * following get call will be a no-op. There is thus no need to belance
	 * it in .atomic_flush() either.
701
	 */
702
	rcar_du_crtc_get(rcrtc);
703

704 705
	if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
		rcar_du_vsp_atomic_begin(rcrtc);
706 707
}

708 709
static void rcar_du_crtc_atomic_flush(struct drm_crtc *crtc,
				      struct drm_crtc_state *old_crtc_state)
710 711
{
	struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
712 713
	struct drm_device *dev = rcrtc->crtc.dev;
	unsigned long flags;
714

715
	rcar_du_crtc_update_planes(rcrtc);
716

717 718 719 720 721 722 723 724 725
	if (crtc->state->event) {
		WARN_ON(drm_crtc_vblank_get(crtc) != 0);

		spin_lock_irqsave(&dev->event_lock, flags);
		rcrtc->event = crtc->state->event;
		crtc->state->event = NULL;
		spin_unlock_irqrestore(&dev->event_lock, flags);
	}

726 727
	if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
		rcar_du_vsp_atomic_flush(rcrtc);
728 729
}

730 731 732 733 734 735 736 737 738 739 740 741 742
enum drm_mode_status rcar_du_crtc_mode_valid(struct drm_crtc *crtc,
				   const struct drm_display_mode *mode)
{
	struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
	struct rcar_du_device *rcdu = rcrtc->group->dev;
	bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;

	if (interlaced && !rcar_du_has(rcdu, RCAR_DU_FEATURE_INTERLACED))
		return MODE_NO_INTERLACE;

	return MODE_OK;
}

743
static const struct drm_crtc_helper_funcs crtc_helper_funcs = {
744 745
	.atomic_begin = rcar_du_crtc_atomic_begin,
	.atomic_flush = rcar_du_crtc_atomic_flush,
746
	.atomic_enable = rcar_du_crtc_atomic_enable,
747
	.atomic_disable = rcar_du_crtc_atomic_disable,
748
	.mode_valid = rcar_du_crtc_mode_valid,
749 750
};

751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809
static void rcar_du_crtc_crc_init(struct rcar_du_crtc *rcrtc)
{
	struct rcar_du_device *rcdu = rcrtc->group->dev;
	const char **sources;
	unsigned int count;
	int i = -1;

	/* CRC available only on Gen3 HW. */
	if (rcdu->info->gen < 3)
		return;

	/* Reserve 1 for "auto" source. */
	count = rcrtc->vsp->num_planes + 1;

	sources = kmalloc_array(count, sizeof(*sources), GFP_KERNEL);
	if (!sources)
		return;

	sources[0] = kstrdup("auto", GFP_KERNEL);
	if (!sources[0])
		goto error;

	for (i = 0; i < rcrtc->vsp->num_planes; ++i) {
		struct drm_plane *plane = &rcrtc->vsp->planes[i].plane;
		char name[16];

		sprintf(name, "plane%u", plane->base.id);
		sources[i + 1] = kstrdup(name, GFP_KERNEL);
		if (!sources[i + 1])
			goto error;
	}

	rcrtc->sources = sources;
	rcrtc->sources_count = count;
	return;

error:
	while (i >= 0) {
		kfree(sources[i]);
		i--;
	}
	kfree(sources);
}

static void rcar_du_crtc_crc_cleanup(struct rcar_du_crtc *rcrtc)
{
	unsigned int i;

	if (!rcrtc->sources)
		return;

	for (i = 0; i < rcrtc->sources_count; i++)
		kfree(rcrtc->sources[i]);
	kfree(rcrtc->sources);

	rcrtc->sources = NULL;
	rcrtc->sources_count = 0;
}

810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835
static struct drm_crtc_state *
rcar_du_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
{
	struct rcar_du_crtc_state *state;
	struct rcar_du_crtc_state *copy;

	if (WARN_ON(!crtc->state))
		return NULL;

	state = to_rcar_crtc_state(crtc->state);
	copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
	if (copy == NULL)
		return NULL;

	__drm_atomic_helper_crtc_duplicate_state(crtc, &copy->state);

	return &copy->state;
}

static void rcar_du_crtc_atomic_destroy_state(struct drm_crtc *crtc,
					      struct drm_crtc_state *state)
{
	__drm_atomic_helper_crtc_destroy_state(state);
	kfree(to_rcar_crtc_state(state));
}

836 837 838 839 840 841 842 843 844
static void rcar_du_crtc_cleanup(struct drm_crtc *crtc)
{
	struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);

	rcar_du_crtc_crc_cleanup(rcrtc);

	return drm_crtc_cleanup(crtc);
}

845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864
static void rcar_du_crtc_reset(struct drm_crtc *crtc)
{
	struct rcar_du_crtc_state *state;

	if (crtc->state) {
		rcar_du_crtc_atomic_destroy_state(crtc, crtc->state);
		crtc->state = NULL;
	}

	state = kzalloc(sizeof(*state), GFP_KERNEL);
	if (state == NULL)
		return;

	state->crc.source = VSP1_DU_CRC_NONE;
	state->crc.index = 0;

	crtc->state = &state->state;
	crtc->state->crtc = crtc;
}

865 866 867 868 869 870
static int rcar_du_crtc_enable_vblank(struct drm_crtc *crtc)
{
	struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);

	rcar_du_crtc_write(rcrtc, DSRCR, DSRCR_VBCL);
	rcar_du_crtc_set(rcrtc, DIER, DIER_VBE);
871
	rcrtc->vblank_enable = true;
872 873 874 875 876 877 878 879 880

	return 0;
}

static void rcar_du_crtc_disable_vblank(struct drm_crtc *crtc)
{
	struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);

	rcar_du_crtc_clr(rcrtc, DIER, DIER_VBE);
881
	rcrtc->vblank_enable = false;
882 883
}

884 885 886
static int rcar_du_crtc_parse_crc_source(struct rcar_du_crtc *rcrtc,
					 const char *source_name,
					 enum vsp1_du_crc_source *source)
887
{
888
	unsigned int index;
889 890 891 892 893 894 895
	int ret;

	/*
	 * Parse the source name. Supported values are "plane%u" to compute the
	 * CRC on an input plane (%u is the plane ID), and "auto" to compute the
	 * CRC on the composer (VSP) output.
	 */
896

897
	if (!source_name) {
898 899
		*source = VSP1_DU_CRC_NONE;
		return 0;
900
	} else if (!strcmp(source_name, "auto")) {
901 902
		*source = VSP1_DU_CRC_OUTPUT;
		return 0;
903
	} else if (strstarts(source_name, "plane")) {
904 905 906
		unsigned int i;

		*source = VSP1_DU_CRC_PLANE;
907 908 909 910 911 912

		ret = kstrtouint(source_name + strlen("plane"), 10, &index);
		if (ret < 0)
			return ret;

		for (i = 0; i < rcrtc->vsp->num_planes; ++i) {
913 914
			if (index == rcrtc->vsp->planes[i].plane.base.id)
				return i;
915
		}
916
	}
917

918 919 920 921 922 923 924 925 926 927 928 929
	return -EINVAL;
}

static int rcar_du_crtc_verify_crc_source(struct drm_crtc *crtc,
					  const char *source_name,
					  size_t *values_cnt)
{
	struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
	enum vsp1_du_crc_source source;

	if (rcar_du_crtc_parse_crc_source(rcrtc, source_name, &source) < 0) {
		DRM_DEBUG_DRIVER("unknown source %s\n", source_name);
930 931 932
		return -EINVAL;
	}

933 934 935 936
	*values_cnt = 1;
	return 0;
}

937 938 939 940 941 942 943 944 945
const char *const *rcar_du_crtc_get_crc_sources(struct drm_crtc *crtc,
						size_t *count)
{
	struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);

	*count = rcrtc->sources_count;
	return rcrtc->sources;
}

946
static int rcar_du_crtc_set_crc_source(struct drm_crtc *crtc,
947
				       const char *source_name)
948 949 950 951 952 953 954 955 956 957 958 959 960 961
{
	struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
	struct drm_modeset_acquire_ctx ctx;
	struct drm_crtc_state *crtc_state;
	struct drm_atomic_state *state;
	enum vsp1_du_crc_source source;
	unsigned int index;
	int ret;

	ret = rcar_du_crtc_parse_crc_source(rcrtc, source_name, &source);
	if (ret < 0)
		return ret;

	index = ret;
962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015

	/* Perform an atomic commit to set the CRC source. */
	drm_modeset_acquire_init(&ctx, 0);

	state = drm_atomic_state_alloc(crtc->dev);
	if (!state) {
		ret = -ENOMEM;
		goto unlock;
	}

	state->acquire_ctx = &ctx;

retry:
	crtc_state = drm_atomic_get_crtc_state(state, crtc);
	if (!IS_ERR(crtc_state)) {
		struct rcar_du_crtc_state *rcrtc_state;

		rcrtc_state = to_rcar_crtc_state(crtc_state);
		rcrtc_state->crc.source = source;
		rcrtc_state->crc.index = index;

		ret = drm_atomic_commit(state);
	} else {
		ret = PTR_ERR(crtc_state);
	}

	if (ret == -EDEADLK) {
		drm_atomic_state_clear(state);
		drm_modeset_backoff(&ctx);
		goto retry;
	}

	drm_atomic_state_put(state);

unlock:
	drm_modeset_drop_locks(&ctx);
	drm_modeset_acquire_fini(&ctx);

	return 0;
}

static const struct drm_crtc_funcs crtc_funcs_gen2 = {
	.reset = rcar_du_crtc_reset,
	.destroy = drm_crtc_cleanup,
	.set_config = drm_atomic_helper_set_config,
	.page_flip = drm_atomic_helper_page_flip,
	.atomic_duplicate_state = rcar_du_crtc_atomic_duplicate_state,
	.atomic_destroy_state = rcar_du_crtc_atomic_destroy_state,
	.enable_vblank = rcar_du_crtc_enable_vblank,
	.disable_vblank = rcar_du_crtc_disable_vblank,
};

static const struct drm_crtc_funcs crtc_funcs_gen3 = {
	.reset = rcar_du_crtc_reset,
1016
	.destroy = rcar_du_crtc_cleanup,
1017
	.set_config = drm_atomic_helper_set_config,
1018
	.page_flip = drm_atomic_helper_page_flip,
1019 1020
	.atomic_duplicate_state = rcar_du_crtc_atomic_duplicate_state,
	.atomic_destroy_state = rcar_du_crtc_atomic_destroy_state,
1021 1022
	.enable_vblank = rcar_du_crtc_enable_vblank,
	.disable_vblank = rcar_du_crtc_disable_vblank,
1023
	.set_crc_source = rcar_du_crtc_set_crc_source,
1024
	.verify_crc_source = rcar_du_crtc_verify_crc_source,
1025
	.get_crc_sources = rcar_du_crtc_get_crc_sources,
1026 1027
};

1028 1029 1030 1031 1032 1033 1034
/* -----------------------------------------------------------------------------
 * Interrupt Handling
 */

static irqreturn_t rcar_du_crtc_irq(int irq, void *arg)
{
	struct rcar_du_crtc *rcrtc = arg;
1035
	struct rcar_du_device *rcdu = rcrtc->group->dev;
1036 1037 1038
	irqreturn_t ret = IRQ_NONE;
	u32 status;

1039 1040
	spin_lock(&rcrtc->vblank_lock);

1041 1042 1043
	status = rcar_du_crtc_read(rcrtc, DSSR);
	rcar_du_crtc_write(rcrtc, DSRCR, status & DSRCR_MASK);

1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057
	if (status & DSSR_VBK) {
		/*
		 * Wake up the vblank wait if the counter reaches 0. This must
		 * be protected by the vblank_lock to avoid races in
		 * rcar_du_crtc_disable_planes().
		 */
		if (rcrtc->vblank_count) {
			if (--rcrtc->vblank_count == 0)
				wake_up(&rcrtc->vblank_wait);
		}
	}

	spin_unlock(&rcrtc->vblank_lock);

1058
	if (status & DSSR_VBK) {
1059 1060
		if (rcdu->info->gen < 3) {
			drm_crtc_handle_vblank(&rcrtc->crtc);
1061
			rcar_du_crtc_finish_page_flip(rcrtc);
1062
		}
1063

1064 1065 1066 1067 1068 1069 1070 1071 1072 1073
		ret = IRQ_HANDLED;
	}

	return ret;
}

/* -----------------------------------------------------------------------------
 * Initialization
 */

1074 1075
int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int swindex,
			unsigned int hwindex)
1076
{
1077
	static const unsigned int mmio_offsets[] = {
1078
		DU0_REG_OFFSET, DU1_REG_OFFSET, DU2_REG_OFFSET, DU3_REG_OFFSET
1079 1080
	};

1081
	struct rcar_du_device *rcdu = rgrp->dev;
1082
	struct platform_device *pdev = to_platform_device(rcdu->dev);
1083
	struct rcar_du_crtc *rcrtc = &rcdu->crtcs[swindex];
1084
	struct drm_crtc *crtc = &rcrtc->crtc;
1085
	struct drm_plane *primary;
1086
	unsigned int irqflags;
1087 1088
	struct clk *clk;
	char clk_name[9];
1089 1090
	char *name;
	int irq;
1091 1092
	int ret;

1093
	/* Get the CRTC clock and the optional external clock. */
1094
	if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
1095
		sprintf(clk_name, "du.%u", hwindex);
1096 1097 1098 1099 1100 1101 1102
		name = clk_name;
	} else {
		name = NULL;
	}

	rcrtc->clock = devm_clk_get(rcdu->dev, name);
	if (IS_ERR(rcrtc->clock)) {
1103
		dev_err(rcdu->dev, "no clock for DU channel %u\n", hwindex);
1104 1105 1106
		return PTR_ERR(rcrtc->clock);
	}

1107
	sprintf(clk_name, "dclkin.%u", hwindex);
1108 1109 1110 1111
	clk = devm_clk_get(rcdu->dev, clk_name);
	if (!IS_ERR(clk)) {
		rcrtc->extclock = clk;
	} else if (PTR_ERR(rcrtc->clock) == -EPROBE_DEFER) {
1112
		dev_info(rcdu->dev, "can't get external clock %u\n", hwindex);
1113 1114 1115
		return -EPROBE_DEFER;
	}

1116
	init_waitqueue_head(&rcrtc->flip_wait);
1117 1118
	init_waitqueue_head(&rcrtc->vblank_wait);
	spin_lock_init(&rcrtc->vblank_lock);
1119

1120
	rcrtc->group = rgrp;
1121 1122
	rcrtc->mmio_offset = mmio_offsets[hwindex];
	rcrtc->index = hwindex;
1123
	rcrtc->dsysr = (rcrtc->index % 2 ? 0 : DSYSR_DRES) | DSYSR_TVM_TVSYNC;
1124

1125
	if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE))
1126
		primary = &rcrtc->vsp->planes[rcrtc->vsp_pipe].plane;
1127
	else
1128
		primary = &rgrp->planes[swindex % 2].plane;