gtt.c 64.3 KB
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/*
 * GTT virtualization
 *
 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 *
 * Authors:
 *    Zhi Wang <zhi.a.wang@intel.com>
 *    Zhenyu Wang <zhenyuw@linux.intel.com>
 *    Xiao Zheng <xiao.zheng@intel.com>
 *
 * Contributors:
 *    Min He <min.he@intel.com>
 *    Bing Niu <bing.niu@intel.com>
 *
 */

#include "i915_drv.h"
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#include "gvt.h"
#include "i915_pvinfo.h"
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#include "trace.h"

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#if defined(VERBOSE_DEBUG)
#define gvt_vdbg_mm(fmt, args...) gvt_dbg_mm(fmt, ##args)
#else
#define gvt_vdbg_mm(fmt, args...)
#endif

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static bool enable_out_of_sync = false;
static int preallocated_oos_pages = 8192;

/*
 * validate a gm address and related range size,
 * translate it to host gm address
 */
bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size)
{
	if ((!vgpu_gmadr_is_valid(vgpu, addr)) || (size
			&& !vgpu_gmadr_is_valid(vgpu, addr + size - 1))) {
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		gvt_vgpu_err("invalid range gmadr 0x%llx size 0x%x\n",
				addr, size);
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		return false;
	}
	return true;
}

/* translate a guest gmadr to host gmadr */
int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr)
{
	if (WARN(!vgpu_gmadr_is_valid(vgpu, g_addr),
		 "invalid guest gmadr %llx\n", g_addr))
		return -EACCES;

	if (vgpu_gmadr_is_aperture(vgpu, g_addr))
		*h_addr = vgpu_aperture_gmadr_base(vgpu)
			  + (g_addr - vgpu_aperture_offset(vgpu));
	else
		*h_addr = vgpu_hidden_gmadr_base(vgpu)
			  + (g_addr - vgpu_hidden_offset(vgpu));
	return 0;
}

/* translate a host gmadr to guest gmadr */
int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr)
{
	if (WARN(!gvt_gmadr_is_valid(vgpu->gvt, h_addr),
		 "invalid host gmadr %llx\n", h_addr))
		return -EACCES;

	if (gvt_gmadr_is_aperture(vgpu->gvt, h_addr))
		*g_addr = vgpu_aperture_gmadr_base(vgpu)
			+ (h_addr - gvt_aperture_gmadr_base(vgpu->gvt));
	else
		*g_addr = vgpu_hidden_gmadr_base(vgpu)
			+ (h_addr - gvt_hidden_gmadr_base(vgpu->gvt));
	return 0;
}

int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu, unsigned long g_index,
			     unsigned long *h_index)
{
	u64 h_addr;
	int ret;

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	ret = intel_gvt_ggtt_gmadr_g2h(vgpu, g_index << I915_GTT_PAGE_SHIFT,
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				       &h_addr);
	if (ret)
		return ret;

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	*h_index = h_addr >> I915_GTT_PAGE_SHIFT;
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	return 0;
}

int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index,
			     unsigned long *g_index)
{
	u64 g_addr;
	int ret;

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	ret = intel_gvt_ggtt_gmadr_h2g(vgpu, h_index << I915_GTT_PAGE_SHIFT,
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				       &g_addr);
	if (ret)
		return ret;

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	*g_index = g_addr >> I915_GTT_PAGE_SHIFT;
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	return 0;
}

#define gtt_type_is_entry(type) \
	(type > GTT_TYPE_INVALID && type < GTT_TYPE_PPGTT_ENTRY \
	 && type != GTT_TYPE_PPGTT_PTE_ENTRY \
	 && type != GTT_TYPE_PPGTT_ROOT_ENTRY)

#define gtt_type_is_pt(type) \
	(type >= GTT_TYPE_PPGTT_PTE_PT && type < GTT_TYPE_MAX)

#define gtt_type_is_pte_pt(type) \
	(type == GTT_TYPE_PPGTT_PTE_PT)

#define gtt_type_is_root_pointer(type) \
	(gtt_type_is_entry(type) && type > GTT_TYPE_PPGTT_ROOT_ENTRY)

#define gtt_init_entry(e, t, p, v) do { \
	(e)->type = t; \
	(e)->pdev = p; \
	memcpy(&(e)->val64, &v, sizeof(v)); \
} while (0)

/*
 * Mappings between GTT_TYPE* enumerations.
 * Following information can be found according to the given type:
 * - type of next level page table
 * - type of entry inside this level page table
 * - type of entry with PSE set
 *
 * If the given type doesn't have such a kind of information,
 * e.g. give a l4 root entry type, then request to get its PSE type,
 * give a PTE page table type, then request to get its next level page
 * table type, as we know l4 root entry doesn't have a PSE bit,
 * and a PTE page table doesn't have a next level page table type,
 * GTT_TYPE_INVALID will be returned. This is useful when traversing a
 * page table.
 */

struct gtt_type_table_entry {
	int entry_type;
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	int pt_type;
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	int next_pt_type;
	int pse_entry_type;
};

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#define GTT_TYPE_TABLE_ENTRY(type, e_type, cpt_type, npt_type, pse_type) \
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	[type] = { \
		.entry_type = e_type, \
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		.pt_type = cpt_type, \
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		.next_pt_type = npt_type, \
		.pse_entry_type = pse_type, \
	}

static struct gtt_type_table_entry gtt_type_table[] = {
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_ROOT_L4_ENTRY,
			GTT_TYPE_PPGTT_ROOT_L4_ENTRY,
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			GTT_TYPE_INVALID,
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			GTT_TYPE_PPGTT_PML4_PT,
			GTT_TYPE_INVALID),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PML4_PT,
			GTT_TYPE_PPGTT_PML4_ENTRY,
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			GTT_TYPE_PPGTT_PML4_PT,
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			GTT_TYPE_PPGTT_PDP_PT,
			GTT_TYPE_INVALID),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PML4_ENTRY,
			GTT_TYPE_PPGTT_PML4_ENTRY,
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			GTT_TYPE_PPGTT_PML4_PT,
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			GTT_TYPE_PPGTT_PDP_PT,
			GTT_TYPE_INVALID),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDP_PT,
			GTT_TYPE_PPGTT_PDP_ENTRY,
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			GTT_TYPE_PPGTT_PDP_PT,
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			GTT_TYPE_PPGTT_PDE_PT,
			GTT_TYPE_PPGTT_PTE_1G_ENTRY),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_ROOT_L3_ENTRY,
			GTT_TYPE_PPGTT_ROOT_L3_ENTRY,
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			GTT_TYPE_INVALID,
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			GTT_TYPE_PPGTT_PDE_PT,
			GTT_TYPE_PPGTT_PTE_1G_ENTRY),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDP_ENTRY,
			GTT_TYPE_PPGTT_PDP_ENTRY,
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			GTT_TYPE_PPGTT_PDP_PT,
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			GTT_TYPE_PPGTT_PDE_PT,
			GTT_TYPE_PPGTT_PTE_1G_ENTRY),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDE_PT,
			GTT_TYPE_PPGTT_PDE_ENTRY,
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			GTT_TYPE_PPGTT_PDE_PT,
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			GTT_TYPE_PPGTT_PTE_PT,
			GTT_TYPE_PPGTT_PTE_2M_ENTRY),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDE_ENTRY,
			GTT_TYPE_PPGTT_PDE_ENTRY,
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			GTT_TYPE_PPGTT_PDE_PT,
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			GTT_TYPE_PPGTT_PTE_PT,
			GTT_TYPE_PPGTT_PTE_2M_ENTRY),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_PT,
			GTT_TYPE_PPGTT_PTE_4K_ENTRY,
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			GTT_TYPE_PPGTT_PTE_PT,
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			GTT_TYPE_INVALID,
			GTT_TYPE_INVALID),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_4K_ENTRY,
			GTT_TYPE_PPGTT_PTE_4K_ENTRY,
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			GTT_TYPE_PPGTT_PTE_PT,
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			GTT_TYPE_INVALID,
			GTT_TYPE_INVALID),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_2M_ENTRY,
			GTT_TYPE_PPGTT_PDE_ENTRY,
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			GTT_TYPE_PPGTT_PDE_PT,
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			GTT_TYPE_INVALID,
			GTT_TYPE_PPGTT_PTE_2M_ENTRY),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_1G_ENTRY,
			GTT_TYPE_PPGTT_PDP_ENTRY,
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			GTT_TYPE_PPGTT_PDP_PT,
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			GTT_TYPE_INVALID,
			GTT_TYPE_PPGTT_PTE_1G_ENTRY),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_GGTT_PTE,
			GTT_TYPE_GGTT_PTE,
			GTT_TYPE_INVALID,
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			GTT_TYPE_INVALID,
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			GTT_TYPE_INVALID),
};

static inline int get_next_pt_type(int type)
{
	return gtt_type_table[type].next_pt_type;
}

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static inline int get_pt_type(int type)
{
	return gtt_type_table[type].pt_type;
}

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static inline int get_entry_type(int type)
{
	return gtt_type_table[type].entry_type;
}

static inline int get_pse_type(int type)
{
	return gtt_type_table[type].pse_entry_type;
}

static u64 read_pte64(struct drm_i915_private *dev_priv, unsigned long index)
{
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	void __iomem *addr = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + index;
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	return readq(addr);
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}

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static void ggtt_invalidate(struct drm_i915_private *dev_priv)
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{
	mmio_hw_access_pre(dev_priv);
	I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
	mmio_hw_access_post(dev_priv);
}

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static void write_pte64(struct drm_i915_private *dev_priv,
		unsigned long index, u64 pte)
{
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	void __iomem *addr = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + index;
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	writeq(pte, addr);
}

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static inline int gtt_get_entry64(void *pt,
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		struct intel_gvt_gtt_entry *e,
		unsigned long index, bool hypervisor_access, unsigned long gpa,
		struct intel_vgpu *vgpu)
{
	const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
	int ret;

	if (WARN_ON(info->gtt_entry_size != 8))
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		return -EINVAL;
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	if (hypervisor_access) {
		ret = intel_gvt_hypervisor_read_gpa(vgpu, gpa +
				(index << info->gtt_entry_size_shift),
				&e->val64, 8);
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		if (WARN_ON(ret))
			return ret;
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	} else if (!pt) {
		e->val64 = read_pte64(vgpu->gvt->dev_priv, index);
	} else {
		e->val64 = *((u64 *)pt + index);
	}
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	return 0;
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}

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static inline int gtt_set_entry64(void *pt,
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		struct intel_gvt_gtt_entry *e,
		unsigned long index, bool hypervisor_access, unsigned long gpa,
		struct intel_vgpu *vgpu)
{
	const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
	int ret;

	if (WARN_ON(info->gtt_entry_size != 8))
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		return -EINVAL;
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	if (hypervisor_access) {
		ret = intel_gvt_hypervisor_write_gpa(vgpu, gpa +
				(index << info->gtt_entry_size_shift),
				&e->val64, 8);
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		if (WARN_ON(ret))
			return ret;
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	} else if (!pt) {
		write_pte64(vgpu->gvt->dev_priv, index, e->val64);
	} else {
		*((u64 *)pt + index) = e->val64;
	}
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	return 0;
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}

#define GTT_HAW 46

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#define ADDR_1G_MASK (((1UL << (GTT_HAW - 30)) - 1) << 30)
#define ADDR_2M_MASK (((1UL << (GTT_HAW - 21)) - 1) << 21)
#define ADDR_4K_MASK (((1UL << (GTT_HAW - 12)) - 1) << 12)
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static unsigned long gen8_gtt_get_pfn(struct intel_gvt_gtt_entry *e)
{
	unsigned long pfn;

	if (e->type == GTT_TYPE_PPGTT_PTE_1G_ENTRY)
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		pfn = (e->val64 & ADDR_1G_MASK) >> PAGE_SHIFT;
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	else if (e->type == GTT_TYPE_PPGTT_PTE_2M_ENTRY)
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		pfn = (e->val64 & ADDR_2M_MASK) >> PAGE_SHIFT;
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	else
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		pfn = (e->val64 & ADDR_4K_MASK) >> PAGE_SHIFT;
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	return pfn;
}

static void gen8_gtt_set_pfn(struct intel_gvt_gtt_entry *e, unsigned long pfn)
{
	if (e->type == GTT_TYPE_PPGTT_PTE_1G_ENTRY) {
		e->val64 &= ~ADDR_1G_MASK;
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		pfn &= (ADDR_1G_MASK >> PAGE_SHIFT);
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	} else if (e->type == GTT_TYPE_PPGTT_PTE_2M_ENTRY) {
		e->val64 &= ~ADDR_2M_MASK;
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		pfn &= (ADDR_2M_MASK >> PAGE_SHIFT);
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	} else {
		e->val64 &= ~ADDR_4K_MASK;
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		pfn &= (ADDR_4K_MASK >> PAGE_SHIFT);
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	}

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	e->val64 |= (pfn << PAGE_SHIFT);
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}

static bool gen8_gtt_test_pse(struct intel_gvt_gtt_entry *e)
{
	/* Entry doesn't have PSE bit. */
	if (get_pse_type(e->type) == GTT_TYPE_INVALID)
		return false;

	e->type = get_entry_type(e->type);
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	if (!(e->val64 & _PAGE_PSE))
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		return false;

	e->type = get_pse_type(e->type);
	return true;
}

static bool gen8_gtt_test_present(struct intel_gvt_gtt_entry *e)
{
	/*
	 * i915 writes PDP root pointer registers without present bit,
	 * it also works, so we need to treat root pointer entry
	 * specifically.
	 */
	if (e->type == GTT_TYPE_PPGTT_ROOT_L3_ENTRY
			|| e->type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY)
		return (e->val64 != 0);
	else
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		return (e->val64 & _PAGE_PRESENT);
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}

static void gtt_entry_clear_present(struct intel_gvt_gtt_entry *e)
{
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	e->val64 &= ~_PAGE_PRESENT;
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}

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static void gtt_entry_set_present(struct intel_gvt_gtt_entry *e)
{
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	e->val64 |= _PAGE_PRESENT;
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}

/*
 * Per-platform GMA routines.
 */
static unsigned long gma_to_ggtt_pte_index(unsigned long gma)
{
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	unsigned long x = (gma >> I915_GTT_PAGE_SHIFT);
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	trace_gma_index(__func__, gma, x);
	return x;
}

#define DEFINE_PPGTT_GMA_TO_INDEX(prefix, ename, exp) \
static unsigned long prefix##_gma_to_##ename##_index(unsigned long gma) \
{ \
	unsigned long x = (exp); \
	trace_gma_index(__func__, gma, x); \
	return x; \
}

DEFINE_PPGTT_GMA_TO_INDEX(gen8, pte, (gma >> 12 & 0x1ff));
DEFINE_PPGTT_GMA_TO_INDEX(gen8, pde, (gma >> 21 & 0x1ff));
DEFINE_PPGTT_GMA_TO_INDEX(gen8, l3_pdp, (gma >> 30 & 0x3));
DEFINE_PPGTT_GMA_TO_INDEX(gen8, l4_pdp, (gma >> 30 & 0x1ff));
DEFINE_PPGTT_GMA_TO_INDEX(gen8, pml4, (gma >> 39 & 0x1ff));

static struct intel_gvt_gtt_pte_ops gen8_gtt_pte_ops = {
	.get_entry = gtt_get_entry64,
	.set_entry = gtt_set_entry64,
	.clear_present = gtt_entry_clear_present,
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	.set_present = gtt_entry_set_present,
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	.test_present = gen8_gtt_test_present,
	.test_pse = gen8_gtt_test_pse,
	.get_pfn = gen8_gtt_get_pfn,
	.set_pfn = gen8_gtt_set_pfn,
};

static struct intel_gvt_gtt_gma_ops gen8_gtt_gma_ops = {
	.gma_to_ggtt_pte_index = gma_to_ggtt_pte_index,
	.gma_to_pte_index = gen8_gma_to_pte_index,
	.gma_to_pde_index = gen8_gma_to_pde_index,
	.gma_to_l3_pdp_index = gen8_gma_to_l3_pdp_index,
	.gma_to_l4_pdp_index = gen8_gma_to_l4_pdp_index,
	.gma_to_pml4_index = gen8_gma_to_pml4_index,
};

/*
 * MM helpers.
 */
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static void _ppgtt_get_root_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index,
		bool guest)
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{
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	struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
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	GEM_BUG_ON(mm->type != INTEL_GVT_MM_PPGTT);
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	entry->type = mm->ppgtt_mm.root_entry_type;
	pte_ops->get_entry(guest ? mm->ppgtt_mm.guest_pdps :
			   mm->ppgtt_mm.shadow_pdps,
			   entry, index, false, 0, mm->vgpu);
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	pte_ops->test_pse(entry);
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}

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static inline void ppgtt_get_guest_root_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index)
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{
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	_ppgtt_get_root_entry(mm, entry, index, true);
}

static inline void ppgtt_get_shadow_root_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index)
{
	_ppgtt_get_root_entry(mm, entry, index, false);
}

static void _ppgtt_set_root_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index,
		bool guest)
{
	struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;

	pte_ops->set_entry(guest ? mm->ppgtt_mm.guest_pdps :
			   mm->ppgtt_mm.shadow_pdps,
			   entry, index, false, 0, mm->vgpu);
}

static inline void ppgtt_set_guest_root_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index)
{
	_ppgtt_set_root_entry(mm, entry, index, true);
}

static inline void ppgtt_set_shadow_root_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index)
{
	_ppgtt_set_root_entry(mm, entry, index, false);
}

static void ggtt_get_guest_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index)
{
	struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;

	GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);

	entry->type = GTT_TYPE_GGTT_PTE;
	pte_ops->get_entry(mm->ggtt_mm.virtual_ggtt, entry, index,
			   false, 0, mm->vgpu);
}

static void ggtt_set_guest_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index)
{
	struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;

	GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);

	pte_ops->set_entry(mm->ggtt_mm.virtual_ggtt, entry, index,
			   false, 0, mm->vgpu);
}

static void ggtt_set_host_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index)
{
	struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;

	GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);
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	pte_ops->set_entry(NULL, entry, index, false, 0, mm->vgpu);
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}

/*
 * PPGTT shadow page table helpers.
 */
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static inline int ppgtt_spt_get_entry(
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		struct intel_vgpu_ppgtt_spt *spt,
		void *page_table, int type,
		struct intel_gvt_gtt_entry *e, unsigned long index,
		bool guest)
{
	struct intel_gvt *gvt = spt->vgpu->gvt;
	struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
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	int ret;
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	e->type = get_entry_type(type);

	if (WARN(!gtt_type_is_entry(e->type), "invalid entry type\n"))
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		return -EINVAL;
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	ret = ops->get_entry(page_table, e, index, guest,
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			spt->guest_page.track.gfn << I915_GTT_PAGE_SHIFT,
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			spt->vgpu);
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	if (ret)
		return ret;

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	ops->test_pse(e);
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	gvt_vdbg_mm("read ppgtt entry, spt type %d, entry type %d, index %lu, value %llx\n",
		    type, e->type, index, e->val64);
571
	return 0;
572 573
}

574
static inline int ppgtt_spt_set_entry(
575 576 577 578 579 580 581 582 583
		struct intel_vgpu_ppgtt_spt *spt,
		void *page_table, int type,
		struct intel_gvt_gtt_entry *e, unsigned long index,
		bool guest)
{
	struct intel_gvt *gvt = spt->vgpu->gvt;
	struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;

	if (WARN(!gtt_type_is_entry(e->type), "invalid entry type\n"))
584
		return -EINVAL;
585

586 587 588
	gvt_vdbg_mm("set ppgtt entry, spt type %d, entry type %d, index %lu, value %llx\n",
		    type, e->type, index, e->val64);

589
	return ops->set_entry(page_table, e, index, guest,
590
			spt->guest_page.track.gfn << I915_GTT_PAGE_SHIFT,
591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610
			spt->vgpu);
}

#define ppgtt_get_guest_entry(spt, e, index) \
	ppgtt_spt_get_entry(spt, NULL, \
		spt->guest_page_type, e, index, true)

#define ppgtt_set_guest_entry(spt, e, index) \
	ppgtt_spt_set_entry(spt, NULL, \
		spt->guest_page_type, e, index, true)

#define ppgtt_get_shadow_entry(spt, e, index) \
	ppgtt_spt_get_entry(spt, spt->shadow_page.vaddr, \
		spt->shadow_page.type, e, index, false)

#define ppgtt_set_shadow_entry(spt, e, index) \
	ppgtt_spt_set_entry(spt, spt->shadow_page.vaddr, \
		spt->shadow_page.type, e, index, false)

/**
611
 * intel_vgpu_init_page_track - init a page track data structure
612
 * @vgpu: a vGPU
613
 * @t: a page track data structure
614
 * @gfn: guest memory page frame number
615
 * @handler: the function will be called when target guest memory page has
616 617
 * been modified.
 *
618 619
 * This function is called when a user wants to prepare a page track data
 * structure to track a guest memory page.
620 621 622 623
 *
 * Returns:
 * Zero on success, negative error code if failed.
 */
624 625
int intel_vgpu_init_page_track(struct intel_vgpu *vgpu,
		struct intel_vgpu_page_track *t,
626 627 628 629
		unsigned long gfn,
		int (*handler)(void *, u64, void *, int),
		void *data)
{
630
	INIT_HLIST_NODE(&t->node);
631

632 633 634 635
	t->tracked = false;
	t->gfn = gfn;
	t->handler = handler;
	t->data = data;
636

637
	hash_add(vgpu->gtt.tracked_guest_page_hash_table, &t->node, t->gfn);
638 639 640 641
	return 0;
}

/**
642
 * intel_vgpu_clean_page_track - release a page track data structure
643
 * @vgpu: a vGPU
644
 * @t: a page track data structure
645
 *
646
 * This function is called before a user frees a page track data structure.
647
 */
648 649
void intel_vgpu_clean_page_track(struct intel_vgpu *vgpu,
		struct intel_vgpu_page_track *t)
650
{
651 652
	if (!hlist_unhashed(&t->node))
		hash_del(&t->node);
653

654 655
	if (t->tracked)
		intel_gvt_hypervisor_disable_page_track(vgpu, t);
656 657 658
}

/**
659
 * intel_vgpu_find_tracked_page - find a tracked guest page
660 661 662
 * @vgpu: a vGPU
 * @gfn: guest memory page frame number
 *
663 664
 * This function is called when the emulation layer wants to figure out if a
 * trapped GFN is a tracked guest page.
665 666
 *
 * Returns:
667
 * Pointer to page track data structure, NULL if not found.
668
 */
669
struct intel_vgpu_page_track *intel_vgpu_find_tracked_page(
670 671
		struct intel_vgpu *vgpu, unsigned long gfn)
{
672
	struct intel_vgpu_page_track *t;
673

674 675 676 677
	hash_for_each_possible(vgpu->gtt.tracked_guest_page_hash_table,
			t, node, gfn) {
		if (t->gfn == gfn)
			return t;
678 679 680 681
	}
	return NULL;
}

682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705
static int init_guest_page(struct intel_vgpu *vgpu,
		struct intel_vgpu_guest_page *p,
		unsigned long gfn,
		int (*handler)(void *, u64, void *, int),
		void *data)
{
	p->oos_page = NULL;
	p->write_cnt = 0;

	return intel_vgpu_init_page_track(vgpu, &p->track, gfn, handler, data);
}

static int detach_oos_page(struct intel_vgpu *vgpu,
		struct intel_vgpu_oos_page *oos_page);

static void clean_guest_page(struct intel_vgpu *vgpu,
		struct intel_vgpu_guest_page *p)
{
	if (p->oos_page)
		detach_oos_page(vgpu, p->oos_page);

	intel_vgpu_clean_page_track(vgpu, &p->track);
}

706
static inline int init_shadow_page(struct intel_vgpu *vgpu,
707
		struct intel_vgpu_shadow_page *p, int type, bool hash)
708
{
709 710 711 712 713
	struct device *kdev = &vgpu->gvt->dev_priv->drm.pdev->dev;
	dma_addr_t daddr;

	daddr = dma_map_page(kdev, p->page, 0, 4096, PCI_DMA_BIDIRECTIONAL);
	if (dma_mapping_error(kdev, daddr)) {
714
		gvt_vgpu_err("fail to map dma addr\n");
715 716 717
		return -EINVAL;
	}

718 719 720 721 722
	p->vaddr = page_address(p->page);
	p->type = type;

	INIT_HLIST_NODE(&p->node);

723
	p->mfn = daddr >> I915_GTT_PAGE_SHIFT;
724 725
	if (hash)
		hash_add(vgpu->gtt.shadow_page_hash_table, &p->node, p->mfn);
726 727 728
	return 0;
}

729 730
static inline void clean_shadow_page(struct intel_vgpu *vgpu,
		struct intel_vgpu_shadow_page *p)
731
{
732 733
	struct device *kdev = &vgpu->gvt->dev_priv->drm.pdev->dev;

734
	dma_unmap_page(kdev, p->mfn << I915_GTT_PAGE_SHIFT, 4096,
735 736
			PCI_DMA_BIDIRECTIONAL);

737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753
	if (!hlist_unhashed(&p->node))
		hash_del(&p->node);
}

static inline struct intel_vgpu_shadow_page *find_shadow_page(
		struct intel_vgpu *vgpu, unsigned long mfn)
{
	struct intel_vgpu_shadow_page *p;

	hash_for_each_possible(vgpu->gtt.shadow_page_hash_table,
		p, node, mfn) {
		if (p->mfn == mfn)
			return p;
	}
	return NULL;
}

754 755 756
#define page_track_to_guest_page(ptr) \
	container_of(ptr, struct intel_vgpu_guest_page, track)

757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788
#define guest_page_to_ppgtt_spt(ptr) \
	container_of(ptr, struct intel_vgpu_ppgtt_spt, guest_page)

#define shadow_page_to_ppgtt_spt(ptr) \
	container_of(ptr, struct intel_vgpu_ppgtt_spt, shadow_page)

static void *alloc_spt(gfp_t gfp_mask)
{
	struct intel_vgpu_ppgtt_spt *spt;

	spt = kzalloc(sizeof(*spt), gfp_mask);
	if (!spt)
		return NULL;

	spt->shadow_page.page = alloc_page(gfp_mask);
	if (!spt->shadow_page.page) {
		kfree(spt);
		return NULL;
	}
	return spt;
}

static void free_spt(struct intel_vgpu_ppgtt_spt *spt)
{
	__free_page(spt->shadow_page.page);
	kfree(spt);
}

static void ppgtt_free_shadow_page(struct intel_vgpu_ppgtt_spt *spt)
{
	trace_spt_free(spt->vgpu->id, spt, spt->shadow_page.type);

789
	clean_shadow_page(spt->vgpu, &spt->shadow_page);
790
	clean_guest_page(spt->vgpu, &spt->guest_page);
791 792 793 794 795 796 797 798 799 800 801 802 803 804 805
	list_del_init(&spt->post_shadow_list);

	free_spt(spt);
}

static void ppgtt_free_all_shadow_page(struct intel_vgpu *vgpu)
{
	struct hlist_node *n;
	struct intel_vgpu_shadow_page *sp;
	int i;

	hash_for_each_safe(vgpu->gtt.shadow_page_hash_table, i, n, sp, node)
		ppgtt_free_shadow_page(shadow_page_to_ppgtt_spt(sp));
}

806 807
static int ppgtt_handle_guest_write_page_table_bytes(
		struct intel_vgpu_guest_page *gpt,
808 809
		u64 pa, void *p_data, int bytes);

810
static int ppgtt_write_protection_handler(void *data, u64 pa,
811 812
		void *p_data, int bytes)
{
813 814
	struct intel_vgpu_page_track *t = data;
	struct intel_vgpu_guest_page *p = page_track_to_guest_page(t);
815 816 817 818 819
	int ret;

	if (bytes != 4 && bytes != 8)
		return -EINVAL;

820
	if (!t->tracked)
821 822
		return -EINVAL;

823
	ret = ppgtt_handle_guest_write_page_table_bytes(p,
824 825 826 827 828 829
		pa, p_data, bytes);
	if (ret)
		return ret;
	return ret;
}

830
static int reclaim_one_ppgtt_mm(struct intel_gvt *gvt);
831 832 833 834 835 836 837 838 839 840

static struct intel_vgpu_ppgtt_spt *ppgtt_alloc_shadow_page(
		struct intel_vgpu *vgpu, int type, unsigned long gfn)
{
	struct intel_vgpu_ppgtt_spt *spt = NULL;
	int ret;

retry:
	spt = alloc_spt(GFP_KERNEL | __GFP_ZERO);
	if (!spt) {
841
		if (reclaim_one_ppgtt_mm(vgpu->gvt))
842 843
			goto retry;

844
		gvt_vgpu_err("fail to allocate ppgtt shadow page\n");
845 846 847 848 849 850 851 852 853 854 855 856
		return ERR_PTR(-ENOMEM);
	}

	spt->vgpu = vgpu;
	spt->guest_page_type = type;
	atomic_set(&spt->refcount, 1);
	INIT_LIST_HEAD(&spt->post_shadow_list);

	/*
	 * TODO: guest page type may be different with shadow page type,
	 *	 when we support PSE page in future.
	 */
857
	ret = init_shadow_page(vgpu, &spt->shadow_page, type, true);
858
	if (ret) {
859
		gvt_vgpu_err("fail to initialize shadow page for spt\n");
860 861 862
		goto err;
	}

863
	ret = init_guest_page(vgpu, &spt->guest_page,
864 865
			gfn, ppgtt_write_protection_handler, NULL);
	if (ret) {
866
		gvt_vgpu_err("fail to initialize guest page for spt\n");
867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884
		goto err;
	}

	trace_spt_alloc(vgpu->id, spt, type, spt->shadow_page.mfn, gfn);
	return spt;
err:
	ppgtt_free_shadow_page(spt);
	return ERR_PTR(ret);
}

static struct intel_vgpu_ppgtt_spt *ppgtt_find_shadow_page(
		struct intel_vgpu *vgpu, unsigned long mfn)
{
	struct intel_vgpu_shadow_page *p = find_shadow_page(vgpu, mfn);

	if (p)
		return shadow_page_to_ppgtt_spt(p);

885
	gvt_vgpu_err("fail to find ppgtt shadow page: 0x%lx\n", mfn);
886 887 888 889 890 891 892
	return NULL;
}

#define pt_entry_size_shift(spt) \
	((spt)->vgpu->gvt->device_info.gtt_entry_size_shift)

#define pt_entries(spt) \
893
	(I915_GTT_PAGE_SIZE >> pt_entry_size_shift(spt))
894 895 896

#define for_each_present_guest_entry(spt, e, i) \
	for (i = 0; i < pt_entries(spt); i++) \
897 898
		if (!ppgtt_get_guest_entry(spt, e, i) && \
		    spt->vgpu->gvt->gtt.pte_ops->test_present(e))
899 900 901

#define for_each_present_shadow_entry(spt, e, i) \
	for (i = 0; i < pt_entries(spt); i++) \
902 903
		if (!ppgtt_get_shadow_entry(spt, e, i) && \
		    spt->vgpu->gvt->gtt.pte_ops->test_present(e))
904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920

static void ppgtt_get_shadow_page(struct intel_vgpu_ppgtt_spt *spt)
{
	int v = atomic_read(&spt->refcount);

	trace_spt_refcount(spt->vgpu->id, "inc", spt, v, (v + 1));

	atomic_inc(&spt->refcount);
}

static int ppgtt_invalidate_shadow_page(struct intel_vgpu_ppgtt_spt *spt);

static int ppgtt_invalidate_shadow_page_by_shadow_entry(struct intel_vgpu *vgpu,
		struct intel_gvt_gtt_entry *e)
{
	struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
	struct intel_vgpu_ppgtt_spt *s;
921
	intel_gvt_gtt_type_t cur_pt_type;
922

923
	GEM_BUG_ON(!gtt_type_is_pt(get_next_pt_type(e->type)));
924

925 926 927 928 929 930 931
	if (e->type != GTT_TYPE_PPGTT_ROOT_L3_ENTRY
		&& e->type != GTT_TYPE_PPGTT_ROOT_L4_ENTRY) {
		cur_pt_type = get_next_pt_type(e->type) + 1;
		if (ops->get_pfn(e) ==
			vgpu->gtt.scratch_pt[cur_pt_type].page_mfn)
			return 0;
	}
932 933
	s = ppgtt_find_shadow_page(vgpu, ops->get_pfn(e));
	if (!s) {
934 935
		gvt_vgpu_err("fail to find shadow page: mfn: 0x%lx\n",
				ops->get_pfn(e));
936 937 938 939 940 941 942
		return -ENXIO;
	}
	return ppgtt_invalidate_shadow_page(s);
}

static int ppgtt_invalidate_shadow_page(struct intel_vgpu_ppgtt_spt *spt)
{
943
	struct intel_vgpu *vgpu = spt->vgpu;
944 945 946 947 948 949
	struct intel_gvt_gtt_entry e;
	unsigned long index;
	int ret;
	int v = atomic_read(&spt->refcount);

	trace_spt_change(spt->vgpu->id, "die", spt,
950
			spt->guest_page.track.gfn, spt->shadow_page.type);
951 952 953 954 955 956 957 958 959 960

	trace_spt_refcount(spt->vgpu->id, "dec", spt, v, (v - 1));

	if (atomic_dec_return(&spt->refcount) > 0)
		return 0;

	if (gtt_type_is_pte_pt(spt->shadow_page.type))
		goto release;

	for_each_present_shadow_entry(spt, &e, index) {
961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979
		switch (e.type) {
		case GTT_TYPE_PPGTT_PTE_4K_ENTRY:
			gvt_vdbg_mm("invalidate 4K entry\n");
			continue;
		case GTT_TYPE_PPGTT_PTE_2M_ENTRY:
		case GTT_TYPE_PPGTT_PTE_1G_ENTRY:
			WARN(1, "GVT doesn't support 2M/1GB page\n");
			continue;
		case GTT_TYPE_PPGTT_PML4_ENTRY:
		case GTT_TYPE_PPGTT_PDP_ENTRY:
		case GTT_TYPE_PPGTT_PDE_ENTRY:
			gvt_vdbg_mm("invalidate PMUL4/PDP/PDE entry\n");
			ret = ppgtt_invalidate_shadow_page_by_shadow_entry(
					spt->vgpu, &e);
			if (ret)
				goto fail;
			break;
		default:
			GEM_BUG_ON(1);
980 981 982 983
		}
	}
release:
	trace_spt_change(spt->vgpu->id, "release", spt,
984
			spt->guest_page.track.gfn, spt->shadow_page.type);
985 986 987
	ppgtt_free_shadow_page(spt);
	return 0;
fail:
988 989
	gvt_vgpu_err("fail: shadow page %p shadow entry 0x%llx type %d\n",
			spt, e.val64, e.type);
990 991 992 993 994 995 996 997 998 999 1000
	return ret;
}

static int ppgtt_populate_shadow_page(struct intel_vgpu_ppgtt_spt *spt);

static struct intel_vgpu_ppgtt_spt *ppgtt_populate_shadow_page_by_guest_entry(
		struct intel_vgpu *vgpu, struct intel_gvt_gtt_entry *we)
{
	struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
	struct intel_vgpu_ppgtt_spt *s = NULL;
	struct intel_vgpu_guest_page *g;
1001
	struct intel_vgpu_page_track *t;
1002 1003
	int ret;

1004
	GEM_BUG_ON(!gtt_type_is_pt(get_next_pt_type(we->type)));
1005

1006 1007 1008
	t = intel_vgpu_find_tracked_page(vgpu, ops->get_pfn(we));
	if (t) {
		g = page_track_to_guest_page(t);
1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019
		s = guest_page_to_ppgtt_spt(g);
		ppgtt_get_shadow_page(s);
	} else {
		int type = get_next_pt_type(we->type);

		s = ppgtt_alloc_shadow_page(vgpu, type, ops->get_pfn(we));
		if (IS_ERR(s)) {
			ret = PTR_ERR(s);
			goto fail;
		}

1020 1021
		ret = intel_gvt_hypervisor_enable_page_track(vgpu,
				&s->guest_page.track);
1022 1023 1024 1025 1026 1027 1028
		if (ret)
			goto fail;

		ret = ppgtt_populate_shadow_page(s);
		if (ret)
			goto fail;

1029
		trace_spt_change(vgpu->id, "new", s, s->guest_page.track.gfn,
1030 1031 1032 1033
			s->shadow_page.type);
	}
	return s;
fail:
1034 1035
	gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n",
			s, we->val64, we->type);
1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049
	return ERR_PTR(ret);
}

static inline void ppgtt_generate_shadow_entry(struct intel_gvt_gtt_entry *se,
		struct intel_vgpu_ppgtt_spt *s, struct intel_gvt_gtt_entry *ge)
{
	struct intel_gvt_gtt_pte_ops *ops = s->vgpu->gvt->gtt.pte_ops;

	se->type = ge->type;
	se->val64 = ge->val64;

	ops->set_pfn(se, s->shadow_page.mfn);
}

1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084
static int ppgtt_populate_shadow_entry(struct intel_vgpu *vgpu,
	struct intel_vgpu_ppgtt_spt *spt, unsigned long index,
	struct intel_gvt_gtt_entry *ge)
{
	struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
	struct intel_gvt_gtt_entry se = *ge;
	unsigned long gfn, mfn;

	if (!pte_ops->test_present(ge))
		return 0;

	gfn = pte_ops->get_pfn(ge);

	switch (ge->type) {
	case GTT_TYPE_PPGTT_PTE_4K_ENTRY:
		gvt_vdbg_mm("shadow 4K gtt entry\n");
		break;
	case GTT_TYPE_PPGTT_PTE_2M_ENTRY:
	case GTT_TYPE_PPGTT_PTE_1G_ENTRY:
		gvt_vgpu_err("GVT doesn't support 2M/1GB entry\n");
		return -EINVAL;
	default:
		GEM_BUG_ON(1);
	};

	/* direct shadow */
	mfn = intel_gvt_hypervisor_gfn_to_mfn(vgpu, gfn);
	if (mfn == INTEL_GVT_INVALID_ADDR)
		return -ENXIO;

	pte_ops->set_pfn(&se, mfn);
	ppgtt_set_shadow_entry(spt, &se, index);
	return 0;
}

1085 1086 1087
static int ppgtt_populate_shadow_page(struct intel_vgpu_ppgtt_spt *spt)
{
	struct intel_vgpu *vgpu = spt->vgpu;
1088 1089
	struct intel_gvt *gvt = vgpu->gvt;
	struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
1090 1091
	struct intel_vgpu_ppgtt_spt *s;
	struct intel_gvt_gtt_entry se, ge;
1092
	unsigned long gfn, i;
1093 1094 1095
	int ret;

	trace_spt_change(spt->vgpu->id, "born", spt,
1096
			spt->guest_page.track.gfn, spt->shadow_page.type);
1097

1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109
	for_each_present_guest_entry(spt, &ge, i) {
		if (gtt_type_is_pt(get_next_pt_type(ge.type))) {
			s = ppgtt_populate_shadow_page_by_guest_entry(vgpu,
								      &ge);
			if (IS_ERR(s)) {
				ret = PTR_ERR(s);
				goto fail;
			}
			ppgtt_get_shadow_entry(spt, &se, i);
			ppgtt_generate_shadow_entry(&se, s, &ge);
			ppgtt_set_shadow_entry(spt, &se, i);
		} else {
1110
			gfn = ops->get_pfn(&ge);
1111
			if (!intel_gvt_hypervisor_is_valid_gfn(vgpu, gfn)) {
1112
				ops->set_pfn(&se, gvt->gtt.scratch_mfn);
1113 1114 1115
				ppgtt_set_shadow_entry(spt, &se, i);
				continue;
			}
1116

1117 1118 1119
			ret = ppgtt_populate_shadow_entry(vgpu, spt, i, &ge);
			if (ret)
				goto fail;
1120 1121 1122 1123
		}
	}
	return 0;
fail:
1124 1125
	gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n",
			spt, ge.val64, ge.type);
1126 1127 1128 1129
	return ret;
}

static int ppgtt_handle_guest_entry_removal(struct intel_vgpu_guest_page *gpt,
1130
		struct intel_gvt_gtt_entry *se, unsigned long index)
1131 1132 1133 1134 1135 1136 1137
{
	struct intel_vgpu_ppgtt_spt *spt = guest_page_to_ppgtt_spt(gpt);
	struct intel_vgpu_shadow_page *sp = &spt->shadow_page;
	struct intel_vgpu *vgpu = spt->vgpu;
	struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
	int ret;

1138
	trace_gpt_change(spt->vgpu->id, "remove", spt, sp->type, se->val64,
1139 1140
			 index);

1141 1142 1143
	gvt_vdbg_mm("destroy old shadow entry, type %d, index %lu, value %llx\n",
		    se->type, index, se->val64);

1144
	if (!ops->test_present(se))
1145 1146
		return 0;

1147
	if (ops->get_pfn(se) == vgpu->gtt.scratch_pt[sp->type].page_mfn)
1148 1149
		return 0;

1150
	if (gtt_type_is_pt(get_next_pt_type(se->type))) {
1151
		struct intel_vgpu_ppgtt_spt *s =
1152
			ppgtt_find_shadow_page(vgpu, ops->get_pfn(se));
1153
		if (!s) {
1154
			gvt_vgpu_err("fail to find guest page\n");
1155 1156 1157
			ret = -ENXIO;
			goto fail;
		}
1158
		ret = ppgtt_invalidate_shadow_page(s);
1159 1160 1161 1162 1163
		if (ret)
			goto fail;
	}
	return 0;
fail:
1164
	gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n",
1165
			spt, se->val64, se->type);
1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181
	return ret;
}

static int ppgtt_handle_guest_entry_add(struct intel_vgpu_guest_page *gpt,
		struct intel_gvt_gtt_entry *we, unsigned long index)
{
	struct intel_vgpu_ppgtt_spt *spt = guest_page_to_ppgtt_spt(gpt);
	struct intel_vgpu_shadow_page *sp = &spt->shadow_page;
	struct intel_vgpu *vgpu = spt->vgpu;
	struct intel_gvt_gtt_entry m;
	struct intel_vgpu_ppgtt_spt *s;
	int ret;

	trace_gpt_change(spt->vgpu->id, "add", spt, sp->type,
		we->val64, index);

1182 1183 1184
	gvt_vdbg_mm("add shadow entry: type %d, index %lu, value %llx\n",
		    we->type, index, we->val64);

1185 1186 1187 1188 1189 1190 1191 1192 1193 1194
	if (gtt_type_is_pt(get_next_pt_type(we->type))) {
		s = ppgtt_populate_shadow_page_by_guest_entry(vgpu, we);
		if (IS_ERR(s)) {
			ret = PTR_ERR(s);
			goto fail;
		}
		ppgtt_get_shadow_entry(spt, &m, index);
		ppgtt_generate_shadow_entry(&m, s, we);
		ppgtt_set_shadow_entry(spt, &m, index);
	} else {
1195
		ret = ppgtt_populate_shadow_entry(vgpu, spt, index, we);
1196 1197 1198 1199 1200
		if (ret)
			goto fail;
	}
	return 0;
fail:
1201 1202
	gvt_vgpu_err("fail: spt %p guest entry 0x%llx type %d\n",
		spt, we->val64, we->type);
1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213
	return ret;
}

static int sync_oos_page(struct intel_vgpu *vgpu,
		struct intel_vgpu_oos_page *oos_page)
{
	const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
	struct intel_gvt *gvt = vgpu->gvt;
	struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
	struct intel_vgpu_ppgtt_spt *spt =
		guest_page_to_ppgtt_spt(oos_page->guest_page);
1214
	struct intel_gvt_gtt_entry old, new;
1215 1216 1217 1218 1219 1220 1221 1222 1223
	int index;
	int ret;

	trace_oos_change(vgpu->id, "sync", oos_page->id,
			oos_page->guest_page, spt->guest_page_type);

	old.type = new.type = get_entry_type(spt->guest_page_type);
	old.val64 = new.val64 = 0;

1224 1225
	for (index = 0; index < (I915_GTT_PAGE_SIZE >>
				info->gtt_entry_size_shift); index++) {
1226 1227
		ops->get_entry(oos_page->mem, &old, index, false, 0, vgpu);
		ops->get_entry(NULL, &new