gtt.c 64.5 KB
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/*
 * GTT virtualization
 *
 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 *
 * Authors:
 *    Zhi Wang <zhi.a.wang@intel.com>
 *    Zhenyu Wang <zhenyuw@linux.intel.com>
 *    Xiao Zheng <xiao.zheng@intel.com>
 *
 * Contributors:
 *    Min He <min.he@intel.com>
 *    Bing Niu <bing.niu@intel.com>
 *
 */

#include "i915_drv.h"
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#include "gvt.h"
#include "i915_pvinfo.h"
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#include "trace.h"

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#if defined(VERBOSE_DEBUG)
#define gvt_vdbg_mm(fmt, args...) gvt_dbg_mm(fmt, ##args)
#else
#define gvt_vdbg_mm(fmt, args...)
#endif

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static bool enable_out_of_sync = false;
static int preallocated_oos_pages = 8192;

/*
 * validate a gm address and related range size,
 * translate it to host gm address
 */
bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size)
{
	if ((!vgpu_gmadr_is_valid(vgpu, addr)) || (size
			&& !vgpu_gmadr_is_valid(vgpu, addr + size - 1))) {
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		gvt_vgpu_err("invalid range gmadr 0x%llx size 0x%x\n",
				addr, size);
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		return false;
	}
	return true;
}

/* translate a guest gmadr to host gmadr */
int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr)
{
	if (WARN(!vgpu_gmadr_is_valid(vgpu, g_addr),
		 "invalid guest gmadr %llx\n", g_addr))
		return -EACCES;

	if (vgpu_gmadr_is_aperture(vgpu, g_addr))
		*h_addr = vgpu_aperture_gmadr_base(vgpu)
			  + (g_addr - vgpu_aperture_offset(vgpu));
	else
		*h_addr = vgpu_hidden_gmadr_base(vgpu)
			  + (g_addr - vgpu_hidden_offset(vgpu));
	return 0;
}

/* translate a host gmadr to guest gmadr */
int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr)
{
	if (WARN(!gvt_gmadr_is_valid(vgpu->gvt, h_addr),
		 "invalid host gmadr %llx\n", h_addr))
		return -EACCES;

	if (gvt_gmadr_is_aperture(vgpu->gvt, h_addr))
		*g_addr = vgpu_aperture_gmadr_base(vgpu)
			+ (h_addr - gvt_aperture_gmadr_base(vgpu->gvt));
	else
		*g_addr = vgpu_hidden_gmadr_base(vgpu)
			+ (h_addr - gvt_hidden_gmadr_base(vgpu->gvt));
	return 0;
}

int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu, unsigned long g_index,
			     unsigned long *h_index)
{
	u64 h_addr;
	int ret;

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	ret = intel_gvt_ggtt_gmadr_g2h(vgpu, g_index << I915_GTT_PAGE_SHIFT,
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				       &h_addr);
	if (ret)
		return ret;

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	*h_index = h_addr >> I915_GTT_PAGE_SHIFT;
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	return 0;
}

int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index,
			     unsigned long *g_index)
{
	u64 g_addr;
	int ret;

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	ret = intel_gvt_ggtt_gmadr_h2g(vgpu, h_index << I915_GTT_PAGE_SHIFT,
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				       &g_addr);
	if (ret)
		return ret;

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	*g_index = g_addr >> I915_GTT_PAGE_SHIFT;
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	return 0;
}

#define gtt_type_is_entry(type) \
	(type > GTT_TYPE_INVALID && type < GTT_TYPE_PPGTT_ENTRY \
	 && type != GTT_TYPE_PPGTT_PTE_ENTRY \
	 && type != GTT_TYPE_PPGTT_ROOT_ENTRY)

#define gtt_type_is_pt(type) \
	(type >= GTT_TYPE_PPGTT_PTE_PT && type < GTT_TYPE_MAX)

#define gtt_type_is_pte_pt(type) \
	(type == GTT_TYPE_PPGTT_PTE_PT)

#define gtt_type_is_root_pointer(type) \
	(gtt_type_is_entry(type) && type > GTT_TYPE_PPGTT_ROOT_ENTRY)

#define gtt_init_entry(e, t, p, v) do { \
	(e)->type = t; \
	(e)->pdev = p; \
	memcpy(&(e)->val64, &v, sizeof(v)); \
} while (0)

/*
 * Mappings between GTT_TYPE* enumerations.
 * Following information can be found according to the given type:
 * - type of next level page table
 * - type of entry inside this level page table
 * - type of entry with PSE set
 *
 * If the given type doesn't have such a kind of information,
 * e.g. give a l4 root entry type, then request to get its PSE type,
 * give a PTE page table type, then request to get its next level page
 * table type, as we know l4 root entry doesn't have a PSE bit,
 * and a PTE page table doesn't have a next level page table type,
 * GTT_TYPE_INVALID will be returned. This is useful when traversing a
 * page table.
 */

struct gtt_type_table_entry {
	int entry_type;
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	int pt_type;
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	int next_pt_type;
	int pse_entry_type;
};

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#define GTT_TYPE_TABLE_ENTRY(type, e_type, cpt_type, npt_type, pse_type) \
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	[type] = { \
		.entry_type = e_type, \
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		.pt_type = cpt_type, \
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		.next_pt_type = npt_type, \
		.pse_entry_type = pse_type, \
	}

static struct gtt_type_table_entry gtt_type_table[] = {
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_ROOT_L4_ENTRY,
			GTT_TYPE_PPGTT_ROOT_L4_ENTRY,
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			GTT_TYPE_INVALID,
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			GTT_TYPE_PPGTT_PML4_PT,
			GTT_TYPE_INVALID),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PML4_PT,
			GTT_TYPE_PPGTT_PML4_ENTRY,
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			GTT_TYPE_PPGTT_PML4_PT,
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			GTT_TYPE_PPGTT_PDP_PT,
			GTT_TYPE_INVALID),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PML4_ENTRY,
			GTT_TYPE_PPGTT_PML4_ENTRY,
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			GTT_TYPE_PPGTT_PML4_PT,
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			GTT_TYPE_PPGTT_PDP_PT,
			GTT_TYPE_INVALID),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDP_PT,
			GTT_TYPE_PPGTT_PDP_ENTRY,
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			GTT_TYPE_PPGTT_PDP_PT,
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			GTT_TYPE_PPGTT_PDE_PT,
			GTT_TYPE_PPGTT_PTE_1G_ENTRY),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_ROOT_L3_ENTRY,
			GTT_TYPE_PPGTT_ROOT_L3_ENTRY,
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			GTT_TYPE_INVALID,
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			GTT_TYPE_PPGTT_PDE_PT,
			GTT_TYPE_PPGTT_PTE_1G_ENTRY),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDP_ENTRY,
			GTT_TYPE_PPGTT_PDP_ENTRY,
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			GTT_TYPE_PPGTT_PDP_PT,
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			GTT_TYPE_PPGTT_PDE_PT,
			GTT_TYPE_PPGTT_PTE_1G_ENTRY),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDE_PT,
			GTT_TYPE_PPGTT_PDE_ENTRY,
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			GTT_TYPE_PPGTT_PDE_PT,
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			GTT_TYPE_PPGTT_PTE_PT,
			GTT_TYPE_PPGTT_PTE_2M_ENTRY),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDE_ENTRY,
			GTT_TYPE_PPGTT_PDE_ENTRY,
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			GTT_TYPE_PPGTT_PDE_PT,
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			GTT_TYPE_PPGTT_PTE_PT,
			GTT_TYPE_PPGTT_PTE_2M_ENTRY),
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	/* We take IPS bit as 'PSE' for PTE level. */
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	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_PT,
			GTT_TYPE_PPGTT_PTE_4K_ENTRY,
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			GTT_TYPE_PPGTT_PTE_PT,
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			GTT_TYPE_INVALID,
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			GTT_TYPE_PPGTT_PTE_64K_ENTRY),
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	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_4K_ENTRY,
			GTT_TYPE_PPGTT_PTE_4K_ENTRY,
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			GTT_TYPE_PPGTT_PTE_PT,
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			GTT_TYPE_INVALID,
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			GTT_TYPE_PPGTT_PTE_64K_ENTRY),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_64K_ENTRY,
			GTT_TYPE_PPGTT_PTE_4K_ENTRY,
			GTT_TYPE_PPGTT_PTE_PT,
			GTT_TYPE_INVALID,
			GTT_TYPE_PPGTT_PTE_64K_ENTRY),
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	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_2M_ENTRY,
			GTT_TYPE_PPGTT_PDE_ENTRY,
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			GTT_TYPE_PPGTT_PDE_PT,
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			GTT_TYPE_INVALID,
			GTT_TYPE_PPGTT_PTE_2M_ENTRY),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_1G_ENTRY,
			GTT_TYPE_PPGTT_PDP_ENTRY,
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			GTT_TYPE_PPGTT_PDP_PT,
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			GTT_TYPE_INVALID,
			GTT_TYPE_PPGTT_PTE_1G_ENTRY),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_GGTT_PTE,
			GTT_TYPE_GGTT_PTE,
			GTT_TYPE_INVALID,
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			GTT_TYPE_INVALID,
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			GTT_TYPE_INVALID),
};

static inline int get_next_pt_type(int type)
{
	return gtt_type_table[type].next_pt_type;
}

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static inline int get_pt_type(int type)
{
	return gtt_type_table[type].pt_type;
}

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static inline int get_entry_type(int type)
{
	return gtt_type_table[type].entry_type;
}

static inline int get_pse_type(int type)
{
	return gtt_type_table[type].pse_entry_type;
}

static u64 read_pte64(struct drm_i915_private *dev_priv, unsigned long index)
{
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	void __iomem *addr = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + index;
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	return readq(addr);
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}

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static void ggtt_invalidate(struct drm_i915_private *dev_priv)
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{
	mmio_hw_access_pre(dev_priv);
	I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
	mmio_hw_access_post(dev_priv);
}

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static void write_pte64(struct drm_i915_private *dev_priv,
		unsigned long index, u64 pte)
{
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	void __iomem *addr = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + index;
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	writeq(pte, addr);
}

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static inline int gtt_get_entry64(void *pt,
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		struct intel_gvt_gtt_entry *e,
		unsigned long index, bool hypervisor_access, unsigned long gpa,
		struct intel_vgpu *vgpu)
{
	const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
	int ret;

	if (WARN_ON(info->gtt_entry_size != 8))
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		return -EINVAL;
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	if (hypervisor_access) {
		ret = intel_gvt_hypervisor_read_gpa(vgpu, gpa +
				(index << info->gtt_entry_size_shift),
				&e->val64, 8);
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		if (WARN_ON(ret))
			return ret;
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	} else if (!pt) {
		e->val64 = read_pte64(vgpu->gvt->dev_priv, index);
	} else {
		e->val64 = *((u64 *)pt + index);
	}
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	return 0;
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}

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static inline int gtt_set_entry64(void *pt,
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		struct intel_gvt_gtt_entry *e,
		unsigned long index, bool hypervisor_access, unsigned long gpa,
		struct intel_vgpu *vgpu)
{
	const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
	int ret;

	if (WARN_ON(info->gtt_entry_size != 8))
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		return -EINVAL;
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	if (hypervisor_access) {
		ret = intel_gvt_hypervisor_write_gpa(vgpu, gpa +
				(index << info->gtt_entry_size_shift),
				&e->val64, 8);
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		if (WARN_ON(ret))
			return ret;
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	} else if (!pt) {
		write_pte64(vgpu->gvt->dev_priv, index, e->val64);
	} else {
		*((u64 *)pt + index) = e->val64;
	}
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	return 0;
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}

#define GTT_HAW 46

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#define ADDR_1G_MASK	GENMASK_ULL(GTT_HAW - 1, 30)
#define ADDR_2M_MASK	GENMASK_ULL(GTT_HAW - 1, 21)
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#define ADDR_64K_MASK	GENMASK_ULL(GTT_HAW - 1, 16)
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#define ADDR_4K_MASK	GENMASK_ULL(GTT_HAW - 1, 12)
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#define GTT_SPTE_FLAG_MASK GENMASK_ULL(62, 52)
#define GTT_SPTE_FLAG_64K_SPLITED BIT(52) /* splited 64K gtt entry */

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static unsigned long gen8_gtt_get_pfn(struct intel_gvt_gtt_entry *e)
{
	unsigned long pfn;

	if (e->type == GTT_TYPE_PPGTT_PTE_1G_ENTRY)
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		pfn = (e->val64 & ADDR_1G_MASK) >> PAGE_SHIFT;
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	else if (e->type == GTT_TYPE_PPGTT_PTE_2M_ENTRY)
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		pfn = (e->val64 & ADDR_2M_MASK) >> PAGE_SHIFT;
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	else if (e->type == GTT_TYPE_PPGTT_PTE_64K_ENTRY)
		pfn = (e->val64 & ADDR_64K_MASK) >> PAGE_SHIFT;
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	else
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		pfn = (e->val64 & ADDR_4K_MASK) >> PAGE_SHIFT;
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	return pfn;
}

static void gen8_gtt_set_pfn(struct intel_gvt_gtt_entry *e, unsigned long pfn)
{
	if (e->type == GTT_TYPE_PPGTT_PTE_1G_ENTRY) {
		e->val64 &= ~ADDR_1G_MASK;
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		pfn &= (ADDR_1G_MASK >> PAGE_SHIFT);
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	} else if (e->type == GTT_TYPE_PPGTT_PTE_2M_ENTRY) {
		e->val64 &= ~ADDR_2M_MASK;
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		pfn &= (ADDR_2M_MASK >> PAGE_SHIFT);
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	} else if (e->type == GTT_TYPE_PPGTT_PTE_64K_ENTRY) {
		e->val64 &= ~ADDR_64K_MASK;
		pfn &= (ADDR_64K_MASK >> PAGE_SHIFT);
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	} else {
		e->val64 &= ~ADDR_4K_MASK;
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		pfn &= (ADDR_4K_MASK >> PAGE_SHIFT);
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	}

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	e->val64 |= (pfn << PAGE_SHIFT);
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}

static bool gen8_gtt_test_pse(struct intel_gvt_gtt_entry *e)
{
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	return !!(e->val64 & _PAGE_PSE);
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}

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static bool gen8_gtt_test_ips(struct intel_gvt_gtt_entry *e)
{
	if (GEM_WARN_ON(e->type != GTT_TYPE_PPGTT_PDE_ENTRY))
		return false;

	return !!(e->val64 & GEN8_PDE_IPS_64K);
}

static void gen8_gtt_clear_ips(struct intel_gvt_gtt_entry *e)
{
	if (GEM_WARN_ON(e->type != GTT_TYPE_PPGTT_PDE_ENTRY))
		return;

	e->val64 &= ~GEN8_PDE_IPS_64K;
}

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static bool gen8_gtt_test_present(struct intel_gvt_gtt_entry *e)
{
	/*
	 * i915 writes PDP root pointer registers without present bit,
	 * it also works, so we need to treat root pointer entry
	 * specifically.
	 */
	if (e->type == GTT_TYPE_PPGTT_ROOT_L3_ENTRY
			|| e->type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY)
		return (e->val64 != 0);
	else
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		return (e->val64 & _PAGE_PRESENT);
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}

static void gtt_entry_clear_present(struct intel_gvt_gtt_entry *e)
{
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	e->val64 &= ~_PAGE_PRESENT;
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}

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static void gtt_entry_set_present(struct intel_gvt_gtt_entry *e)
{
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	e->val64 |= _PAGE_PRESENT;
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}

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static bool gen8_gtt_test_64k_splited(struct intel_gvt_gtt_entry *e)
{
	return !!(e->val64 & GTT_SPTE_FLAG_64K_SPLITED);
}

static void gen8_gtt_set_64k_splited(struct intel_gvt_gtt_entry *e)
{
	e->val64 |= GTT_SPTE_FLAG_64K_SPLITED;
}

static void gen8_gtt_clear_64k_splited(struct intel_gvt_gtt_entry *e)
{
	e->val64 &= ~GTT_SPTE_FLAG_64K_SPLITED;
}

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/*
 * Per-platform GMA routines.
 */
static unsigned long gma_to_ggtt_pte_index(unsigned long gma)
{
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	unsigned long x = (gma >> I915_GTT_PAGE_SHIFT);
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	trace_gma_index(__func__, gma, x);
	return x;
}

#define DEFINE_PPGTT_GMA_TO_INDEX(prefix, ename, exp) \
static unsigned long prefix##_gma_to_##ename##_index(unsigned long gma) \
{ \
	unsigned long x = (exp); \
	trace_gma_index(__func__, gma, x); \
	return x; \
}

DEFINE_PPGTT_GMA_TO_INDEX(gen8, pte, (gma >> 12 & 0x1ff));
DEFINE_PPGTT_GMA_TO_INDEX(gen8, pde, (gma >> 21 & 0x1ff));
DEFINE_PPGTT_GMA_TO_INDEX(gen8, l3_pdp, (gma >> 30 & 0x3));
DEFINE_PPGTT_GMA_TO_INDEX(gen8, l4_pdp, (gma >> 30 & 0x1ff));
DEFINE_PPGTT_GMA_TO_INDEX(gen8, pml4, (gma >> 39 & 0x1ff));

static struct intel_gvt_gtt_pte_ops gen8_gtt_pte_ops = {
	.get_entry = gtt_get_entry64,
	.set_entry = gtt_set_entry64,
	.clear_present = gtt_entry_clear_present,
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	.set_present = gtt_entry_set_present,
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	.test_present = gen8_gtt_test_present,
	.test_pse = gen8_gtt_test_pse,
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	.clear_ips = gen8_gtt_clear_ips,
	.test_ips = gen8_gtt_test_ips,
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	.clear_64k_splited = gen8_gtt_clear_64k_splited,
	.set_64k_splited = gen8_gtt_set_64k_splited,
	.test_64k_splited = gen8_gtt_test_64k_splited,
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	.get_pfn = gen8_gtt_get_pfn,
	.set_pfn = gen8_gtt_set_pfn,
};

static struct intel_gvt_gtt_gma_ops gen8_gtt_gma_ops = {
	.gma_to_ggtt_pte_index = gma_to_ggtt_pte_index,
	.gma_to_pte_index = gen8_gma_to_pte_index,
	.gma_to_pde_index = gen8_gma_to_pde_index,
	.gma_to_l3_pdp_index = gen8_gma_to_l3_pdp_index,
	.gma_to_l4_pdp_index = gen8_gma_to_l4_pdp_index,
	.gma_to_pml4_index = gen8_gma_to_pml4_index,
};

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/* Update entry type per pse and ips bit. */
static void update_entry_type_for_real(struct intel_gvt_gtt_pte_ops *pte_ops,
	struct intel_gvt_gtt_entry *entry, bool ips)
{
	switch (entry->type) {
	case GTT_TYPE_PPGTT_PDE_ENTRY:
	case GTT_TYPE_PPGTT_PDP_ENTRY:
		if (pte_ops->test_pse(entry))
			entry->type = get_pse_type(entry->type);
		break;
	case GTT_TYPE_PPGTT_PTE_4K_ENTRY:
		if (ips)
			entry->type = get_pse_type(entry->type);
		break;
	default:
		GEM_BUG_ON(!gtt_type_is_entry(entry->type));
	}

	GEM_BUG_ON(entry->type == GTT_TYPE_INVALID);
}

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/*
 * MM helpers.
 */
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static void _ppgtt_get_root_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index,
		bool guest)
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{
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	struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
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	GEM_BUG_ON(mm->type != INTEL_GVT_MM_PPGTT);
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	entry->type = mm->ppgtt_mm.root_entry_type;
	pte_ops->get_entry(guest ? mm->ppgtt_mm.guest_pdps :
			   mm->ppgtt_mm.shadow_pdps,
			   entry, index, false, 0, mm->vgpu);
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	update_entry_type_for_real(pte_ops, entry, false);
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}

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static inline void ppgtt_get_guest_root_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index)
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{
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	_ppgtt_get_root_entry(mm, entry, index, true);
}

static inline void ppgtt_get_shadow_root_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index)
{
	_ppgtt_get_root_entry(mm, entry, index, false);
}

static void _ppgtt_set_root_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index,
		bool guest)
{
	struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;

	pte_ops->set_entry(guest ? mm->ppgtt_mm.guest_pdps :
			   mm->ppgtt_mm.shadow_pdps,
			   entry, index, false, 0, mm->vgpu);
}

static inline void ppgtt_set_guest_root_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index)
{
	_ppgtt_set_root_entry(mm, entry, index, true);
}

static inline void ppgtt_set_shadow_root_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index)
{
	_ppgtt_set_root_entry(mm, entry, index, false);
}

static void ggtt_get_guest_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index)
{
	struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;

	GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);

	entry->type = GTT_TYPE_GGTT_PTE;
	pte_ops->get_entry(mm->ggtt_mm.virtual_ggtt, entry, index,
			   false, 0, mm->vgpu);
}

static void ggtt_set_guest_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index)
{
	struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;

	GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);

	pte_ops->set_entry(mm->ggtt_mm.virtual_ggtt, entry, index,
			   false, 0, mm->vgpu);
}

595 596 597 598 599 600 601 602 603 604
static void ggtt_get_host_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index)
{
	struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;

	GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);

	pte_ops->get_entry(NULL, entry, index, false, 0, mm->vgpu);
}

605 606 607 608 609 610
static void ggtt_set_host_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index)
{
	struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;

	GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);
611

612
	pte_ops->set_entry(NULL, entry, index, false, 0, mm->vgpu);
613 614 615 616 617
}

/*
 * PPGTT shadow page table helpers.
 */
618
static inline int ppgtt_spt_get_entry(
619 620 621 622 623 624 625
		struct intel_vgpu_ppgtt_spt *spt,
		void *page_table, int type,
		struct intel_gvt_gtt_entry *e, unsigned long index,
		bool guest)
{
	struct intel_gvt *gvt = spt->vgpu->gvt;
	struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
626
	int ret;
627 628 629 630

	e->type = get_entry_type(type);

	if (WARN(!gtt_type_is_entry(e->type), "invalid entry type\n"))
631
		return -EINVAL;
632

633
	ret = ops->get_entry(page_table, e, index, guest,
634
			spt->guest_page.gfn << I915_GTT_PAGE_SHIFT,
635
			spt->vgpu);
636 637 638
	if (ret)
		return ret;

639 640
	update_entry_type_for_real(ops, e, guest ?
				   spt->guest_page.pde_ips : false);
641 642 643

	gvt_vdbg_mm("read ppgtt entry, spt type %d, entry type %d, index %lu, value %llx\n",
		    type, e->type, index, e->val64);
644
	return 0;
645 646
}

647
static inline int ppgtt_spt_set_entry(
648 649 650 651 652 653 654 655 656
		struct intel_vgpu_ppgtt_spt *spt,
		void *page_table, int type,
		struct intel_gvt_gtt_entry *e, unsigned long index,
		bool guest)
{
	struct intel_gvt *gvt = spt->vgpu->gvt;
	struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;

	if (WARN(!gtt_type_is_entry(e->type), "invalid entry type\n"))
657
		return -EINVAL;
658

659 660 661
	gvt_vdbg_mm("set ppgtt entry, spt type %d, entry type %d, index %lu, value %llx\n",
		    type, e->type, index, e->val64);

662
	return ops->set_entry(page_table, e, index, guest,
663
			spt->guest_page.gfn << I915_GTT_PAGE_SHIFT,
664 665 666 667 668
			spt->vgpu);
}

#define ppgtt_get_guest_entry(spt, e, index) \
	ppgtt_spt_get_entry(spt, NULL, \
669
		spt->guest_page.type, e, index, true)
670 671 672

#define ppgtt_set_guest_entry(spt, e, index) \
	ppgtt_spt_set_entry(spt, NULL, \
673
		spt->guest_page.type, e, index, true)
674 675 676 677 678 679 680 681 682

#define ppgtt_get_shadow_entry(spt, e, index) \
	ppgtt_spt_get_entry(spt, spt->shadow_page.vaddr, \
		spt->shadow_page.type, e, index, false)

#define ppgtt_set_shadow_entry(spt, e, index) \
	ppgtt_spt_set_entry(spt, spt->shadow_page.vaddr, \
		spt->shadow_page.type, e, index, false)

683
static void *alloc_spt(gfp_t gfp_mask)
684
{
685
	struct intel_vgpu_ppgtt_spt *spt;
686

687 688 689
	spt = kzalloc(sizeof(*spt), gfp_mask);
	if (!spt)
		return NULL;
690

691 692 693 694 695 696
	spt->shadow_page.page = alloc_page(gfp_mask);
	if (!spt->shadow_page.page) {
		kfree(spt);
		return NULL;
	}
	return spt;
697 698
}

699
static void free_spt(struct intel_vgpu_ppgtt_spt *spt)
700
{
701 702
	__free_page(spt->shadow_page.page);
	kfree(spt);
703 704
}

705 706 707
static int detach_oos_page(struct intel_vgpu *vgpu,
		struct intel_vgpu_oos_page *oos_page);

708
static void ppgtt_free_spt(struct intel_vgpu_ppgtt_spt *spt)
709
{
710
	struct device *kdev = &spt->vgpu->gvt->dev_priv->drm.pdev->dev;
711

712
	trace_spt_free(spt->vgpu->id, spt, spt->guest_page.type);
713

714 715
	dma_unmap_page(kdev, spt->shadow_page.mfn << I915_GTT_PAGE_SHIFT, 4096,
		       PCI_DMA_BIDIRECTIONAL);
716 717

	radix_tree_delete(&spt->vgpu->gtt.spt_tree, spt->shadow_page.mfn);
718

719 720
	if (spt->guest_page.oos_page)
		detach_oos_page(spt->vgpu, spt->guest_page.oos_page);
721

722
	intel_vgpu_unregister_page_track(spt->vgpu, spt->guest_page.gfn);
723 724 725 726 727

	list_del_init(&spt->post_shadow_list);
	free_spt(spt);
}

728
static void ppgtt_free_all_spt(struct intel_vgpu *vgpu)
729
{
730
	struct intel_vgpu_ppgtt_spt *spt;
731 732
	struct radix_tree_iter iter;
	void **slot;
733

734 735
	radix_tree_for_each_slot(slot, &vgpu->gtt.spt_tree, &iter, 0) {
		spt = radix_tree_deref_slot(slot);
736
		ppgtt_free_spt(spt);
737
	}
738 739
}

740
static int ppgtt_handle_guest_write_page_table_bytes(
741
		struct intel_vgpu_ppgtt_spt *spt,
742 743
		u64 pa, void *p_data, int bytes);

744 745 746
static int ppgtt_write_protection_handler(
		struct intel_vgpu_page_track *page_track,
		u64 gpa, void *data, int bytes)
747
{
748 749
	struct intel_vgpu_ppgtt_spt *spt = page_track->priv_data;

750 751 752 753 754
	int ret;

	if (bytes != 4 && bytes != 8)
		return -EINVAL;

755
	ret = ppgtt_handle_guest_write_page_table_bytes(spt, gpa, data, bytes);
756 757 758 759 760
	if (ret)
		return ret;
	return ret;
}

761 762 763 764 765 766
/* Find a spt by guest gfn. */
static struct intel_vgpu_ppgtt_spt *intel_vgpu_find_spt_by_gfn(
		struct intel_vgpu *vgpu, unsigned long gfn)
{
	struct intel_vgpu_page_track *track;

767 768 769
	track = intel_vgpu_find_page_track(vgpu, gfn);
	if (track && track->handler == ppgtt_write_protection_handler)
		return track->priv_data;
770 771 772 773 774

	return NULL;
}

/* Find the spt by shadow page mfn. */
775
static inline struct intel_vgpu_ppgtt_spt *intel_vgpu_find_spt_by_mfn(
776 777
		struct intel_vgpu *vgpu, unsigned long mfn)
{
778
	return radix_tree_lookup(&vgpu->gtt.spt_tree, mfn);
779 780
}

781
static int reclaim_one_ppgtt_mm(struct intel_gvt *gvt);
782

783
static struct intel_vgpu_ppgtt_spt *ppgtt_alloc_spt(
784 785
		struct intel_vgpu *vgpu, int type, unsigned long gfn,
		bool guest_pde_ips)
786
{
787
	struct device *kdev = &vgpu->gvt->dev_priv->drm.pdev->dev;
788
	struct intel_vgpu_ppgtt_spt *spt = NULL;
789
	dma_addr_t daddr;
790
	int ret;
791 792 793 794

retry:
	spt = alloc_spt(GFP_KERNEL | __GFP_ZERO);
	if (!spt) {
795
		if (reclaim_one_ppgtt_mm(vgpu->gvt))
796 797
			goto retry;

798
		gvt_vgpu_err("fail to allocate ppgtt shadow page\n");
799 800 801 802 803 804 805 806
		return ERR_PTR(-ENOMEM);
	}

	spt->vgpu = vgpu;
	atomic_set(&spt->refcount, 1);
	INIT_LIST_HEAD(&spt->post_shadow_list);

	/*
807
	 * Init shadow_page.
808
	 */
809 810 811 812 813
	spt->shadow_page.type = type;
	daddr = dma_map_page(kdev, spt->shadow_page.page,
			     0, 4096, PCI_DMA_BIDIRECTIONAL);
	if (dma_mapping_error(kdev, daddr)) {
		gvt_vgpu_err("fail to map dma addr\n");
814 815
		ret = -EINVAL;
		goto err_free_spt;
816
	}
817 818
	spt->shadow_page.vaddr = page_address(spt->shadow_page.page);
	spt->shadow_page.mfn = daddr >> I915_GTT_PAGE_SHIFT;
819

820 821 822 823 824
	/*
	 * Init guest_page.
	 */
	spt->guest_page.type = type;
	spt->guest_page.gfn = gfn;
825
	spt->guest_page.pde_ips = guest_pde_ips;
826

827 828
	ret = intel_vgpu_register_page_track(vgpu, spt->guest_page.gfn,
					ppgtt_write_protection_handler, spt);
829 830
	if (ret)
		goto err_unmap_dma;
831

832 833 834
	ret = radix_tree_insert(&vgpu->gtt.spt_tree, spt->shadow_page.mfn, spt);
	if (ret)
		goto err_unreg_page_track;
835

836 837
	trace_spt_alloc(vgpu->id, spt, type, spt->shadow_page.mfn, gfn);
	return spt;
838 839 840 841 842 843 844 845

err_unreg_page_track:
	intel_vgpu_unregister_page_track(vgpu, spt->guest_page.gfn);
err_unmap_dma:
	dma_unmap_page(kdev, daddr, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
err_free_spt:
	free_spt(spt);
	return ERR_PTR(ret);
846 847 848 849 850 851
}

#define pt_entry_size_shift(spt) \
	((spt)->vgpu->gvt->device_info.gtt_entry_size_shift)

#define pt_entries(spt) \
852
	(I915_GTT_PAGE_SIZE >> pt_entry_size_shift(spt))
853 854 855

#define for_each_present_guest_entry(spt, e, i) \
	for (i = 0; i < pt_entries(spt); i++) \
856 857
		if (!ppgtt_get_guest_entry(spt, e, i) && \
		    spt->vgpu->gvt->gtt.pte_ops->test_present(e))
858 859 860

#define for_each_present_shadow_entry(spt, e, i) \
	for (i = 0; i < pt_entries(spt); i++) \
861 862
		if (!ppgtt_get_shadow_entry(spt, e, i) && \
		    spt->vgpu->gvt->gtt.pte_ops->test_present(e))
863

864
static void ppgtt_get_spt(struct intel_vgpu_ppgtt_spt *spt)
865 866 867 868 869 870 871 872
{
	int v = atomic_read(&spt->refcount);

	trace_spt_refcount(spt->vgpu->id, "inc", spt, v, (v + 1));

	atomic_inc(&spt->refcount);
}

873
static int ppgtt_invalidate_spt(struct intel_vgpu_ppgtt_spt *spt);
874

875
static int ppgtt_invalidate_spt_by_shadow_entry(struct intel_vgpu *vgpu,
876 877 878 879
		struct intel_gvt_gtt_entry *e)
{
	struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
	struct intel_vgpu_ppgtt_spt *s;
880
	intel_gvt_gtt_type_t cur_pt_type;
881

882
	GEM_BUG_ON(!gtt_type_is_pt(get_next_pt_type(e->type)));
883

884 885 886 887 888 889 890
	if (e->type != GTT_TYPE_PPGTT_ROOT_L3_ENTRY
		&& e->type != GTT_TYPE_PPGTT_ROOT_L4_ENTRY) {
		cur_pt_type = get_next_pt_type(e->type) + 1;
		if (ops->get_pfn(e) ==
			vgpu->gtt.scratch_pt[cur_pt_type].page_mfn)
			return 0;
	}
891
	s = intel_vgpu_find_spt_by_mfn(vgpu, ops->get_pfn(e));
892
	if (!s) {
893 894
		gvt_vgpu_err("fail to find shadow page: mfn: 0x%lx\n",
				ops->get_pfn(e));
895 896
		return -ENXIO;
	}
897
	return ppgtt_invalidate_spt(s);
898 899
}

900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916
static inline void ppgtt_invalidate_pte(struct intel_vgpu_ppgtt_spt *spt,
		struct intel_gvt_gtt_entry *entry)
{
	struct intel_vgpu *vgpu = spt->vgpu;
	struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
	unsigned long pfn;
	int type;

	pfn = ops->get_pfn(entry);
	type = spt->shadow_page.type;

	if (pfn == vgpu->gtt.scratch_pt[type].page_mfn)
		return;

	intel_gvt_hypervisor_dma_unmap_guest_page(vgpu, pfn << PAGE_SHIFT);
}

917
static int ppgtt_invalidate_spt(struct intel_vgpu_ppgtt_spt *spt)
918
{
919
	struct intel_vgpu *vgpu = spt->vgpu;
920 921 922 923 924 925
	struct intel_gvt_gtt_entry e;
	unsigned long index;
	int ret;
	int v = atomic_read(&spt->refcount);

	trace_spt_change(spt->vgpu->id, "die", spt,
926
			spt->guest_page.gfn, spt->shadow_page.type);
927 928 929 930 931 932 933

	trace_spt_refcount(spt->vgpu->id, "dec", spt, v, (v - 1));

	if (atomic_dec_return(&spt->refcount) > 0)
		return 0;

	for_each_present_shadow_entry(spt, &e, index) {
934 935 936
		switch (e.type) {
		case GTT_TYPE_PPGTT_PTE_4K_ENTRY:
			gvt_vdbg_mm("invalidate 4K entry\n");
937 938
			ppgtt_invalidate_pte(spt, &e);
			break;
939
		case GTT_TYPE_PPGTT_PTE_64K_ENTRY:
940 941
		case GTT_TYPE_PPGTT_PTE_2M_ENTRY:
		case GTT_TYPE_PPGTT_PTE_1G_ENTRY:
942
			WARN(1, "GVT doesn't support 64K/2M/1GB page\n");
943 944 945 946 947
			continue;
		case GTT_TYPE_PPGTT_PML4_ENTRY:
		case GTT_TYPE_PPGTT_PDP_ENTRY:
		case GTT_TYPE_PPGTT_PDE_ENTRY:
			gvt_vdbg_mm("invalidate PMUL4/PDP/PDE entry\n");
948
			ret = ppgtt_invalidate_spt_by_shadow_entry(
949 950 951 952 953 954
					spt->vgpu, &e);
			if (ret)
				goto fail;
			break;
		default:
			GEM_BUG_ON(1);
955 956
		}
	}
957

958
	trace_spt_change(spt->vgpu->id, "release", spt,
959
			 spt->guest_page.gfn, spt->shadow_page.type);
960
	ppgtt_free_spt(spt);
961 962
	return 0;
fail:
963 964
	gvt_vgpu_err("fail: shadow page %p shadow entry 0x%llx type %d\n",
			spt, e.val64, e.type);
965 966 967
	return ret;
}

968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983
static bool vgpu_ips_enabled(struct intel_vgpu *vgpu)
{
	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;

	if (INTEL_GEN(dev_priv) == 9 || INTEL_GEN(dev_priv) == 10) {
		u32 ips = vgpu_vreg_t(vgpu, GEN8_GAMW_ECO_DEV_RW_IA) &
			GAMW_ECO_ENABLE_64K_IPS_FIELD;

		return ips == GAMW_ECO_ENABLE_64K_IPS_FIELD;
	} else if (INTEL_GEN(dev_priv) >= 11) {
		/* 64K paging only controlled by IPS bit in PTE now. */
		return true;
	} else
		return false;
}

984
static int ppgtt_populate_spt(struct intel_vgpu_ppgtt_spt *spt);
985

986
static struct intel_vgpu_ppgtt_spt *ppgtt_populate_spt_by_guest_entry(
987 988 989
		struct intel_vgpu *vgpu, struct intel_gvt_gtt_entry *we)
{
	struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
990
	struct intel_vgpu_ppgtt_spt *spt = NULL;
991
	bool ips = false;
992 993
	int ret;

994
	GEM_BUG_ON(!gtt_type_is_pt(get_next_pt_type(we->type)));
995

996 997
	spt = intel_vgpu_find_spt_by_gfn(vgpu, ops->get_pfn(we));
	if (spt)
998
		ppgtt_get_spt(spt);
999
	else {
1000 1001
		int type = get_next_pt_type(we->type);

1002 1003 1004 1005
		if (we->type == GTT_TYPE_PPGTT_PDE_ENTRY)
			ips = vgpu_ips_enabled(vgpu) && ops->test_ips(we);

		spt = ppgtt_alloc_spt(vgpu, type, ops->get_pfn(we), ips);
1006 1007
		if (IS_ERR(spt)) {
			ret = PTR_ERR(spt);
1008 1009 1010
			goto fail;
		}

1011
		ret = intel_vgpu_enable_page_track(vgpu, spt->guest_page.gfn);
1012 1013 1014
		if (ret)
			goto fail;

1015
		ret = ppgtt_populate_spt(spt);
1016 1017 1018
		if (ret)
			goto fail;

1019 1020
		trace_spt_change(vgpu->id, "new", spt, spt->guest_page.gfn,
				 spt->shadow_page.type);
1021
	}
1022
	return spt;
1023
fail:
1024
	gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n",
1025
		     spt, we->val64, we->type);
1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039
	return ERR_PTR(ret);
}

static inline void ppgtt_generate_shadow_entry(struct intel_gvt_gtt_entry *se,
		struct intel_vgpu_ppgtt_spt *s, struct intel_gvt_gtt_entry *ge)
{
	struct intel_gvt_gtt_pte_ops *ops = s->vgpu->gvt->gtt.pte_ops;

	se->type = ge->type;
	se->val64 = ge->val64;

	ops->set_pfn(se, s->shadow_page.mfn);
}

1040 1041 1042 1043 1044 1045
static int ppgtt_populate_shadow_entry(struct intel_vgpu *vgpu,
	struct intel_vgpu_ppgtt_spt *spt, unsigned long index,
	struct intel_gvt_gtt_entry *ge)
{
	struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
	struct intel_gvt_gtt_entry se = *ge;
1046 1047 1048
	unsigned long gfn;
	dma_addr_t dma_addr;
	int ret;
1049 1050 1051 1052 1053 1054 1055 1056 1057 1058

	if (!pte_ops->test_present(ge))
		return 0;

	gfn = pte_ops->get_pfn(ge);

	switch (ge->type) {
	case GTT_TYPE_PPGTT_PTE_4K_ENTRY:
		gvt_vdbg_mm("shadow 4K gtt entry\n");
		break;
1059
	case GTT_TYPE_PPGTT_PTE_64K_ENTRY:
1060 1061
	case GTT_TYPE_PPGTT_PTE_2M_ENTRY:
	case GTT_TYPE_PPGTT_PTE_1G_ENTRY:
1062
		gvt_vgpu_err("GVT doesn't support 64K/2M/1GB entry\n");
1063 1064 1065 1066 1067 1068
		return -EINVAL;
	default:
		GEM_BUG_ON(1);
	};

	/* direct shadow */
1069 1070
	ret = intel_gvt_hypervisor_dma_map_guest_page(vgpu, gfn, &dma_addr);
	if (ret)
1071 1072
		return -ENXIO;

1073
	pte_ops->set_pfn(&se, dma_addr >> PAGE_SHIFT);
1074 1075 1076 1077
	ppgtt_set_shadow_entry(spt, &se, index);
	return 0;
}

1078
static int ppgtt_populate_spt(struct intel_vgpu_ppgtt_spt *spt)
1079 1080
{
	struct intel_vgpu *vgpu = spt->vgpu;
1081 1082
	struct intel_gvt *gvt = vgpu->gvt;
	struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
1083 1084
	struct intel_vgpu_ppgtt_spt *s;
	struct intel_gvt_gtt_entry se, ge;
1085
	unsigned long gfn, i;
1086 1087 1088
	int ret;

	trace_spt_change(spt->vgpu->id, "born", spt,
1089
			 spt->guest_page.gfn, spt->shadow_page.type);
1090

1091 1092
	for_each_present_guest_entry(spt, &ge, i) {
		if (gtt_type_is_pt(get_next_pt_type(ge.type))) {
1093
			s = ppgtt_populate_spt_by_guest_entry(vgpu, &ge);
1094 1095 1096 1097 1098 1099 1100 1101
			if (IS_ERR(s)) {
				ret = PTR_ERR(s);
				goto fail;
			}
			ppgtt_get_shadow_entry(spt, &se, i);
			ppgtt_generate_shadow_entry(&se, s, &ge);
			ppgtt_set_shadow_entry(spt, &se, i);
		} else {