ahci.c 46 KB
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/*
 *  ahci.c - AHCI SATA support
 *
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 *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
 *    		    Please ALWAYS copy linux-ide@vger.kernel.org
 *		    on emails.
 *
 *  Copyright 2004-2005 Red Hat, Inc.
 *
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2, or (at your option)
 *  any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; see the file COPYING.  If not, write to
 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *
 * libata documentation is available via 'make {ps|pdf}docs',
 * as Documentation/DocBook/libata.*
 *
 * AHCI hardware documentation:
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 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
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 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
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 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
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#include <linux/dma-mapping.h>
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#include <linux/device.h>
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#include <scsi/scsi_host.h>
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#include <scsi/scsi_cmnd.h>
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#include <linux/libata.h>

#define DRV_NAME	"ahci"
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#define DRV_VERSION	"2.1"
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enum {
	AHCI_PCI_BAR		= 5,
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	AHCI_MAX_PORTS		= 32,
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	AHCI_MAX_SG		= 168, /* hardware max is 64K */
	AHCI_DMA_BOUNDARY	= 0xffffffff,
	AHCI_USE_CLUSTERING	= 0,
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	AHCI_MAX_CMDS		= 32,
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	AHCI_CMD_SZ		= 32,
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	AHCI_CMD_SLOT_SZ	= AHCI_MAX_CMDS * AHCI_CMD_SZ,
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	AHCI_RX_FIS_SZ		= 256,
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	AHCI_CMD_TBL_CDB	= 0x40,
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	AHCI_CMD_TBL_HDR_SZ	= 0x80,
	AHCI_CMD_TBL_SZ		= AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
	AHCI_CMD_TBL_AR_SZ	= AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
	AHCI_PORT_PRIV_DMA_SZ	= AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
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				  AHCI_RX_FIS_SZ,
	AHCI_IRQ_ON_SG		= (1 << 31),
	AHCI_CMD_ATAPI		= (1 << 5),
	AHCI_CMD_WRITE		= (1 << 6),
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	AHCI_CMD_PREFETCH	= (1 << 7),
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	AHCI_CMD_RESET		= (1 << 8),
	AHCI_CMD_CLR_BUSY	= (1 << 10),
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	RX_FIS_D2H_REG		= 0x40,	/* offset of D2H Register FIS data */
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	RX_FIS_SDB		= 0x58, /* offset of SDB FIS data */
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	RX_FIS_UNK		= 0x60, /* offset of Unknown FIS data */
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	board_ahci		= 0,
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	board_ahci_pi		= 1,
	board_ahci_vt8251	= 2,
	board_ahci_ign_iferr	= 3,
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	/* global controller registers */
	HOST_CAP		= 0x00, /* host capabilities */
	HOST_CTL		= 0x04, /* global host control */
	HOST_IRQ_STAT		= 0x08, /* interrupt status */
	HOST_PORTS_IMPL		= 0x0c, /* bitmap of implemented ports */
	HOST_VERSION		= 0x10, /* AHCI spec. version compliancy */

	/* HOST_CTL bits */
	HOST_RESET		= (1 << 0),  /* reset controller; self-clear */
	HOST_IRQ_EN		= (1 << 1),  /* global IRQ enable */
	HOST_AHCI_EN		= (1 << 31), /* AHCI enabled */

	/* HOST_CAP bits */
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	HOST_CAP_SSC		= (1 << 14), /* Slumber capable */
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	HOST_CAP_CLO		= (1 << 24), /* Command List Override support */
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	HOST_CAP_SSS		= (1 << 27), /* Staggered Spin-up */
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	HOST_CAP_NCQ		= (1 << 30), /* Native Command Queueing */
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	HOST_CAP_64		= (1 << 31), /* PCI DAC (64-bit DMA) support */
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	/* registers for each SATA port */
	PORT_LST_ADDR		= 0x00, /* command list DMA addr */
	PORT_LST_ADDR_HI	= 0x04, /* command list DMA addr hi */
	PORT_FIS_ADDR		= 0x08, /* FIS rx buf addr */
	PORT_FIS_ADDR_HI	= 0x0c, /* FIS rx buf addr hi */
	PORT_IRQ_STAT		= 0x10, /* interrupt status */
	PORT_IRQ_MASK		= 0x14, /* interrupt enable/disable mask */
	PORT_CMD		= 0x18, /* port command */
	PORT_TFDATA		= 0x20,	/* taskfile data */
	PORT_SIG		= 0x24,	/* device TF signature */
	PORT_CMD_ISSUE		= 0x38, /* command issue */
	PORT_SCR		= 0x28, /* SATA phy register block */
	PORT_SCR_STAT		= 0x28, /* SATA phy register: SStatus */
	PORT_SCR_CTL		= 0x2c, /* SATA phy register: SControl */
	PORT_SCR_ERR		= 0x30, /* SATA phy register: SError */
	PORT_SCR_ACT		= 0x34, /* SATA phy register: SActive */

	/* PORT_IRQ_{STAT,MASK} bits */
	PORT_IRQ_COLD_PRES	= (1 << 31), /* cold presence detect */
	PORT_IRQ_TF_ERR		= (1 << 30), /* task file error */
	PORT_IRQ_HBUS_ERR	= (1 << 29), /* host bus fatal error */
	PORT_IRQ_HBUS_DATA_ERR	= (1 << 28), /* host bus data error */
	PORT_IRQ_IF_ERR		= (1 << 27), /* interface fatal error */
	PORT_IRQ_IF_NONFATAL	= (1 << 26), /* interface non-fatal error */
	PORT_IRQ_OVERFLOW	= (1 << 24), /* xfer exhausted available S/G */
	PORT_IRQ_BAD_PMP	= (1 << 23), /* incorrect port multiplier */

	PORT_IRQ_PHYRDY		= (1 << 22), /* PhyRdy changed */
	PORT_IRQ_DEV_ILCK	= (1 << 7), /* device interlock */
	PORT_IRQ_CONNECT	= (1 << 6), /* port connect change status */
	PORT_IRQ_SG_DONE	= (1 << 5), /* descriptor processed */
	PORT_IRQ_UNK_FIS	= (1 << 4), /* unknown FIS rx'd */
	PORT_IRQ_SDB_FIS	= (1 << 3), /* Set Device Bits FIS rx'd */
	PORT_IRQ_DMAS_FIS	= (1 << 2), /* DMA Setup FIS rx'd */
	PORT_IRQ_PIOS_FIS	= (1 << 1), /* PIO Setup FIS rx'd */
	PORT_IRQ_D2H_REG_FIS	= (1 << 0), /* D2H Register FIS rx'd */

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	PORT_IRQ_FREEZE		= PORT_IRQ_HBUS_ERR |
				  PORT_IRQ_IF_ERR |
				  PORT_IRQ_CONNECT |
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				  PORT_IRQ_PHYRDY |
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				  PORT_IRQ_UNK_FIS,
	PORT_IRQ_ERROR		= PORT_IRQ_FREEZE |
				  PORT_IRQ_TF_ERR |
				  PORT_IRQ_HBUS_DATA_ERR,
	DEF_PORT_IRQ		= PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
				  PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
				  PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
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	/* PORT_CMD bits */
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	PORT_CMD_ATAPI		= (1 << 24), /* Device is ATAPI */
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	PORT_CMD_LIST_ON	= (1 << 15), /* cmd list DMA engine running */
	PORT_CMD_FIS_ON		= (1 << 14), /* FIS DMA engine running */
	PORT_CMD_FIS_RX		= (1 << 4), /* Enable FIS receive DMA engine */
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	PORT_CMD_CLO		= (1 << 3), /* Command list override */
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	PORT_CMD_POWER_ON	= (1 << 2), /* Power up device */
	PORT_CMD_SPIN_UP	= (1 << 1), /* Spin up device */
	PORT_CMD_START		= (1 << 0), /* Enable port DMA engine */

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	PORT_CMD_ICC_MASK	= (0xf << 28), /* i/f ICC state mask */
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	PORT_CMD_ICC_ACTIVE	= (0x1 << 28), /* Put i/f in active state */
	PORT_CMD_ICC_PARTIAL	= (0x2 << 28), /* Put i/f in partial state */
	PORT_CMD_ICC_SLUMBER	= (0x6 << 28), /* Put i/f in slumber state */
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	/* ap->flags bits */
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	AHCI_FLAG_NO_NCQ		= (1 << 24),
	AHCI_FLAG_IGN_IRQ_IF_ERR	= (1 << 25), /* ignore IRQ_IF_ERR */
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	AHCI_FLAG_HONOR_PI		= (1 << 26), /* honor PORTS_IMPL */
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};

struct ahci_cmd_hdr {
	u32			opts;
	u32			status;
	u32			tbl_addr;
	u32			tbl_addr_hi;
	u32			reserved[4];
};

struct ahci_sg {
	u32			addr;
	u32			addr_hi;
	u32			reserved;
	u32			flags_size;
};

struct ahci_host_priv {
	u32			cap;	/* cache of HOST_CAP register */
	u32			port_map; /* cache of HOST_PORTS_IMPL reg */
};

struct ahci_port_priv {
	struct ahci_cmd_hdr	*cmd_slot;
	dma_addr_t		cmd_slot_dma;
	void			*cmd_tbl;
	dma_addr_t		cmd_tbl_dma;
	void			*rx_fis;
	dma_addr_t		rx_fis_dma;
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	/* for NCQ spurious interrupt analysis */
	unsigned int		ncq_saw_d2h:1;
	unsigned int		ncq_saw_dmas:1;
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	unsigned int		ncq_saw_sdb:1;
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};

static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
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static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
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static irqreturn_t ahci_interrupt (int irq, void *dev_instance);
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static void ahci_irq_clear(struct ata_port *ap);
static int ahci_port_start(struct ata_port *ap);
static void ahci_port_stop(struct ata_port *ap);
static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
static void ahci_qc_prep(struct ata_queued_cmd *qc);
static u8 ahci_check_status(struct ata_port *ap);
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static void ahci_freeze(struct ata_port *ap);
static void ahci_thaw(struct ata_port *ap);
static void ahci_error_handler(struct ata_port *ap);
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static void ahci_vt8251_error_handler(struct ata_port *ap);
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static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
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static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
static int ahci_port_resume(struct ata_port *ap);
static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
static int ahci_pci_device_resume(struct pci_dev *pdev);
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static struct scsi_host_template ahci_sht = {
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	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
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	.change_queue_depth	= ata_scsi_change_queue_depth,
	.can_queue		= AHCI_MAX_CMDS - 1,
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	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= AHCI_MAX_SG,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= AHCI_USE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= AHCI_DMA_BOUNDARY,
	.slave_configure	= ata_scsi_slave_config,
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	.slave_destroy		= ata_scsi_slave_destroy,
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	.bios_param		= ata_std_bios_param,
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	.suspend		= ata_scsi_device_suspend,
	.resume			= ata_scsi_device_resume,
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};

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static const struct ata_port_operations ahci_ops = {
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	.port_disable		= ata_port_disable,

	.check_status		= ahci_check_status,
	.check_altstatus	= ahci_check_status,
	.dev_select		= ata_noop_dev_select,

	.tf_read		= ahci_tf_read,

	.qc_prep		= ahci_qc_prep,
	.qc_issue		= ahci_qc_issue,

	.irq_handler		= ahci_interrupt,
	.irq_clear		= ahci_irq_clear,
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	.irq_on			= ata_dummy_irq_on,
	.irq_ack		= ata_dummy_irq_ack,
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	.scr_read		= ahci_scr_read,
	.scr_write		= ahci_scr_write,

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	.freeze			= ahci_freeze,
	.thaw			= ahci_thaw,

	.error_handler		= ahci_error_handler,
	.post_internal_cmd	= ahci_post_internal_cmd,

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	.port_suspend		= ahci_port_suspend,
	.port_resume		= ahci_port_resume,

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	.port_start		= ahci_port_start,
	.port_stop		= ahci_port_stop,
};

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static const struct ata_port_operations ahci_vt8251_ops = {
	.port_disable		= ata_port_disable,

	.check_status		= ahci_check_status,
	.check_altstatus	= ahci_check_status,
	.dev_select		= ata_noop_dev_select,

	.tf_read		= ahci_tf_read,

	.qc_prep		= ahci_qc_prep,
	.qc_issue		= ahci_qc_issue,

	.irq_handler		= ahci_interrupt,
	.irq_clear		= ahci_irq_clear,
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	.irq_on			= ata_dummy_irq_on,
	.irq_ack		= ata_dummy_irq_ack,
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	.scr_read		= ahci_scr_read,
	.scr_write		= ahci_scr_write,

	.freeze			= ahci_freeze,
	.thaw			= ahci_thaw,

	.error_handler		= ahci_vt8251_error_handler,
	.post_internal_cmd	= ahci_post_internal_cmd,

	.port_suspend		= ahci_port_suspend,
	.port_resume		= ahci_port_resume,

	.port_start		= ahci_port_start,
	.port_stop		= ahci_port_stop,
};

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static const struct ata_port_info ahci_port_info[] = {
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	/* board_ahci */
	{
		.sht		= &ahci_sht,
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		.flags		= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
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				  ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
				  ATA_FLAG_SKIP_D2H_BSY,
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		.pio_mask	= 0x1f, /* pio0-4 */
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		.udma_mask	= 0x7f, /* udma0-6 ; FIXME */
		.port_ops	= &ahci_ops,
	},
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	/* board_ahci_pi */
	{
		.sht		= &ahci_sht,
		.flags		= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
				  ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
				  ATA_FLAG_SKIP_D2H_BSY | AHCI_FLAG_HONOR_PI,
		.pio_mask	= 0x1f, /* pio0-4 */
		.udma_mask	= 0x7f, /* udma0-6 ; FIXME */
		.port_ops	= &ahci_ops,
	},
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	/* board_ahci_vt8251 */
	{
		.sht		= &ahci_sht,
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		.flags		= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
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				  ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
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				  ATA_FLAG_SKIP_D2H_BSY |
				  ATA_FLAG_HRST_TO_RESUME | AHCI_FLAG_NO_NCQ,
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		.pio_mask	= 0x1f, /* pio0-4 */
		.udma_mask	= 0x7f, /* udma0-6 ; FIXME */
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		.port_ops	= &ahci_vt8251_ops,
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	},
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	/* board_ahci_ign_iferr */
	{
		.sht		= &ahci_sht,
		.flags		= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
				  ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
				  ATA_FLAG_SKIP_D2H_BSY |
				  AHCI_FLAG_IGN_IRQ_IF_ERR,
		.pio_mask	= 0x1f, /* pio0-4 */
		.udma_mask	= 0x7f, /* udma0-6 ; FIXME */
		.port_ops	= &ahci_ops,
	},
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};

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static const struct pci_device_id ahci_pci_tbl[] = {
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	/* Intel */
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	{ PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
	{ PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
	{ PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
	{ PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
	{ PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
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	{ PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
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	{ PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
	{ PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
	{ PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
	{ PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
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	{ PCI_VDEVICE(INTEL, 0x2821), board_ahci_pi }, /* ICH8 */
	{ PCI_VDEVICE(INTEL, 0x2822), board_ahci_pi }, /* ICH8 */
	{ PCI_VDEVICE(INTEL, 0x2824), board_ahci_pi }, /* ICH8 */
	{ PCI_VDEVICE(INTEL, 0x2829), board_ahci_pi }, /* ICH8M */
	{ PCI_VDEVICE(INTEL, 0x282a), board_ahci_pi }, /* ICH8M */
	{ PCI_VDEVICE(INTEL, 0x2922), board_ahci_pi }, /* ICH9 */
	{ PCI_VDEVICE(INTEL, 0x2923), board_ahci_pi }, /* ICH9 */
	{ PCI_VDEVICE(INTEL, 0x2924), board_ahci_pi }, /* ICH9 */
	{ PCI_VDEVICE(INTEL, 0x2925), board_ahci_pi }, /* ICH9 */
	{ PCI_VDEVICE(INTEL, 0x2927), board_ahci_pi }, /* ICH9 */
	{ PCI_VDEVICE(INTEL, 0x2929), board_ahci_pi }, /* ICH9M */
	{ PCI_VDEVICE(INTEL, 0x292a), board_ahci_pi }, /* ICH9M */
	{ PCI_VDEVICE(INTEL, 0x292b), board_ahci_pi }, /* ICH9M */
	{ PCI_VDEVICE(INTEL, 0x292f), board_ahci_pi }, /* ICH9M */
	{ PCI_VDEVICE(INTEL, 0x294d), board_ahci_pi }, /* ICH9 */
	{ PCI_VDEVICE(INTEL, 0x294e), board_ahci_pi }, /* ICH9M */
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	/* JMicron 360/1/3/5/6, match class to avoid IDE function */
	{ PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
	  PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
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	/* ATI */
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	{ PCI_VDEVICE(ATI, 0x4380), board_ahci }, /* ATI SB600 non-raid */
	{ PCI_VDEVICE(ATI, 0x4381), board_ahci }, /* ATI SB600 raid */
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	/* VIA */
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	{ PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
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	/* NVIDIA */
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	{ PCI_VDEVICE(NVIDIA, 0x044c), board_ahci },		/* MCP65 */
	{ PCI_VDEVICE(NVIDIA, 0x044d), board_ahci },		/* MCP65 */
	{ PCI_VDEVICE(NVIDIA, 0x044e), board_ahci },		/* MCP65 */
	{ PCI_VDEVICE(NVIDIA, 0x044f), board_ahci },		/* MCP65 */
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	{ PCI_VDEVICE(NVIDIA, 0x045c), board_ahci },		/* MCP65 */
	{ PCI_VDEVICE(NVIDIA, 0x045d), board_ahci },		/* MCP65 */
	{ PCI_VDEVICE(NVIDIA, 0x045e), board_ahci },		/* MCP65 */
	{ PCI_VDEVICE(NVIDIA, 0x045f), board_ahci },		/* MCP65 */
	{ PCI_VDEVICE(NVIDIA, 0x0550), board_ahci },		/* MCP67 */
	{ PCI_VDEVICE(NVIDIA, 0x0551), board_ahci },		/* MCP67 */
	{ PCI_VDEVICE(NVIDIA, 0x0552), board_ahci },		/* MCP67 */
	{ PCI_VDEVICE(NVIDIA, 0x0553), board_ahci },		/* MCP67 */
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	{ PCI_VDEVICE(NVIDIA, 0x0554), board_ahci },		/* MCP67 */
	{ PCI_VDEVICE(NVIDIA, 0x0555), board_ahci },		/* MCP67 */
	{ PCI_VDEVICE(NVIDIA, 0x0556), board_ahci },		/* MCP67 */
	{ PCI_VDEVICE(NVIDIA, 0x0557), board_ahci },		/* MCP67 */
	{ PCI_VDEVICE(NVIDIA, 0x0558), board_ahci },		/* MCP67 */
	{ PCI_VDEVICE(NVIDIA, 0x0559), board_ahci },		/* MCP67 */
	{ PCI_VDEVICE(NVIDIA, 0x055a), board_ahci },		/* MCP67 */
	{ PCI_VDEVICE(NVIDIA, 0x055b), board_ahci },		/* MCP67 */
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	/* SiS */
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	{ PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
	{ PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
	{ PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
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	/* Generic, PCI class code for AHCI */
	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
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	  PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
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	{ }	/* terminate list */
};


static struct pci_driver ahci_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= ahci_pci_tbl,
	.probe			= ahci_init_one,
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	.remove			= ata_pci_remove_one,
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	.suspend		= ahci_pci_device_suspend,
	.resume			= ahci_pci_device_resume,
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};


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static inline int ahci_nr_ports(u32 cap)
{
	return (cap & 0x1f) + 1;
}

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static inline void __iomem *ahci_port_base(void __iomem *base,
					   unsigned int port)
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{
	return base + 0x100 + (port * 0x80);
}

static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
{
	unsigned int sc_reg;

	switch (sc_reg_in) {
	case SCR_STATUS:	sc_reg = 0; break;
	case SCR_CONTROL:	sc_reg = 1; break;
	case SCR_ERROR:		sc_reg = 2; break;
	case SCR_ACTIVE:	sc_reg = 3; break;
	default:
		return 0xffffffffU;
	}

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	return readl(ap->ioaddr.scr_addr + (sc_reg * 4));
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}


static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
			       u32 val)
{
	unsigned int sc_reg;

	switch (sc_reg_in) {
	case SCR_STATUS:	sc_reg = 0; break;
	case SCR_CONTROL:	sc_reg = 1; break;
	case SCR_ERROR:		sc_reg = 2; break;
	case SCR_ACTIVE:	sc_reg = 3; break;
	default:
		return;
	}

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	writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
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}

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static void ahci_start_engine(void __iomem *port_mmio)
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{
	u32 tmp;

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	/* start DMA */
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	tmp = readl(port_mmio + PORT_CMD);
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	tmp |= PORT_CMD_START;
	writel(tmp, port_mmio + PORT_CMD);
	readl(port_mmio + PORT_CMD); /* flush */
}

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static int ahci_stop_engine(void __iomem *port_mmio)
{
	u32 tmp;

	tmp = readl(port_mmio + PORT_CMD);

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	/* check if the HBA is idle */
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	if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
		return 0;

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	/* setting HBA to idle */
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	tmp &= ~PORT_CMD_START;
	writel(tmp, port_mmio + PORT_CMD);

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	/* wait for engine to stop. This could be as long as 500 msec */
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	tmp = ata_wait_register(port_mmio + PORT_CMD,
			        PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
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	if (tmp & PORT_CMD_LIST_ON)
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		return -EIO;

	return 0;
}

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static void ahci_start_fis_rx(void __iomem *port_mmio, u32 cap,
			      dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma)
{
	u32 tmp;

	/* set FIS registers */
	if (cap & HOST_CAP_64)
		writel((cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
	writel(cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);

	if (cap & HOST_CAP_64)
		writel((rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
	writel(rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);

	/* enable FIS reception */
	tmp = readl(port_mmio + PORT_CMD);
	tmp |= PORT_CMD_FIS_RX;
	writel(tmp, port_mmio + PORT_CMD);

	/* flush */
	readl(port_mmio + PORT_CMD);
}

static int ahci_stop_fis_rx(void __iomem *port_mmio)
{
	u32 tmp;

	/* disable FIS reception */
	tmp = readl(port_mmio + PORT_CMD);
	tmp &= ~PORT_CMD_FIS_RX;
	writel(tmp, port_mmio + PORT_CMD);

	/* wait for completion, spec says 500ms, give it 1000 */
	tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
				PORT_CMD_FIS_ON, 10, 1000);
	if (tmp & PORT_CMD_FIS_ON)
		return -EBUSY;

	return 0;
}

static void ahci_power_up(void __iomem *port_mmio, u32 cap)
{
	u32 cmd;

	cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;

	/* spin up device */
	if (cap & HOST_CAP_SSS) {
		cmd |= PORT_CMD_SPIN_UP;
		writel(cmd, port_mmio + PORT_CMD);
	}

	/* wake up link */
	writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
}

static void ahci_power_down(void __iomem *port_mmio, u32 cap)
{
	u32 cmd, scontrol;

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	if (!(cap & HOST_CAP_SSS))
		return;
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	/* put device into listen mode, first set PxSCTL.DET to 0 */
	scontrol = readl(port_mmio + PORT_SCR_CTL);
	scontrol &= ~0xf;
	writel(scontrol, port_mmio + PORT_SCR_CTL);
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	/* then set PxCMD.SUD to 0 */
	cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
	cmd &= ~PORT_CMD_SPIN_UP;
	writel(cmd, port_mmio + PORT_CMD);
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}

static void ahci_init_port(void __iomem *port_mmio, u32 cap,
			   dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma)
{
	/* enable FIS reception */
	ahci_start_fis_rx(port_mmio, cap, cmd_slot_dma, rx_fis_dma);

	/* enable DMA */
	ahci_start_engine(port_mmio);
}

static int ahci_deinit_port(void __iomem *port_mmio, u32 cap, const char **emsg)
{
	int rc;

	/* disable DMA */
	rc = ahci_stop_engine(port_mmio);
	if (rc) {
		*emsg = "failed to stop engine";
		return rc;
	}

	/* disable FIS reception */
	rc = ahci_stop_fis_rx(port_mmio);
	if (rc) {
		*emsg = "failed stop FIS RX";
		return rc;
	}

	return 0;
}

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static int ahci_reset_controller(void __iomem *mmio, struct pci_dev *pdev)
{
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	u32 cap_save, impl_save, tmp;
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	cap_save = readl(mmio + HOST_CAP);
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	impl_save = readl(mmio + HOST_PORTS_IMPL);
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	/* global controller reset */
	tmp = readl(mmio + HOST_CTL);
	if ((tmp & HOST_RESET) == 0) {
		writel(tmp | HOST_RESET, mmio + HOST_CTL);
		readl(mmio + HOST_CTL); /* flush */
	}

	/* reset must complete within 1 second, or
	 * the hardware should be considered fried.
	 */
	ssleep(1);

	tmp = readl(mmio + HOST_CTL);
	if (tmp & HOST_RESET) {
		dev_printk(KERN_ERR, &pdev->dev,
			   "controller reset failed (0x%x)\n", tmp);
		return -EIO;
	}

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	/* turn on AHCI mode */
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	writel(HOST_AHCI_EN, mmio + HOST_CTL);
	(void) readl(mmio + HOST_CTL);	/* flush */
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	/* These write-once registers are normally cleared on reset.
	 * Restore BIOS values... which we HOPE were present before
	 * reset.
	 */
	if (!impl_save) {
		impl_save = (1 << ahci_nr_ports(cap_save)) - 1;
		dev_printk(KERN_WARNING, &pdev->dev,
			   "PORTS_IMPL is zero, forcing 0x%x\n", impl_save);
	}
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	writel(cap_save, mmio + HOST_CAP);
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	writel(impl_save, mmio + HOST_PORTS_IMPL);
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	(void) readl(mmio + HOST_PORTS_IMPL);	/* flush */

	if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
		u16 tmp16;

		/* configure PCS */
		pci_read_config_word(pdev, 0x92, &tmp16);
		tmp16 |= 0xf;
		pci_write_config_word(pdev, 0x92, tmp16);
	}

	return 0;
}

static void ahci_init_controller(void __iomem *mmio, struct pci_dev *pdev,
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				 int n_ports, unsigned int port_flags,
				 struct ahci_host_priv *hpriv)
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{
	int i, rc;
	u32 tmp;

	for (i = 0; i < n_ports; i++) {
		void __iomem *port_mmio = ahci_port_base(mmio, i);
		const char *emsg = NULL;

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		if ((port_flags & AHCI_FLAG_HONOR_PI) &&
		    !(hpriv->port_map & (1 << i)))
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			continue;

		/* make sure port is not active */
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		rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
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		if (rc)
			dev_printk(KERN_WARNING, &pdev->dev,
				   "%s (%d)\n", emsg, rc);

		/* clear SError */
		tmp = readl(port_mmio + PORT_SCR_ERR);
		VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
		writel(tmp, port_mmio + PORT_SCR_ERR);

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		/* clear port IRQ */
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		tmp = readl(port_mmio + PORT_IRQ_STAT);
		VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
		if (tmp)
			writel(tmp, port_mmio + PORT_IRQ_STAT);

		writel(1 << i, mmio + HOST_IRQ_STAT);
	}

	tmp = readl(mmio + HOST_CTL);
	VPRINTK("HOST_CTL 0x%x\n", tmp);
	writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
	tmp = readl(mmio + HOST_CTL);
	VPRINTK("HOST_CTL 0x%x\n", tmp);
}

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static unsigned int ahci_dev_classify(struct ata_port *ap)
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{
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	void __iomem *port_mmio = ap->ioaddr.cmd_addr;
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	struct ata_taskfile tf;
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	u32 tmp;

	tmp = readl(port_mmio + PORT_SIG);
	tf.lbah		= (tmp >> 24)	& 0xff;
	tf.lbam		= (tmp >> 16)	& 0xff;
	tf.lbal		= (tmp >> 8)	& 0xff;
	tf.nsect	= (tmp)		& 0xff;

	return ata_dev_classify(&tf);
}

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static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
			       u32 opts)
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{
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	dma_addr_t cmd_tbl_dma;

	cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;

	pp->cmd_slot[tag].opts = cpu_to_le32(opts);
	pp->cmd_slot[tag].status = 0;
	pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
	pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
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}

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static int ahci_clo(struct ata_port *ap)
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{
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	void __iomem *port_mmio = ap->ioaddr.cmd_addr;
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	struct ahci_host_priv *hpriv = ap->host->private_data;
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	u32 tmp;

	if (!(hpriv->cap & HOST_CAP_CLO))
		return -EOPNOTSUPP;

	tmp = readl(port_mmio + PORT_CMD);
	tmp |= PORT_CMD_CLO;
	writel(tmp, port_mmio + PORT_CMD);

	tmp = ata_wait_register(port_mmio + PORT_CMD,
				PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
	if (tmp & PORT_CMD_CLO)
		return -EIO;

	return 0;
}

static int ahci_softreset(struct ata_port *ap, unsigned int *class)
{
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	struct ahci_port_priv *pp = ap->private_data;
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	void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
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	void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
	const u32 cmd_fis_len = 5; /* five dwords */
	const char *reason = NULL;
	struct ata_taskfile tf;
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	u32 tmp;
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	u8 *fis;
	int rc;

	DPRINTK("ENTER\n");

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	if (ata_port_offline(ap)) {
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		DPRINTK("PHY reports no device\n");
		*class = ATA_DEV_NONE;
		return 0;
	}

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	/* prepare for SRST (AHCI-1.1 10.4.1) */
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	rc = ahci_stop_engine(port_mmio);
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	if (rc) {
		reason = "failed to stop engine";
		goto fail_restart;
	}

	/* check BUSY/DRQ, perform Command List Override if necessary */
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	if (ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ)) {
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		rc = ahci_clo(ap);
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		if (rc == -EOPNOTSUPP) {
			reason = "port busy but CLO unavailable";
			goto fail_restart;
		} else if (rc) {
			reason = "port busy but CLO failed";
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			goto fail_restart;
		}
	}

	/* restart engine */
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	ahci_start_engine(port_mmio);
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	ata_tf_init(ap->device, &tf);
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	fis = pp->cmd_tbl;

	/* issue the first D2H Register FIS */
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	ahci_fill_cmd_slot(pp, 0,
			   cmd_fis_len | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY);
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	tf.ctl |= ATA_SRST;
	ata_tf_to_fis(&tf, fis, 0);
	fis[1] &= ~(1 << 7);	/* turn off Command FIS bit */

	writel(1, port_mmio + PORT_CMD_ISSUE);

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	tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, 1, 500);
	if (tmp & 0x1) {
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		rc = -EIO;
		reason = "1st FIS failed";
		goto fail;
	}

	/* spec says at least 5us, but be generous and sleep for 1ms */
	msleep(1);

	/* issue the second D2H Register FIS */
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	ahci_fill_cmd_slot(pp, 0, cmd_fis_len);
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	tf.ctl &= ~ATA_SRST;
	ata_tf_to_fis(&tf, fis, 0);
	fis[1] &= ~(1 << 7);	/* turn off Command FIS bit */

	writel(1, port_mmio + PORT_CMD_ISSUE);
	readl(port_mmio + PORT_CMD_ISSUE);	/* flush */

	/* spec mandates ">= 2ms" before checking status.
	 * We wait 150ms, because that was the magic delay used for
	 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
	 * between when the ATA command register is written, and then
	 * status is checked.  Because waiting for "a while" before
	 * checking status is fine, post SRST, we perform this magic
	 * delay here as well.
	 */
	msleep(150);

	*class = ATA_DEV_NONE;
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	if (ata_port_online(ap)) {
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		if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
			rc = -EIO;
			reason = "device not ready";
			goto fail;
		}
		*class = ahci_dev_classify(ap);
	}

	DPRINTK("EXIT, class=%u\n", *class);
	return 0;

 fail_restart:
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	ahci_start_engine(port_mmio);
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 fail:
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	ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
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	return rc;
}

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static int ahci_hardreset(struct ata_port *ap, unsigned int *class)
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{
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	struct ahci_port_priv *pp = ap->private_data;
	u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
	struct ata_taskfile tf;
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	void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
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	void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
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	int rc;

	DPRINTK("ENTER\n");
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	ahci_stop_engine(port_mmio);
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	/* clear D2H reception area to properly wait for D2H FIS */
	ata_tf_init(ap->device, &tf);
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	tf.command = 0x80;
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	ata_tf_to_fis(&tf, d2h_fis, 0);

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	rc = sata_std_hardreset(ap, class);
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	ahci_start_engine(port_mmio);
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	if (rc == 0 && ata_port_online(ap))
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		*class = ahci_dev_classify(ap);
	if (*class == ATA_DEV_UNKNOWN)
		*class = ATA_DEV_NONE;
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	DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
	return rc;
}

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static int ahci_vt8251_hardreset(struct ata_port *ap, unsigned int *class)
{
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	void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
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	void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
	int rc;

	DPRINTK("ENTER\n");

	ahci_stop_engine(port_mmio);

	rc = sata_port_hardreset(ap, sata_ehc_deb_timing(&ap->eh_context));

	/* vt8251 needs SError cleared for the port to operate */
	ahci_scr_write(ap, SCR_ERROR, ahci_scr_read(ap, SCR_ERROR));

	ahci_start_engine(port_mmio);

	DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);

	/* vt8251 doesn't clear BSY on signature FIS reception,
	 * request follow-up softreset.
	 */
	return rc ?: -EAGAIN;
}

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static void ahci_postreset(struct ata_port *ap, unsigned int *class)
{
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	void __iomem *port_mmio = ap->ioaddr.cmd_addr;
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	u32 new_tmp, tmp;

	ata_std_postreset(ap, class);
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	/* Make sure port's ATAPI bit is set appropriately */
	new_tmp = tmp = readl(port_mmio + PORT_CMD);
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	if (*class == ATA_DEV_ATAPI)
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		new_tmp |= PORT_CMD_ATAPI;
	else
		new_tmp &= ~PORT_CMD_ATAPI;
	if (new_tmp != tmp) {
		writel(new_tmp, port_mmio + PORT_CMD);
		readl(port_mmio + PORT_CMD); /* flush */
	}
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}

static u8 ahci_check_status(struct ata_port *ap)
{
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	void __iomem *mmio = ap->ioaddr.cmd_addr;
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	return readl(mmio + PORT_TFDATA) & 0xFF;
}

static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
{
	struct ahci_port_priv *pp = ap->private_data;
	u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;

	ata_tf_from_fis(d2h_fis, tf);
}

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static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
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{
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	struct scatterlist *sg;
	struct ahci_sg *ahci_sg;
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	unsigned int n_sg = 0;
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	VPRINTK("ENTER\n");

	/*
	 * Next, the S/G list.
	 */
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	ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
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	ata_for_each_sg(sg, qc) {
		dma_addr_t addr = sg_dma_address(sg);
		u32 sg_len = sg_dma_len(sg);

		ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
		ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
		ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
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		ahci_sg++;
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		n_sg++;
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	}
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	return n_sg;
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}

static void ahci_qc_prep(struct ata_queued_cmd *qc)
{
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	struct ata_port *ap = qc->ap;
	struct ahci_port_priv *pp = ap->private_data;
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	int is_atapi = is_atapi_taskfile(&qc->tf);
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	void *cmd_tbl;
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	u32 opts;
	const u32 cmd_fis_len = 5; /* five dwords */
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	unsigned int n_elem;
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	/*
	 * Fill in command table information.  First, the header,
	 * a SATA Register - Host to Device command FIS.
	 */
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	cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;

	ata_tf_to_fis(&qc->tf, cmd_tbl, 0);
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	if (is_atapi) {
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		memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
		memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
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	}
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	n_elem = 0;
	if (qc->flags & ATA_QCFLAG_DMAMAP)
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		n_elem = ahci_fill_sg(qc, cmd_tbl);
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	/*
	 * Fill in command slot information.
	 */
	opts = cmd_fis_len | n_elem << 16;
	if (qc->tf.flags & ATA_TFLAG_WRITE)
		opts |= AHCI_CMD_WRITE;
	if (is_atapi)
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		opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
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	ahci_fill_cmd_slot(pp, qc->tag, opts);
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}

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static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
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{
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	struct ahci_port_priv *pp = ap->private_data;
	struct ata_eh_info *ehi = &ap->eh_info;
	unsigned int err_mask = 0, action = 0;
	struct ata_queued_cmd *qc;
	u32 serror;
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	ata_ehi_clear_desc(ehi);
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	/* AHCI needs SError cleared; otherwise, it might lock up */
	serror = ahci_scr_read(ap, SCR_ERROR);
	ahci_scr_write(ap, SCR_ERROR, serror);
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	/* analyze @irq_stat */
	ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);

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	/* some controllers set IRQ_IF_ERR on device errors, ignore it */
	if (ap->flags & AHCI_FLAG_IGN_IRQ_IF_ERR)
		irq_stat &= ~PORT_IRQ_IF_ERR;

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	if (irq_stat & PORT_IRQ_TF_ERR)
		err_mask |= AC_ERR_DEV;

	if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
		err_mask |= AC_ERR_HOST_BUS;
		action |= ATA_EH_SOFTRESET;
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	}

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	if (irq_stat & PORT_IRQ_IF_ERR) {
		err_mask |= AC_ERR_ATA_BUS;
		action |= ATA_EH_SOFTRESET;
		ata_ehi_push_desc(ehi, ", interface fatal error");
	}
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	if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
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		ata_ehi_hotplugged(ehi);
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		ata_ehi_push_desc(ehi, ", %s", irq_stat & PORT_IRQ_CONNECT ?
			"connection status changed" : "PHY RDY changed");
	}

	if (irq_stat & PORT_IRQ_UNK_FIS) {
		u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
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		err_mask |= AC_ERR_HSM;
		action |= ATA_EH_SOFTRESET;
		ata_ehi_push_desc(ehi, ", unknown FIS %08x %08x %08x %08x",
				  unk[0], unk[1], unk[2], unk[3]);
	}
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	/* okay, let's hand over to EH */
	ehi->serror |= serror;
	ehi->action |= action;
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	qc = ata_qc_from_tag(ap, ap->active_tag);
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	if (qc)
		qc->err_mask |= err_mask;
	else
		ehi->err_mask |= err_mask;
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	if (irq_stat & PORT_IRQ_FREEZE)
		ata_port_freeze(ap);
	else
		ata_port_abort(ap);
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}

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static void ahci_host_intr(struct ata_port *ap)
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{
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	void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
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	void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
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	struct ata_eh_info *ehi = &ap->eh_info;
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	struct ahci_port_priv *pp = ap->private_data;
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	u32 status, qc_active;
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	int rc, known_irq = 0;
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	status = readl(port_mmio + PORT_IRQ_STAT);
	writel(status, port_mmio + PORT_IRQ_STAT);

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	if (unlikely(status & PORT_IRQ_ERROR)) {
		ahci_error_intr(ap, status);
		return;
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	}

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	if (ap->sactive)
		qc_active = readl(port_mmio + PORT_SCR_ACT);
	else
		qc_active = readl(port_mmio + PORT_CMD_ISSUE);

	rc = ata_qc_complete_multiple(ap, qc_active, NULL);
	if (rc > 0)
		return;
	if (rc < 0) {
		ehi->err_mask |= AC_ERR_HSM;
		ehi->action |= ATA_EH_SOFTRESET;
		ata_port_freeze(ap);
		return;
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	}

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	/* hmmm... a spurious interupt */

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	/* if !NCQ, ignore.  No modern ATA device has broken HSM
	 * implementation for non-NCQ commands.
	 */
	if (!ap->sactive)
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		return;

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	if (status & PORT_IRQ_D2H_REG_FIS) {
		if (!pp->ncq_saw_d2h)
			ata_port_printk(ap, KERN_INFO,
				"D2H reg with I during NCQ, "
				"this message won't be printed again\n");
		pp->ncq_saw_d2h = 1;
		known_irq = 1;
	}

	if (status & PORT_IRQ_DMAS_FIS) {
		if (!pp->ncq_saw_dmas)
			ata_port_printk(ap, KERN_INFO,
				"DMAS FIS during NCQ, "
				"this message won't be printed again\n");
		pp->ncq_saw_dmas = 1;
		known_irq = 1;
	}

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	if (status & PORT_IRQ_SDB_FIS) {
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		const __le32 *f = pp->rx_fis + RX_FIS_SDB;
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		if (le32_to_cpu(f[1])) {
			/* SDB FIS containing spurious completions
			 * might be dangerous, whine and fail commands
			 * with HSM violation.  EH will turn off NCQ
			 * after several such failures.
			 */
			ata_ehi_push_desc(ehi,
				"spurious completions during NCQ "
				"issue=0x%x SAct=0x%x FIS=%08x:%08x",
				readl(port_mmio + PORT_CMD_ISSUE),
				readl(port_mmio + PORT_SCR_ACT),
				le32_to_cpu(f[0]), le32_to_cpu(f[1]));
			ehi->err_mask |= AC_ERR_HSM;
			ehi->action |= ATA_EH_SOFTRESET;
			ata_port_freeze(ap);
		} else {
			if (!pp->ncq_saw_sdb)
				ata_port_printk(ap, KERN_INFO,
					"spurious SDB FIS %08x:%08x during NCQ, "
					"this message won't be printed again\n",
					le32_to_cpu(f[0]), le32_to_cpu(f[1]));
			pp->ncq_saw_sdb = 1;
		}
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		known_irq = 1;
	}
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	if (!known_irq)
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		ata_port_printk(ap, KERN_INFO, "spurious interrupt "
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				"(irq_stat 0x%x active_tag 0x%x sactive 0x%x)\n",
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				status, ap->active_tag, ap->sactive);
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}

static void ahci_irq_clear(struct ata_port *ap)
{
	/* TODO */
}

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static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
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{
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	struct ata_host *host = dev_instance;
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	struct ahci_host_priv *hpriv;
	unsigned int i, handled = 0;
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	void __iomem *mmio;
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	u32 irq_stat, irq_ack = 0;

	VPRINTK("ENTER\n");

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	hpriv = host->private_data;
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	mmio = host->iomap[AHCI_PCI_BAR];
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	/* sigh.  0xffffffff is a valid return from h/w */
	irq_stat = readl(mmio + HOST_IRQ_STAT);
	irq_stat &= hpriv->port_map;
	if (!irq_stat)
		return IRQ_NONE;

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        spin_lock(&host->lock);
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        for (i = 0; i < host->n_ports; i++) {
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		struct ata_port *ap;

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		if (!(irq_stat & (1 << i)))
			continue;

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		ap = host->ports[i];
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		if (ap) {
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			ahci_host_intr(ap);
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			VPRINTK("port %u\n", i);
		} else {
			VPRINTK("port %u (no irq)\n", i);
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			if (ata_ratelimit())
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				dev_printk(KERN_WARNING, host->dev,
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					"interrupt on disabled port %u\n", i);
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		}
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		irq_ack |= (1 << i);
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	}

	if (irq_ack) {
		writel(irq_ack, mmio + HOST_IRQ_STAT);
		handled = 1;
	}

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