gtt.c 63 KB
Newer Older
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
/*
 * GTT virtualization
 *
 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 *
 * Authors:
 *    Zhi Wang <zhi.a.wang@intel.com>
 *    Zhenyu Wang <zhenyuw@linux.intel.com>
 *    Xiao Zheng <xiao.zheng@intel.com>
 *
 * Contributors:
 *    Min He <min.he@intel.com>
 *    Bing Niu <bing.niu@intel.com>
 *
 */

#include "i915_drv.h"
37 38
#include "gvt.h"
#include "i915_pvinfo.h"
39 40
#include "trace.h"

41 42 43 44 45 46
#if defined(VERBOSE_DEBUG)
#define gvt_vdbg_mm(fmt, args...) gvt_dbg_mm(fmt, ##args)
#else
#define gvt_vdbg_mm(fmt, args...)
#endif

47 48 49 50 51 52 53 54 55 56 57
static bool enable_out_of_sync = false;
static int preallocated_oos_pages = 8192;

/*
 * validate a gm address and related range size,
 * translate it to host gm address
 */
bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size)
{
	if ((!vgpu_gmadr_is_valid(vgpu, addr)) || (size
			&& !vgpu_gmadr_is_valid(vgpu, addr + size - 1))) {
58 59
		gvt_vgpu_err("invalid range gmadr 0x%llx size 0x%x\n",
				addr, size);
60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102
		return false;
	}
	return true;
}

/* translate a guest gmadr to host gmadr */
int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr)
{
	if (WARN(!vgpu_gmadr_is_valid(vgpu, g_addr),
		 "invalid guest gmadr %llx\n", g_addr))
		return -EACCES;

	if (vgpu_gmadr_is_aperture(vgpu, g_addr))
		*h_addr = vgpu_aperture_gmadr_base(vgpu)
			  + (g_addr - vgpu_aperture_offset(vgpu));
	else
		*h_addr = vgpu_hidden_gmadr_base(vgpu)
			  + (g_addr - vgpu_hidden_offset(vgpu));
	return 0;
}

/* translate a host gmadr to guest gmadr */
int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr)
{
	if (WARN(!gvt_gmadr_is_valid(vgpu->gvt, h_addr),
		 "invalid host gmadr %llx\n", h_addr))
		return -EACCES;

	if (gvt_gmadr_is_aperture(vgpu->gvt, h_addr))
		*g_addr = vgpu_aperture_gmadr_base(vgpu)
			+ (h_addr - gvt_aperture_gmadr_base(vgpu->gvt));
	else
		*g_addr = vgpu_hidden_gmadr_base(vgpu)
			+ (h_addr - gvt_hidden_gmadr_base(vgpu->gvt));
	return 0;
}

int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu, unsigned long g_index,
			     unsigned long *h_index)
{
	u64 h_addr;
	int ret;

103
	ret = intel_gvt_ggtt_gmadr_g2h(vgpu, g_index << I915_GTT_PAGE_SHIFT,
104 105 106 107
				       &h_addr);
	if (ret)
		return ret;

108
	*h_index = h_addr >> I915_GTT_PAGE_SHIFT;
109 110 111 112 113 114 115 116 117
	return 0;
}

int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index,
			     unsigned long *g_index)
{
	u64 g_addr;
	int ret;

118
	ret = intel_gvt_ggtt_gmadr_h2g(vgpu, h_index << I915_GTT_PAGE_SHIFT,
119 120 121 122
				       &g_addr);
	if (ret)
		return ret;

123
	*g_index = g_addr >> I915_GTT_PAGE_SHIFT;
124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164
	return 0;
}

#define gtt_type_is_entry(type) \
	(type > GTT_TYPE_INVALID && type < GTT_TYPE_PPGTT_ENTRY \
	 && type != GTT_TYPE_PPGTT_PTE_ENTRY \
	 && type != GTT_TYPE_PPGTT_ROOT_ENTRY)

#define gtt_type_is_pt(type) \
	(type >= GTT_TYPE_PPGTT_PTE_PT && type < GTT_TYPE_MAX)

#define gtt_type_is_pte_pt(type) \
	(type == GTT_TYPE_PPGTT_PTE_PT)

#define gtt_type_is_root_pointer(type) \
	(gtt_type_is_entry(type) && type > GTT_TYPE_PPGTT_ROOT_ENTRY)

#define gtt_init_entry(e, t, p, v) do { \
	(e)->type = t; \
	(e)->pdev = p; \
	memcpy(&(e)->val64, &v, sizeof(v)); \
} while (0)

/*
 * Mappings between GTT_TYPE* enumerations.
 * Following information can be found according to the given type:
 * - type of next level page table
 * - type of entry inside this level page table
 * - type of entry with PSE set
 *
 * If the given type doesn't have such a kind of information,
 * e.g. give a l4 root entry type, then request to get its PSE type,
 * give a PTE page table type, then request to get its next level page
 * table type, as we know l4 root entry doesn't have a PSE bit,
 * and a PTE page table doesn't have a next level page table type,
 * GTT_TYPE_INVALID will be returned. This is useful when traversing a
 * page table.
 */

struct gtt_type_table_entry {
	int entry_type;
165
	int pt_type;
166 167 168 169
	int next_pt_type;
	int pse_entry_type;
};

170
#define GTT_TYPE_TABLE_ENTRY(type, e_type, cpt_type, npt_type, pse_type) \
171 172
	[type] = { \
		.entry_type = e_type, \
173
		.pt_type = cpt_type, \
174 175 176 177 178 179 180
		.next_pt_type = npt_type, \
		.pse_entry_type = pse_type, \
	}

static struct gtt_type_table_entry gtt_type_table[] = {
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_ROOT_L4_ENTRY,
			GTT_TYPE_PPGTT_ROOT_L4_ENTRY,
181
			GTT_TYPE_INVALID,
182 183 184 185
			GTT_TYPE_PPGTT_PML4_PT,
			GTT_TYPE_INVALID),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PML4_PT,
			GTT_TYPE_PPGTT_PML4_ENTRY,
186
			GTT_TYPE_PPGTT_PML4_PT,
187 188 189 190
			GTT_TYPE_PPGTT_PDP_PT,
			GTT_TYPE_INVALID),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PML4_ENTRY,
			GTT_TYPE_PPGTT_PML4_ENTRY,
191
			GTT_TYPE_PPGTT_PML4_PT,
192 193 194 195
			GTT_TYPE_PPGTT_PDP_PT,
			GTT_TYPE_INVALID),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDP_PT,
			GTT_TYPE_PPGTT_PDP_ENTRY,
196
			GTT_TYPE_PPGTT_PDP_PT,
197 198 199 200
			GTT_TYPE_PPGTT_PDE_PT,
			GTT_TYPE_PPGTT_PTE_1G_ENTRY),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_ROOT_L3_ENTRY,
			GTT_TYPE_PPGTT_ROOT_L3_ENTRY,
201
			GTT_TYPE_INVALID,
202 203 204 205
			GTT_TYPE_PPGTT_PDE_PT,
			GTT_TYPE_PPGTT_PTE_1G_ENTRY),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDP_ENTRY,
			GTT_TYPE_PPGTT_PDP_ENTRY,
206
			GTT_TYPE_PPGTT_PDP_PT,
207 208 209 210
			GTT_TYPE_PPGTT_PDE_PT,
			GTT_TYPE_PPGTT_PTE_1G_ENTRY),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDE_PT,
			GTT_TYPE_PPGTT_PDE_ENTRY,
211
			GTT_TYPE_PPGTT_PDE_PT,
212 213 214 215
			GTT_TYPE_PPGTT_PTE_PT,
			GTT_TYPE_PPGTT_PTE_2M_ENTRY),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDE_ENTRY,
			GTT_TYPE_PPGTT_PDE_ENTRY,
216
			GTT_TYPE_PPGTT_PDE_PT,
217 218
			GTT_TYPE_PPGTT_PTE_PT,
			GTT_TYPE_PPGTT_PTE_2M_ENTRY),
219
	/* We take IPS bit as 'PSE' for PTE level. */
220 221
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_PT,
			GTT_TYPE_PPGTT_PTE_4K_ENTRY,
222
			GTT_TYPE_PPGTT_PTE_PT,
223
			GTT_TYPE_INVALID,
224
			GTT_TYPE_PPGTT_PTE_64K_ENTRY),
225 226
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_4K_ENTRY,
			GTT_TYPE_PPGTT_PTE_4K_ENTRY,
227
			GTT_TYPE_PPGTT_PTE_PT,
228
			GTT_TYPE_INVALID,
229 230 231 232 233 234
			GTT_TYPE_PPGTT_PTE_64K_ENTRY),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_64K_ENTRY,
			GTT_TYPE_PPGTT_PTE_4K_ENTRY,
			GTT_TYPE_PPGTT_PTE_PT,
			GTT_TYPE_INVALID,
			GTT_TYPE_PPGTT_PTE_64K_ENTRY),
235 236
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_2M_ENTRY,
			GTT_TYPE_PPGTT_PDE_ENTRY,
237
			GTT_TYPE_PPGTT_PDE_PT,
238 239 240 241
			GTT_TYPE_INVALID,
			GTT_TYPE_PPGTT_PTE_2M_ENTRY),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_1G_ENTRY,
			GTT_TYPE_PPGTT_PDP_ENTRY,
242
			GTT_TYPE_PPGTT_PDP_PT,
243 244 245 246 247
			GTT_TYPE_INVALID,
			GTT_TYPE_PPGTT_PTE_1G_ENTRY),
	GTT_TYPE_TABLE_ENTRY(GTT_TYPE_GGTT_PTE,
			GTT_TYPE_GGTT_PTE,
			GTT_TYPE_INVALID,
248
			GTT_TYPE_INVALID,
249 250 251 252 253 254 255 256
			GTT_TYPE_INVALID),
};

static inline int get_next_pt_type(int type)
{
	return gtt_type_table[type].next_pt_type;
}

257 258 259 260 261
static inline int get_pt_type(int type)
{
	return gtt_type_table[type].pt_type;
}

262 263 264 265 266 267 268 269 270 271 272 273
static inline int get_entry_type(int type)
{
	return gtt_type_table[type].entry_type;
}

static inline int get_pse_type(int type)
{
	return gtt_type_table[type].pse_entry_type;
}

static u64 read_pte64(struct drm_i915_private *dev_priv, unsigned long index)
{
274
	void __iomem *addr = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + index;
275 276

	return readq(addr);
277 278
}

279
static void ggtt_invalidate(struct drm_i915_private *dev_priv)
280 281 282 283 284 285
{
	mmio_hw_access_pre(dev_priv);
	I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
	mmio_hw_access_post(dev_priv);
}

286 287 288
static void write_pte64(struct drm_i915_private *dev_priv,
		unsigned long index, u64 pte)
{
289
	void __iomem *addr = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + index;
290 291 292 293

	writeq(pte, addr);
}

294
static inline int gtt_get_entry64(void *pt,
295 296 297 298 299 300 301 302
		struct intel_gvt_gtt_entry *e,
		unsigned long index, bool hypervisor_access, unsigned long gpa,
		struct intel_vgpu *vgpu)
{
	const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
	int ret;

	if (WARN_ON(info->gtt_entry_size != 8))
303
		return -EINVAL;
304 305 306 307 308

	if (hypervisor_access) {
		ret = intel_gvt_hypervisor_read_gpa(vgpu, gpa +
				(index << info->gtt_entry_size_shift),
				&e->val64, 8);
309 310
		if (WARN_ON(ret))
			return ret;
311 312 313 314 315
	} else if (!pt) {
		e->val64 = read_pte64(vgpu->gvt->dev_priv, index);
	} else {
		e->val64 = *((u64 *)pt + index);
	}
316
	return 0;
317 318
}

319
static inline int gtt_set_entry64(void *pt,
320 321 322 323 324 325 326 327
		struct intel_gvt_gtt_entry *e,
		unsigned long index, bool hypervisor_access, unsigned long gpa,
		struct intel_vgpu *vgpu)
{
	const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
	int ret;

	if (WARN_ON(info->gtt_entry_size != 8))
328
		return -EINVAL;
329 330 331 332 333

	if (hypervisor_access) {
		ret = intel_gvt_hypervisor_write_gpa(vgpu, gpa +
				(index << info->gtt_entry_size_shift),
				&e->val64, 8);
334 335
		if (WARN_ON(ret))
			return ret;
336 337 338 339 340
	} else if (!pt) {
		write_pte64(vgpu->gvt->dev_priv, index, e->val64);
	} else {
		*((u64 *)pt + index) = e->val64;
	}
341
	return 0;
342 343 344 345
}

#define GTT_HAW 46

346 347
#define ADDR_1G_MASK	GENMASK_ULL(GTT_HAW - 1, 30)
#define ADDR_2M_MASK	GENMASK_ULL(GTT_HAW - 1, 21)
348
#define ADDR_64K_MASK	GENMASK_ULL(GTT_HAW - 1, 16)
349
#define ADDR_4K_MASK	GENMASK_ULL(GTT_HAW - 1, 12)
350 351 352 353 354 355

static unsigned long gen8_gtt_get_pfn(struct intel_gvt_gtt_entry *e)
{
	unsigned long pfn;

	if (e->type == GTT_TYPE_PPGTT_PTE_1G_ENTRY)
356
		pfn = (e->val64 & ADDR_1G_MASK) >> PAGE_SHIFT;
357
	else if (e->type == GTT_TYPE_PPGTT_PTE_2M_ENTRY)
358
		pfn = (e->val64 & ADDR_2M_MASK) >> PAGE_SHIFT;
359 360
	else if (e->type == GTT_TYPE_PPGTT_PTE_64K_ENTRY)
		pfn = (e->val64 & ADDR_64K_MASK) >> PAGE_SHIFT;
361
	else
362
		pfn = (e->val64 & ADDR_4K_MASK) >> PAGE_SHIFT;
363 364 365 366 367 368 369
	return pfn;
}

static void gen8_gtt_set_pfn(struct intel_gvt_gtt_entry *e, unsigned long pfn)
{
	if (e->type == GTT_TYPE_PPGTT_PTE_1G_ENTRY) {
		e->val64 &= ~ADDR_1G_MASK;
370
		pfn &= (ADDR_1G_MASK >> PAGE_SHIFT);
371 372
	} else if (e->type == GTT_TYPE_PPGTT_PTE_2M_ENTRY) {
		e->val64 &= ~ADDR_2M_MASK;
373
		pfn &= (ADDR_2M_MASK >> PAGE_SHIFT);
374 375 376
	} else if (e->type == GTT_TYPE_PPGTT_PTE_64K_ENTRY) {
		e->val64 &= ~ADDR_64K_MASK;
		pfn &= (ADDR_64K_MASK >> PAGE_SHIFT);
377 378
	} else {
		e->val64 &= ~ADDR_4K_MASK;
379
		pfn &= (ADDR_4K_MASK >> PAGE_SHIFT);
380 381
	}

382
	e->val64 |= (pfn << PAGE_SHIFT);
383 384 385 386 387 388 389 390 391
}

static bool gen8_gtt_test_pse(struct intel_gvt_gtt_entry *e)
{
	/* Entry doesn't have PSE bit. */
	if (get_pse_type(e->type) == GTT_TYPE_INVALID)
		return false;

	e->type = get_entry_type(e->type);
392
	if (!(e->val64 & _PAGE_PSE))
393 394
		return false;

395 396 397 398
	/* We don't support 64K entry yet, will remove this later. */
	if (get_pse_type(e->type) == GTT_TYPE_PPGTT_PTE_64K_ENTRY)
		return false;

399 400 401 402
	e->type = get_pse_type(e->type);
	return true;
}

403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418
static bool gen8_gtt_test_ips(struct intel_gvt_gtt_entry *e)
{
	if (GEM_WARN_ON(e->type != GTT_TYPE_PPGTT_PDE_ENTRY))
		return false;

	return !!(e->val64 & GEN8_PDE_IPS_64K);
}

static void gen8_gtt_clear_ips(struct intel_gvt_gtt_entry *e)
{
	if (GEM_WARN_ON(e->type != GTT_TYPE_PPGTT_PDE_ENTRY))
		return;

	e->val64 &= ~GEN8_PDE_IPS_64K;
}

419 420 421 422 423 424 425 426 427 428 429
static bool gen8_gtt_test_present(struct intel_gvt_gtt_entry *e)
{
	/*
	 * i915 writes PDP root pointer registers without present bit,
	 * it also works, so we need to treat root pointer entry
	 * specifically.
	 */
	if (e->type == GTT_TYPE_PPGTT_ROOT_L3_ENTRY
			|| e->type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY)
		return (e->val64 != 0);
	else
430
		return (e->val64 & _PAGE_PRESENT);
431 432 433 434
}

static void gtt_entry_clear_present(struct intel_gvt_gtt_entry *e)
{
435
	e->val64 &= ~_PAGE_PRESENT;
436 437
}

438 439
static void gtt_entry_set_present(struct intel_gvt_gtt_entry *e)
{
440
	e->val64 |= _PAGE_PRESENT;
441 442 443 444 445 446 447
}

/*
 * Per-platform GMA routines.
 */
static unsigned long gma_to_ggtt_pte_index(unsigned long gma)
{
448
	unsigned long x = (gma >> I915_GTT_PAGE_SHIFT);
449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471

	trace_gma_index(__func__, gma, x);
	return x;
}

#define DEFINE_PPGTT_GMA_TO_INDEX(prefix, ename, exp) \
static unsigned long prefix##_gma_to_##ename##_index(unsigned long gma) \
{ \
	unsigned long x = (exp); \
	trace_gma_index(__func__, gma, x); \
	return x; \
}

DEFINE_PPGTT_GMA_TO_INDEX(gen8, pte, (gma >> 12 & 0x1ff));
DEFINE_PPGTT_GMA_TO_INDEX(gen8, pde, (gma >> 21 & 0x1ff));
DEFINE_PPGTT_GMA_TO_INDEX(gen8, l3_pdp, (gma >> 30 & 0x3));
DEFINE_PPGTT_GMA_TO_INDEX(gen8, l4_pdp, (gma >> 30 & 0x1ff));
DEFINE_PPGTT_GMA_TO_INDEX(gen8, pml4, (gma >> 39 & 0x1ff));

static struct intel_gvt_gtt_pte_ops gen8_gtt_pte_ops = {
	.get_entry = gtt_get_entry64,
	.set_entry = gtt_set_entry64,
	.clear_present = gtt_entry_clear_present,
472
	.set_present = gtt_entry_set_present,
473 474
	.test_present = gen8_gtt_test_present,
	.test_pse = gen8_gtt_test_pse,
475 476
	.clear_ips = gen8_gtt_clear_ips,
	.test_ips = gen8_gtt_test_ips,
477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492
	.get_pfn = gen8_gtt_get_pfn,
	.set_pfn = gen8_gtt_set_pfn,
};

static struct intel_gvt_gtt_gma_ops gen8_gtt_gma_ops = {
	.gma_to_ggtt_pte_index = gma_to_ggtt_pte_index,
	.gma_to_pte_index = gen8_gma_to_pte_index,
	.gma_to_pde_index = gen8_gma_to_pde_index,
	.gma_to_l3_pdp_index = gen8_gma_to_l3_pdp_index,
	.gma_to_l4_pdp_index = gen8_gma_to_l4_pdp_index,
	.gma_to_pml4_index = gen8_gma_to_pml4_index,
};

/*
 * MM helpers.
 */
493 494 495
static void _ppgtt_get_root_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index,
		bool guest)
496
{
497
	struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
498

499
	GEM_BUG_ON(mm->type != INTEL_GVT_MM_PPGTT);
500

501 502 503 504
	entry->type = mm->ppgtt_mm.root_entry_type;
	pte_ops->get_entry(guest ? mm->ppgtt_mm.guest_pdps :
			   mm->ppgtt_mm.shadow_pdps,
			   entry, index, false, 0, mm->vgpu);
505

506
	pte_ops->test_pse(entry);
507 508
}

509 510
static inline void ppgtt_get_guest_root_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index)
511
{
512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566
	_ppgtt_get_root_entry(mm, entry, index, true);
}

static inline void ppgtt_get_shadow_root_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index)
{
	_ppgtt_get_root_entry(mm, entry, index, false);
}

static void _ppgtt_set_root_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index,
		bool guest)
{
	struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;

	pte_ops->set_entry(guest ? mm->ppgtt_mm.guest_pdps :
			   mm->ppgtt_mm.shadow_pdps,
			   entry, index, false, 0, mm->vgpu);
}

static inline void ppgtt_set_guest_root_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index)
{
	_ppgtt_set_root_entry(mm, entry, index, true);
}

static inline void ppgtt_set_shadow_root_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index)
{
	_ppgtt_set_root_entry(mm, entry, index, false);
}

static void ggtt_get_guest_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index)
{
	struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;

	GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);

	entry->type = GTT_TYPE_GGTT_PTE;
	pte_ops->get_entry(mm->ggtt_mm.virtual_ggtt, entry, index,
			   false, 0, mm->vgpu);
}

static void ggtt_set_guest_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index)
{
	struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;

	GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);

	pte_ops->set_entry(mm->ggtt_mm.virtual_ggtt, entry, index,
			   false, 0, mm->vgpu);
}

567 568 569 570 571 572 573 574 575 576
static void ggtt_get_host_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index)
{
	struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;

	GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);

	pte_ops->get_entry(NULL, entry, index, false, 0, mm->vgpu);
}

577 578 579 580 581 582
static void ggtt_set_host_entry(struct intel_vgpu_mm *mm,
		struct intel_gvt_gtt_entry *entry, unsigned long index)
{
	struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;

	GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);
583

584
	pte_ops->set_entry(NULL, entry, index, false, 0, mm->vgpu);
585 586 587 588 589
}

/*
 * PPGTT shadow page table helpers.
 */
590
static inline int ppgtt_spt_get_entry(
591 592 593 594 595 596 597
		struct intel_vgpu_ppgtt_spt *spt,
		void *page_table, int type,
		struct intel_gvt_gtt_entry *e, unsigned long index,
		bool guest)
{
	struct intel_gvt *gvt = spt->vgpu->gvt;
	struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
598
	int ret;
599 600 601 602

	e->type = get_entry_type(type);

	if (WARN(!gtt_type_is_entry(e->type), "invalid entry type\n"))
603
		return -EINVAL;
604

605
	ret = ops->get_entry(page_table, e, index, guest,
606
			spt->guest_page.gfn << I915_GTT_PAGE_SHIFT,
607
			spt->vgpu);
608 609 610
	if (ret)
		return ret;

611
	ops->test_pse(e);
612 613 614

	gvt_vdbg_mm("read ppgtt entry, spt type %d, entry type %d, index %lu, value %llx\n",
		    type, e->type, index, e->val64);
615
	return 0;
616 617
}

618
static inline int ppgtt_spt_set_entry(
619 620 621 622 623 624 625 626 627
		struct intel_vgpu_ppgtt_spt *spt,
		void *page_table, int type,
		struct intel_gvt_gtt_entry *e, unsigned long index,
		bool guest)
{
	struct intel_gvt *gvt = spt->vgpu->gvt;
	struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;

	if (WARN(!gtt_type_is_entry(e->type), "invalid entry type\n"))
628
		return -EINVAL;
629

630 631 632
	gvt_vdbg_mm("set ppgtt entry, spt type %d, entry type %d, index %lu, value %llx\n",
		    type, e->type, index, e->val64);

633
	return ops->set_entry(page_table, e, index, guest,
634
			spt->guest_page.gfn << I915_GTT_PAGE_SHIFT,
635 636 637 638 639
			spt->vgpu);
}

#define ppgtt_get_guest_entry(spt, e, index) \
	ppgtt_spt_get_entry(spt, NULL, \
640
		spt->guest_page.type, e, index, true)
641 642 643

#define ppgtt_set_guest_entry(spt, e, index) \
	ppgtt_spt_set_entry(spt, NULL, \
644
		spt->guest_page.type, e, index, true)
645 646 647 648 649 650 651 652 653

#define ppgtt_get_shadow_entry(spt, e, index) \
	ppgtt_spt_get_entry(spt, spt->shadow_page.vaddr, \
		spt->shadow_page.type, e, index, false)

#define ppgtt_set_shadow_entry(spt, e, index) \
	ppgtt_spt_set_entry(spt, spt->shadow_page.vaddr, \
		spt->shadow_page.type, e, index, false)

654
static void *alloc_spt(gfp_t gfp_mask)
655
{
656
	struct intel_vgpu_ppgtt_spt *spt;
657

658 659 660
	spt = kzalloc(sizeof(*spt), gfp_mask);
	if (!spt)
		return NULL;
661

662 663 664 665 666 667
	spt->shadow_page.page = alloc_page(gfp_mask);
	if (!spt->shadow_page.page) {
		kfree(spt);
		return NULL;
	}
	return spt;
668 669
}

670
static void free_spt(struct intel_vgpu_ppgtt_spt *spt)
671
{
672 673
	__free_page(spt->shadow_page.page);
	kfree(spt);
674 675
}

676 677 678
static int detach_oos_page(struct intel_vgpu *vgpu,
		struct intel_vgpu_oos_page *oos_page);

679
static void ppgtt_free_spt(struct intel_vgpu_ppgtt_spt *spt)
680
{
681
	struct device *kdev = &spt->vgpu->gvt->dev_priv->drm.pdev->dev;
682

683
	trace_spt_free(spt->vgpu->id, spt, spt->guest_page.type);
684

685 686
	dma_unmap_page(kdev, spt->shadow_page.mfn << I915_GTT_PAGE_SHIFT, 4096,
		       PCI_DMA_BIDIRECTIONAL);
687 688

	radix_tree_delete(&spt->vgpu->gtt.spt_tree, spt->shadow_page.mfn);
689

690 691
	if (spt->guest_page.oos_page)
		detach_oos_page(spt->vgpu, spt->guest_page.oos_page);
692

693
	intel_vgpu_unregister_page_track(spt->vgpu, spt->guest_page.gfn);
694 695 696 697 698

	list_del_init(&spt->post_shadow_list);
	free_spt(spt);
}

699
static void ppgtt_free_all_spt(struct intel_vgpu *vgpu)
700
{
701
	struct intel_vgpu_ppgtt_spt *spt;
702 703
	struct radix_tree_iter iter;
	void **slot;
704

705 706
	radix_tree_for_each_slot(slot, &vgpu->gtt.spt_tree, &iter, 0) {
		spt = radix_tree_deref_slot(slot);
707
		ppgtt_free_spt(spt);
708
	}
709 710
}

711
static int ppgtt_handle_guest_write_page_table_bytes(
712
		struct intel_vgpu_ppgtt_spt *spt,
713 714
		u64 pa, void *p_data, int bytes);

715 716 717
static int ppgtt_write_protection_handler(
		struct intel_vgpu_page_track *page_track,
		u64 gpa, void *data, int bytes)
718
{
719 720
	struct intel_vgpu_ppgtt_spt *spt = page_track->priv_data;

721 722 723 724 725
	int ret;

	if (bytes != 4 && bytes != 8)
		return -EINVAL;

726
	ret = ppgtt_handle_guest_write_page_table_bytes(spt, gpa, data, bytes);
727 728 729 730 731
	if (ret)
		return ret;
	return ret;
}

732 733 734 735 736 737
/* Find a spt by guest gfn. */
static struct intel_vgpu_ppgtt_spt *intel_vgpu_find_spt_by_gfn(
		struct intel_vgpu *vgpu, unsigned long gfn)
{
	struct intel_vgpu_page_track *track;

738 739 740
	track = intel_vgpu_find_page_track(vgpu, gfn);
	if (track && track->handler == ppgtt_write_protection_handler)
		return track->priv_data;
741 742 743 744 745

	return NULL;
}

/* Find the spt by shadow page mfn. */
746
static inline struct intel_vgpu_ppgtt_spt *intel_vgpu_find_spt_by_mfn(
747 748
		struct intel_vgpu *vgpu, unsigned long mfn)
{
749
	return radix_tree_lookup(&vgpu->gtt.spt_tree, mfn);
750 751
}

752
static int reclaim_one_ppgtt_mm(struct intel_gvt *gvt);
753

754
static struct intel_vgpu_ppgtt_spt *ppgtt_alloc_spt(
755 756
		struct intel_vgpu *vgpu, int type, unsigned long gfn)
{
757
	struct device *kdev = &vgpu->gvt->dev_priv->drm.pdev->dev;
758
	struct intel_vgpu_ppgtt_spt *spt = NULL;
759
	dma_addr_t daddr;
760
	int ret;
761 762 763 764

retry:
	spt = alloc_spt(GFP_KERNEL | __GFP_ZERO);
	if (!spt) {
765
		if (reclaim_one_ppgtt_mm(vgpu->gvt))
766 767
			goto retry;

768
		gvt_vgpu_err("fail to allocate ppgtt shadow page\n");
769 770 771 772 773 774 775 776
		return ERR_PTR(-ENOMEM);
	}

	spt->vgpu = vgpu;
	atomic_set(&spt->refcount, 1);
	INIT_LIST_HEAD(&spt->post_shadow_list);

	/*
777
	 * Init shadow_page.
778
	 */
779 780 781 782 783
	spt->shadow_page.type = type;
	daddr = dma_map_page(kdev, spt->shadow_page.page,
			     0, 4096, PCI_DMA_BIDIRECTIONAL);
	if (dma_mapping_error(kdev, daddr)) {
		gvt_vgpu_err("fail to map dma addr\n");
784 785
		ret = -EINVAL;
		goto err_free_spt;
786
	}
787 788
	spt->shadow_page.vaddr = page_address(spt->shadow_page.page);
	spt->shadow_page.mfn = daddr >> I915_GTT_PAGE_SHIFT;
789

790 791 792 793 794
	/*
	 * Init guest_page.
	 */
	spt->guest_page.type = type;
	spt->guest_page.gfn = gfn;
795

796 797
	ret = intel_vgpu_register_page_track(vgpu, spt->guest_page.gfn,
					ppgtt_write_protection_handler, spt);
798 799
	if (ret)
		goto err_unmap_dma;
800

801 802 803
	ret = radix_tree_insert(&vgpu->gtt.spt_tree, spt->shadow_page.mfn, spt);
	if (ret)
		goto err_unreg_page_track;
804

805 806
	trace_spt_alloc(vgpu->id, spt, type, spt->shadow_page.mfn, gfn);
	return spt;
807 808 809 810 811 812 813 814

err_unreg_page_track:
	intel_vgpu_unregister_page_track(vgpu, spt->guest_page.gfn);
err_unmap_dma:
	dma_unmap_page(kdev, daddr, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
err_free_spt:
	free_spt(spt);
	return ERR_PTR(ret);
815 816 817 818 819 820
}

#define pt_entry_size_shift(spt) \
	((spt)->vgpu->gvt->device_info.gtt_entry_size_shift)

#define pt_entries(spt) \
821
	(I915_GTT_PAGE_SIZE >> pt_entry_size_shift(spt))
822 823 824

#define for_each_present_guest_entry(spt, e, i) \
	for (i = 0; i < pt_entries(spt); i++) \
825 826
		if (!ppgtt_get_guest_entry(spt, e, i) && \
		    spt->vgpu->gvt->gtt.pte_ops->test_present(e))
827 828 829

#define for_each_present_shadow_entry(spt, e, i) \
	for (i = 0; i < pt_entries(spt); i++) \
830 831
		if (!ppgtt_get_shadow_entry(spt, e, i) && \
		    spt->vgpu->gvt->gtt.pte_ops->test_present(e))
832

833
static void ppgtt_get_spt(struct intel_vgpu_ppgtt_spt *spt)
834 835 836 837 838 839 840 841
{
	int v = atomic_read(&spt->refcount);

	trace_spt_refcount(spt->vgpu->id, "inc", spt, v, (v + 1));

	atomic_inc(&spt->refcount);
}

842
static int ppgtt_invalidate_spt(struct intel_vgpu_ppgtt_spt *spt);
843

844
static int ppgtt_invalidate_spt_by_shadow_entry(struct intel_vgpu *vgpu,
845 846 847 848
		struct intel_gvt_gtt_entry *e)
{
	struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
	struct intel_vgpu_ppgtt_spt *s;
849
	intel_gvt_gtt_type_t cur_pt_type;
850

851
	GEM_BUG_ON(!gtt_type_is_pt(get_next_pt_type(e->type)));
852

853 854 855 856 857 858 859
	if (e->type != GTT_TYPE_PPGTT_ROOT_L3_ENTRY
		&& e->type != GTT_TYPE_PPGTT_ROOT_L4_ENTRY) {
		cur_pt_type = get_next_pt_type(e->type) + 1;
		if (ops->get_pfn(e) ==
			vgpu->gtt.scratch_pt[cur_pt_type].page_mfn)
			return 0;
	}
860
	s = intel_vgpu_find_spt_by_mfn(vgpu, ops->get_pfn(e));
861
	if (!s) {
862 863
		gvt_vgpu_err("fail to find shadow page: mfn: 0x%lx\n",
				ops->get_pfn(e));
864 865
		return -ENXIO;
	}
866
	return ppgtt_invalidate_spt(s);
867 868
}

869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885
static inline void ppgtt_invalidate_pte(struct intel_vgpu_ppgtt_spt *spt,
		struct intel_gvt_gtt_entry *entry)
{
	struct intel_vgpu *vgpu = spt->vgpu;
	struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
	unsigned long pfn;
	int type;

	pfn = ops->get_pfn(entry);
	type = spt->shadow_page.type;

	if (pfn == vgpu->gtt.scratch_pt[type].page_mfn)
		return;

	intel_gvt_hypervisor_dma_unmap_guest_page(vgpu, pfn << PAGE_SHIFT);
}

886
static int ppgtt_invalidate_spt(struct intel_vgpu_ppgtt_spt *spt)
887
{
888
	struct intel_vgpu *vgpu = spt->vgpu;
889 890 891 892 893 894
	struct intel_gvt_gtt_entry e;
	unsigned long index;
	int ret;
	int v = atomic_read(&spt->refcount);

	trace_spt_change(spt->vgpu->id, "die", spt,
895
			spt->guest_page.gfn, spt->shadow_page.type);
896 897 898 899 900 901 902

	trace_spt_refcount(spt->vgpu->id, "dec", spt, v, (v - 1));

	if (atomic_dec_return(&spt->refcount) > 0)
		return 0;

	for_each_present_shadow_entry(spt, &e, index) {
903 904 905
		switch (e.type) {
		case GTT_TYPE_PPGTT_PTE_4K_ENTRY:
			gvt_vdbg_mm("invalidate 4K entry\n");
906 907
			ppgtt_invalidate_pte(spt, &e);
			break;
908
		case GTT_TYPE_PPGTT_PTE_64K_ENTRY:
909 910
		case GTT_TYPE_PPGTT_PTE_2M_ENTRY:
		case GTT_TYPE_PPGTT_PTE_1G_ENTRY:
911
			WARN(1, "GVT doesn't support 64K/2M/1GB page\n");
912 913 914 915 916
			continue;
		case GTT_TYPE_PPGTT_PML4_ENTRY:
		case GTT_TYPE_PPGTT_PDP_ENTRY:
		case GTT_TYPE_PPGTT_PDE_ENTRY:
			gvt_vdbg_mm("invalidate PMUL4/PDP/PDE entry\n");
917
			ret = ppgtt_invalidate_spt_by_shadow_entry(
918 919 920 921 922 923
					spt->vgpu, &e);
			if (ret)
				goto fail;
			break;
		default:
			GEM_BUG_ON(1);
924 925
		}
	}
926

927
	trace_spt_change(spt->vgpu->id, "release", spt,
928
			 spt->guest_page.gfn, spt->shadow_page.type);
929
	ppgtt_free_spt(spt);
930 931
	return 0;
fail:
932 933
	gvt_vgpu_err("fail: shadow page %p shadow entry 0x%llx type %d\n",
			spt, e.val64, e.type);
934 935 936
	return ret;
}

937
static int ppgtt_populate_spt(struct intel_vgpu_ppgtt_spt *spt);
938

939
static struct intel_vgpu_ppgtt_spt *ppgtt_populate_spt_by_guest_entry(
940 941 942
		struct intel_vgpu *vgpu, struct intel_gvt_gtt_entry *we)
{
	struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
943
	struct intel_vgpu_ppgtt_spt *spt = NULL;
944 945
	int ret;

946
	GEM_BUG_ON(!gtt_type_is_pt(get_next_pt_type(we->type)));
947

948 949
	spt = intel_vgpu_find_spt_by_gfn(vgpu, ops->get_pfn(we));
	if (spt)
950
		ppgtt_get_spt(spt);
951
	else {
952 953
		int type = get_next_pt_type(we->type);

954
		spt = ppgtt_alloc_spt(vgpu, type, ops->get_pfn(we));
955 956
		if (IS_ERR(spt)) {
			ret = PTR_ERR(spt);
957 958 959
			goto fail;
		}

960
		ret = intel_vgpu_enable_page_track(vgpu, spt->guest_page.gfn);
961 962 963
		if (ret)
			goto fail;

964
		ret = ppgtt_populate_spt(spt);
965 966 967
		if (ret)
			goto fail;

968 969
		trace_spt_change(vgpu->id, "new", spt, spt->guest_page.gfn,
				 spt->shadow_page.type);
970
	}
971
	return spt;
972
fail:
973
	gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n",
974
		     spt, we->val64, we->type);
975 976 977 978 979 980 981 982 983 984 985 986 987 988
	return ERR_PTR(ret);
}

static inline void ppgtt_generate_shadow_entry(struct intel_gvt_gtt_entry *se,
		struct intel_vgpu_ppgtt_spt *s, struct intel_gvt_gtt_entry *ge)
{
	struct intel_gvt_gtt_pte_ops *ops = s->vgpu->gvt->gtt.pte_ops;

	se->type = ge->type;
	se->val64 = ge->val64;

	ops->set_pfn(se, s->shadow_page.mfn);
}

989 990 991 992 993 994
static int ppgtt_populate_shadow_entry(struct intel_vgpu *vgpu,
	struct intel_vgpu_ppgtt_spt *spt, unsigned long index,
	struct intel_gvt_gtt_entry *ge)
{
	struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
	struct intel_gvt_gtt_entry se = *ge;
995 996 997
	unsigned long gfn;
	dma_addr_t dma_addr;
	int ret;
998 999 1000 1001 1002 1003 1004 1005 1006 1007

	if (!pte_ops->test_present(ge))
		return 0;

	gfn = pte_ops->get_pfn(ge);

	switch (ge->type) {
	case GTT_TYPE_PPGTT_PTE_4K_ENTRY:
		gvt_vdbg_mm("shadow 4K gtt entry\n");
		break;
1008
	case GTT_TYPE_PPGTT_PTE_64K_ENTRY:
1009 1010
	case GTT_TYPE_PPGTT_PTE_2M_ENTRY:
	case GTT_TYPE_PPGTT_PTE_1G_ENTRY:
1011
		gvt_vgpu_err("GVT doesn't support 64K/2M/1GB entry\n");
1012 1013 1014 1015 1016 1017
		return -EINVAL;
	default:
		GEM_BUG_ON(1);
	};

	/* direct shadow */
1018 1019
	ret = intel_gvt_hypervisor_dma_map_guest_page(vgpu, gfn, &dma_addr);
	if (ret)
1020 1021
		return -ENXIO;

1022
	pte_ops->set_pfn(&se, dma_addr >> PAGE_SHIFT);
1023 1024 1025 1026
	ppgtt_set_shadow_entry(spt, &se, index);
	return 0;
}

1027
static int ppgtt_populate_spt(struct intel_vgpu_ppgtt_spt *spt)
1028 1029
{
	struct intel_vgpu *vgpu = spt->vgpu;
1030 1031
	struct intel_gvt *gvt = vgpu->gvt;
	struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
1032 1033
	struct intel_vgpu_ppgtt_spt *s;
	struct intel_gvt_gtt_entry se, ge;
1034
	unsigned long gfn, i;
1035 1036 1037
	int ret;

	trace_spt_change(spt->vgpu->id, "born", spt,
1038
			 spt->guest_page.gfn, spt->shadow_page.type);
1039

1040 1041
	for_each_present_guest_entry(spt, &ge, i) {
		if (gtt_type_is_pt(get_next_pt_type(ge.type))) {
1042
			s = ppgtt_populate_spt_by_guest_entry(vgpu, &ge);
1043 1044 1045 1046 1047 1048 1049 1050
			if (IS_ERR(s)) {
				ret = PTR_ERR(s);
				goto fail;
			}
			ppgtt_get_shadow_entry(spt, &se, i);
			ppgtt_generate_shadow_entry(&se, s, &ge);
			ppgtt_set_shadow_entry(spt, &se, i);
		} else {
1051
			gfn = ops->get_pfn(&ge);
1052
			if (!intel_gvt_hypervisor_is_valid_gfn(vgpu, gfn)) {
1053
				ops->set_pfn(&se, gvt->gtt.scratch_mfn);
1054 1055 1056
				ppgtt_set_shadow_entry(spt, &se, i);
				continue;
			}
1057

1058 1059 1060
			ret = ppgtt_populate_shadow_entry(vgpu, spt, i, &ge);
			if (ret)
				goto fail;
1061 1062 1063 1064
		}
	}
	return 0;
fail:
1065 1066
	gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n",
			spt, ge.val64, ge.type);
1067 1068 1069
	return ret;
}

1070
static int ppgtt_handle_guest_entry_removal(struct intel_vgpu_ppgtt_spt *spt,
1071
		struct intel_gvt_gtt_entry *se, unsigned long index)
1072 1073 1074 1075 1076
{
	struct intel_vgpu *vgpu = spt->vgpu;
	struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
	int ret;

1077 1078
	trace_spt_guest_change(spt->vgpu->id, "remove", spt,
			       spt->shadow_page.type, se->val64, index);
1079

1080 1081 1082
	gvt_vdbg_mm("destroy old shadow entry, type %d, index %lu, value %llx