rcar_du_group.c 7.52 KB
Newer Older
1 2 3
/*
 * rcar_du_group.c  --  R-Car Display Unit Channels Pair
 *
4
 * Copyright (C) 2013-2015 Renesas Electronics Corporation
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
 *
 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

/*
 * The R8A7779 DU is split in per-CRTC resources (scan-out engine, blending
 * unit, timings generator, ...) and device-global resources (start/stop
 * control, planes, ...) shared between the two CRTCs.
 *
 * The R8A7790 introduced a third CRTC with its own set of global resources.
 * This would be modeled as two separate DU device instances if it wasn't for
 * a handful or resources that are shared between the three CRTCs (mostly
 * related to input and output routing). For this reason the R8A7790 DU must be
 * modeled as a single device with three CRTCs, two sets of "semi-global"
 * resources, and a few device-global resources.
 *
 * The rcar_du_group object is a driver specific object, without any real
 * counterpart in the DU documentation, that models those semi-global resources.
 */

30
#include <linux/clk.h>
31 32 33 34 35 36
#include <linux/io.h>

#include "rcar_du_drv.h"
#include "rcar_du_group.h"
#include "rcar_du_regs.h"

37
u32 rcar_du_group_read(struct rcar_du_group *rgrp, u32 reg)
38 39 40 41
{
	return rcar_du_read(rgrp->dev, rgrp->mmio_offset + reg);
}

42
void rcar_du_group_write(struct rcar_du_group *rgrp, u32 reg, u32 data)
43 44 45 46
{
	rcar_du_write(rgrp->dev, rgrp->mmio_offset + reg, data);
}

47 48 49 50 51 52 53 54 55 56
static void rcar_du_group_setup_pins(struct rcar_du_group *rgrp)
{
	u32 defr6 = DEFR6_CODE | DEFR6_ODPM12_DISP;

	if (rgrp->num_crtcs > 1)
		defr6 |= DEFR6_ODPM22_DISP;

	rcar_du_group_write(rgrp, DEFR6, defr6);
}

57 58
static void rcar_du_group_setup_defr8(struct rcar_du_group *rgrp)
{
59 60 61 62
	struct rcar_du_device *rcdu = rgrp->dev;
	unsigned int possible_crtcs =
		rcdu->info->routes[RCAR_DU_OUTPUT_DPAD0].possible_crtcs;
	u32 defr8 = DEFR8_CODE;
63

64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
	if (rcdu->info->gen < 3) {
		defr8 |= DEFR8_DEFE8;

		/* On Gen2 the DEFR8 register for the first group also controls
		 * RGB output routing to DPAD0 and VSPD1 routing to DU0/1/2 for
		 * DU instances that support it.
		 */
		if (rgrp->index == 0) {
			if (possible_crtcs > 1)
				defr8 |= DEFR8_DRGBS_DU(rcdu->dpad0_source);
			if (rgrp->dev->vspd1_sink == 2)
				defr8 |= DEFR8_VSCS;
		}
	} else {
		/* On Gen3 VSPD routing can't be configured, but DPAD routing
		 * needs to be set despite having a single option available.
		 */
		u32 crtc = ffs(possible_crtcs) - 1;

		if (crtc / 2 == rgrp->index)
			defr8 |= DEFR8_DRGBS_DU(crtc);
85
	}
86 87 88 89

	rcar_du_group_write(rgrp, DEFR8, defr8);
}

90 91
static void rcar_du_group_setup(struct rcar_du_group *rgrp)
{
92 93
	struct rcar_du_device *rcdu = rgrp->dev;

94 95
	/* Enable extended features */
	rcar_du_group_write(rgrp, DEFR, DEFR_CODE | DEFR_DEFE);
96 97 98 99 100
	if (rcdu->info->gen < 3) {
		rcar_du_group_write(rgrp, DEFR2, DEFR2_CODE | DEFR2_DEFE2G);
		rcar_du_group_write(rgrp, DEFR3, DEFR3_CODE | DEFR3_DEFE3);
		rcar_du_group_write(rgrp, DEFR4, DEFR4_CODE);
	}
101
	rcar_du_group_write(rgrp, DEFR5, DEFR5_CODE | DEFR5_DEFE5);
102

103 104
	rcar_du_group_setup_pins(rgrp);

105
	if (rcar_du_has(rgrp->dev, RCAR_DU_FEATURE_EXT_CTRL_REGS)) {
106
		rcar_du_group_setup_defr8(rgrp);
107

108 109 110 111 112 113 114 115 116 117
		/*
		 * Configure input dot clock routing. We currently hardcode the
		 * configuration to routing DOTCLKINn to DUn. Register fields
		 * depend on the DU generation, but the resulting value is 0 in
		 * all cases.
		 *
		 * On Gen2 a single register in the first group controls dot
		 * clock selection for all channels, while on Gen3 dot clocks
		 * are setup through per-group registers, only available when
		 * the group has two channels.
118
		 */
119 120 121
		if ((rcdu->info->gen < 3 && rgrp->index == 0) ||
		    (rcdu->info->gen == 3 &&  rgrp->num_crtcs > 1))
			rcar_du_group_write(rgrp, DIDSR, DIDSR_CODE);
122 123
	}

124 125 126
	if (rcdu->info->gen >= 3)
		rcar_du_group_write(rgrp, DEFR10, DEFR10_CODE | DEFR10_DEFE10);

127 128 129 130
	/* Use DS1PR and DS2PR to configure planes priorities and connects the
	 * superposition 0 to DU0 pins. DU1 pins will be configured dynamically.
	 */
	rcar_du_group_write(rgrp, DORCR, DORCR_PG1D_DS1 | DORCR_DPRS);
131 132 133 134 135 136

	/* Apply planes to CRTCs association. */
	mutex_lock(&rgrp->lock);
	rcar_du_group_write(rgrp, DPTSR, (rgrp->dptsr_planes << 16) |
			    rgrp->dptsr_planes);
	mutex_unlock(&rgrp->lock);
137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202
}

/*
 * rcar_du_group_get - Acquire a reference to the DU channels group
 *
 * Acquiring the first reference setups core registers. A reference must be held
 * before accessing any hardware registers.
 *
 * This function must be called with the DRM mode_config lock held.
 *
 * Return 0 in case of success or a negative error code otherwise.
 */
int rcar_du_group_get(struct rcar_du_group *rgrp)
{
	if (rgrp->use_count)
		goto done;

	rcar_du_group_setup(rgrp);

done:
	rgrp->use_count++;
	return 0;
}

/*
 * rcar_du_group_put - Release a reference to the DU
 *
 * This function must be called with the DRM mode_config lock held.
 */
void rcar_du_group_put(struct rcar_du_group *rgrp)
{
	--rgrp->use_count;
}

static void __rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start)
{
	rcar_du_group_write(rgrp, DSYSR,
		(rcar_du_group_read(rgrp, DSYSR) & ~(DSYSR_DRES | DSYSR_DEN)) |
		(start ? DSYSR_DEN : DSYSR_DRES));
}

void rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start)
{
	/* Many of the configuration bits are only updated when the display
	 * reset (DRES) bit in DSYSR is set to 1, disabling *both* CRTCs. Some
	 * of those bits could be pre-configured, but others (especially the
	 * bits related to plane assignment to display timing controllers) need
	 * to be modified at runtime.
	 *
	 * Restart the display controller if a start is requested. Sorry for the
	 * flicker. It should be possible to move most of the "DRES-update" bits
	 * setup to driver initialization time and minimize the number of cases
	 * when the display controller will have to be restarted.
	 */
	if (start) {
		if (rgrp->used_crtcs++ != 0)
			__rcar_du_group_start_stop(rgrp, false);
		__rcar_du_group_start_stop(rgrp, true);
	} else {
		if (--rgrp->used_crtcs == 0)
			__rcar_du_group_start_stop(rgrp, false);
	}
}

void rcar_du_group_restart(struct rcar_du_group *rgrp)
{
203 204
	rgrp->need_restart = false;

205 206 207
	__rcar_du_group_start_stop(rgrp, false);
	__rcar_du_group_start_stop(rgrp, true);
}
208

209
int rcar_du_set_dpad0_vsp1_routing(struct rcar_du_device *rcdu)
210 211 212
{
	int ret;

213 214 215
	if (!rcar_du_has(rcdu, RCAR_DU_FEATURE_EXT_CTRL_REGS))
		return 0;

216 217 218 219
	/* RGB output routing to DPAD0 and VSP1D routing to DU0/1/2 are
	 * configured in the DEFR8 register of the first group. As this function
	 * can be called with the DU0 and DU1 CRTCs disabled, we need to enable
	 * the first group clock before accessing the register.
220 221 222 223 224 225 226 227 228 229 230 231 232
	 */
	ret = clk_prepare_enable(rcdu->crtcs[0].clock);
	if (ret < 0)
		return ret;

	rcar_du_group_setup_defr8(&rcdu->groups[0]);

	clk_disable_unprepare(rcdu->crtcs[0].clock);

	return 0;
}

int rcar_du_group_set_routing(struct rcar_du_group *rgrp)
233 234 235 236 237 238
{
	struct rcar_du_crtc *crtc0 = &rgrp->dev->crtcs[rgrp->index * 2];
	u32 dorcr = rcar_du_group_read(rgrp, DORCR);

	dorcr &= ~(DORCR_PG2T | DORCR_DK2S | DORCR_PG2D_MASK);

239 240 241
	/* Set the DPAD1 pins sources. Select CRTC 0 if explicitly requested and
	 * CRTC 1 in all other cases to avoid cloning CRTC 0 to DPAD0 and DPAD1
	 * by default.
242
	 */
243
	if (crtc0->outputs & BIT(RCAR_DU_OUTPUT_DPAD1))
244 245 246 247 248
		dorcr |= DORCR_PG2D_DS1;
	else
		dorcr |= DORCR_PG2T | DORCR_DK2S | DORCR_PG2D_DS2;

	rcar_du_group_write(rgrp, DORCR, dorcr);
249

250
	return rcar_du_set_dpad0_vsp1_routing(rgrp->dev);
251
}