rcar_du_crtc.c 27 KB
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/*
 * rcar_du_crtc.c  --  R-Car Display Unit CRTCs
 *
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 * Copyright (C) 2013-2015 Renesas Electronics Corporation
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 *
 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/clk.h>
#include <linux/mutex.h>
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#include <linux/sys_soc.h>
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#include <drm/drmP.h>
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#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
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#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_fb_cma_helper.h>
#include <drm/drm_gem_cma_helper.h>
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#include <drm/drm_plane_helper.h>
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#include "rcar_du_crtc.h"
#include "rcar_du_drv.h"
#include "rcar_du_kms.h"
#include "rcar_du_plane.h"
#include "rcar_du_regs.h"
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#include "rcar_du_vsp.h"
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static u32 rcar_du_crtc_read(struct rcar_du_crtc *rcrtc, u32 reg)
{
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	struct rcar_du_device *rcdu = rcrtc->group->dev;
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	return rcar_du_read(rcdu, rcrtc->mmio_offset + reg);
}

static void rcar_du_crtc_write(struct rcar_du_crtc *rcrtc, u32 reg, u32 data)
{
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	struct rcar_du_device *rcdu = rcrtc->group->dev;
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	rcar_du_write(rcdu, rcrtc->mmio_offset + reg, data);
}

static void rcar_du_crtc_clr(struct rcar_du_crtc *rcrtc, u32 reg, u32 clr)
{
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	struct rcar_du_device *rcdu = rcrtc->group->dev;
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	rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
		      rcar_du_read(rcdu, rcrtc->mmio_offset + reg) & ~clr);
}

static void rcar_du_crtc_set(struct rcar_du_crtc *rcrtc, u32 reg, u32 set)
{
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	struct rcar_du_device *rcdu = rcrtc->group->dev;
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	rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
		      rcar_du_read(rcdu, rcrtc->mmio_offset + reg) | set);
}

static void rcar_du_crtc_clr_set(struct rcar_du_crtc *rcrtc, u32 reg,
				 u32 clr, u32 set)
{
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	struct rcar_du_device *rcdu = rcrtc->group->dev;
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	u32 value = rcar_du_read(rcdu, rcrtc->mmio_offset + reg);

	rcar_du_write(rcdu, rcrtc->mmio_offset + reg, (value & ~clr) | set);
}

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static int rcar_du_crtc_get(struct rcar_du_crtc *rcrtc)
{
	int ret;

	ret = clk_prepare_enable(rcrtc->clock);
	if (ret < 0)
		return ret;

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	ret = clk_prepare_enable(rcrtc->extclock);
	if (ret < 0)
		goto error_clock;

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	ret = rcar_du_group_get(rcrtc->group);
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	if (ret < 0)
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		goto error_group;

	return 0;
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error_group:
	clk_disable_unprepare(rcrtc->extclock);
error_clock:
	clk_disable_unprepare(rcrtc->clock);
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	return ret;
}

static void rcar_du_crtc_put(struct rcar_du_crtc *rcrtc)
{
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	rcar_du_group_put(rcrtc->group);
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	clk_disable_unprepare(rcrtc->extclock);
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	clk_disable_unprepare(rcrtc->clock);
}

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/* -----------------------------------------------------------------------------
 * Hardware Setup
 */

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struct dpll_info {
	unsigned int output;
	unsigned int fdpll;
	unsigned int n;
	unsigned int m;
};

static void rcar_du_dpll_divider(struct rcar_du_crtc *rcrtc,
				 struct dpll_info *dpll,
				 unsigned long input,
				 unsigned long target)
{
	unsigned long best_diff = (unsigned long)-1;
	unsigned long diff;
	unsigned int fdpll;
	unsigned int m;
	unsigned int n;

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	/*
	 *   fin                                 fvco        fout       fclkout
	 * in --> [1/M] --> |PD| -> [LPF] -> [VCO] -> [1/P] -+-> [1/FDPLL] -> out
	 *              +-> |  |                             |
	 *              |                                    |
	 *              +---------------- [1/N] <------------+
	 *
	 *	fclkout = fvco / P / FDPLL -- (1)
	 *
	 * fin/M = fvco/P/N
	 *
	 *	fvco = fin * P *  N / M -- (2)
	 *
	 * (1) + (2) indicates
	 *
	 *	fclkout = fin * N / M / FDPLL
	 *
	 * NOTES
	 *	N	: (n + 1)
	 *	M	: (m + 1)
	 *	FDPLL	: (fdpll + 1)
	 *	P	: 2
	 *	2kHz < fvco < 4096MHz
	 *
	 * To minimize the jitter,
	 * N : as large as possible
	 * M : as small as possible
	 */
	for (m = 0; m < 4; m++) {
		for (n = 119; n > 38; n--) {
			/*
			 * This code only runs on 64-bit architectures, the
			 * unsigned long type can thus be used for 64-bit
			 * computation. It will still compile without any
			 * warning on 32-bit architectures.
			 *
			 * To optimize calculations, use fout instead of fvco
			 * to verify the VCO frequency constraint.
			 */
			unsigned long fout = input * (n + 1) / (m + 1);

			if (fout < 1000 || fout > 2048 * 1000 * 1000U)
				continue;

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			for (fdpll = 1; fdpll < 32; fdpll++) {
				unsigned long output;

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				output = fout / (fdpll + 1);
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				if (output >= 400 * 1000 * 1000)
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					continue;

				diff = abs((long)output - (long)target);
				if (best_diff > diff) {
					best_diff = diff;
					dpll->n = n;
					dpll->m = m;
					dpll->fdpll = fdpll;
					dpll->output = output;
				}

				if (diff == 0)
					goto done;
			}
		}
	}

done:
	dev_dbg(rcrtc->group->dev->dev,
		"output:%u, fdpll:%u, n:%u, m:%u, diff:%lu\n",
		 dpll->output, dpll->fdpll, dpll->n, dpll->m,
		 best_diff);
}

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static const struct soc_device_attribute rcar_du_r8a7795_es1[] = {
	{ .soc_id = "r8a7795", .revision = "ES1.*" },
	{ /* sentinel */ }
};

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static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
{
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	const struct drm_display_mode *mode = &rcrtc->crtc.state->adjusted_mode;
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	struct rcar_du_device *rcdu = rcrtc->group->dev;
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	unsigned long mode_clock = mode->clock * 1000;
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	unsigned long clk;
	u32 value;
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	u32 escr;
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	u32 div;

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	/*
	 * Compute the clock divisor and select the internal or external dot
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	 * clock based on the requested frequency.
	 */
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	clk = clk_get_rate(rcrtc->clock);
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	div = DIV_ROUND_CLOSEST(clk, mode_clock);
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	div = clamp(div, 1U, 64U) - 1;
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	escr = div | ESCR_DCLKSEL_CLKS;

	if (rcrtc->extclock) {
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		struct dpll_info dpll = { 0 };
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		unsigned long extclk;
		unsigned long extrate;
		unsigned long rate;
		u32 extdiv;

		extclk = clk_get_rate(rcrtc->extclock);
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		if (rcdu->info->dpll_ch & (1 << rcrtc->index)) {
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			unsigned long target = mode_clock;

			/*
			 * The H3 ES1.x exhibits dot clock duty cycle stability
			 * issues. We can work around them by configuring the
			 * DPLL to twice the desired frequency, coupled with a
			 * /2 post-divider. This isn't needed on other SoCs and
			 * breaks HDMI output on M3-W for a currently unknown
			 * reason, so restrict the workaround to H3 ES1.x.
			 */
			if (soc_device_match(rcar_du_r8a7795_es1))
				target *= 2;

			rcar_du_dpll_divider(rcrtc, &dpll, extclk, target);
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			extclk = dpll.output;
		}

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		extdiv = DIV_ROUND_CLOSEST(extclk, mode_clock);
		extdiv = clamp(extdiv, 1U, 64U) - 1;

		rate = clk / (div + 1);
		extrate = extclk / (extdiv + 1);

		if (abs((long)extrate - (long)mode_clock) <
		    abs((long)rate - (long)mode_clock)) {
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			if (rcdu->info->dpll_ch & (1 << rcrtc->index)) {
				u32 dpllcr = DPLLCR_CODE | DPLLCR_CLKE
					   | DPLLCR_FDPLL(dpll.fdpll)
					   | DPLLCR_N(dpll.n) | DPLLCR_M(dpll.m)
					   | DPLLCR_STBY;

				if (rcrtc->index == 1)
					dpllcr |= DPLLCR_PLCS1
					       |  DPLLCR_INCS_DOTCLKIN1;
				else
					dpllcr |= DPLLCR_PLCS0
					       |  DPLLCR_INCS_DOTCLKIN0;

				rcar_du_group_write(rcrtc->group, DPLLCR,
						    dpllcr);
			}
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			escr = ESCR_DCLKSEL_DCLKIN | extdiv;
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		}
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		dev_dbg(rcrtc->group->dev->dev,
			"mode clock %lu extrate %lu rate %lu ESCR 0x%08x\n",
			mode_clock, extrate, rate, escr);
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	}
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	rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? ESCR2 : ESCR,
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			    escr);
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	rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? OTAR2 : OTAR, 0);
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	/* Signal polarities */
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	value = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? DSMR_VSL : 0)
	      | ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? DSMR_HSL : 0)
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	      | DSMR_DIPM_DISP | DSMR_CSPM;
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	rcar_du_crtc_write(rcrtc, DSMR, value);

	/* Display timings */
	rcar_du_crtc_write(rcrtc, HDSR, mode->htotal - mode->hsync_start - 19);
	rcar_du_crtc_write(rcrtc, HDER, mode->htotal - mode->hsync_start +
					mode->hdisplay - 19);
	rcar_du_crtc_write(rcrtc, HSWR, mode->hsync_end -
					mode->hsync_start - 1);
	rcar_du_crtc_write(rcrtc, HCR,  mode->htotal - 1);

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	rcar_du_crtc_write(rcrtc, VDSR, mode->crtc_vtotal -
					mode->crtc_vsync_end - 2);
	rcar_du_crtc_write(rcrtc, VDER, mode->crtc_vtotal -
					mode->crtc_vsync_end +
					mode->crtc_vdisplay - 2);
	rcar_du_crtc_write(rcrtc, VSPR, mode->crtc_vtotal -
					mode->crtc_vsync_end +
					mode->crtc_vsync_start - 1);
	rcar_du_crtc_write(rcrtc, VCR,  mode->crtc_vtotal - 1);
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	rcar_du_crtc_write(rcrtc, DESR,  mode->htotal - mode->hsync_start - 1);
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	rcar_du_crtc_write(rcrtc, DEWR,  mode->hdisplay);
}

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void rcar_du_crtc_route_output(struct drm_crtc *crtc,
			       enum rcar_du_output output)
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{
	struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
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	struct rcar_du_device *rcdu = rcrtc->group->dev;
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	/*
	 * Store the route from the CRTC output to the DU output. The DU will be
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	 * configured when starting the CRTC.
	 */
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	rcrtc->outputs |= BIT(output);
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	/*
	 * Store RGB routing to DPAD0, the hardware will be configured when
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	 * starting the CRTC.
	 */
	if (output == RCAR_DU_OUTPUT_DPAD0)
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		rcdu->dpad0_source = rcrtc->index;
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}

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static unsigned int plane_zpos(struct rcar_du_plane *plane)
{
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	return plane->plane.state->normalized_zpos;
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}

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static const struct rcar_du_format_info *
plane_format(struct rcar_du_plane *plane)
{
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	return to_rcar_plane_state(plane->plane.state)->format;
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}

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static void rcar_du_crtc_update_planes(struct rcar_du_crtc *rcrtc)
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{
	struct rcar_du_plane *planes[RCAR_DU_NUM_HW_PLANES];
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	struct rcar_du_device *rcdu = rcrtc->group->dev;
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	unsigned int num_planes = 0;
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	unsigned int dptsr_planes;
	unsigned int hwplanes = 0;
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	unsigned int prio = 0;
	unsigned int i;
	u32 dspr = 0;

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	for (i = 0; i < rcrtc->group->num_planes; ++i) {
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		struct rcar_du_plane *plane = &rcrtc->group->planes[i];
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		unsigned int j;

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		if (plane->plane.state->crtc != &rcrtc->crtc ||
		    !plane->plane.state->visible)
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			continue;

		/* Insert the plane in the sorted planes array. */
		for (j = num_planes++; j > 0; --j) {
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			if (plane_zpos(planes[j-1]) <= plane_zpos(plane))
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				break;
			planes[j] = planes[j-1];
		}

		planes[j] = plane;
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		prio += plane_format(plane)->planes * 4;
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	}

	for (i = 0; i < num_planes; ++i) {
		struct rcar_du_plane *plane = planes[i];
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		struct drm_plane_state *state = plane->plane.state;
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		unsigned int index = to_rcar_plane_state(state)->hwindex;
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		prio -= 4;
		dspr |= (index + 1) << prio;
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		hwplanes |= 1 << index;
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		if (plane_format(plane)->planes == 2) {
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			index = (index + 1) % 8;

			prio -= 4;
			dspr |= (index + 1) << prio;
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			hwplanes |= 1 << index;
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		}
	}

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	/* If VSP+DU integration is enabled the plane assignment is fixed. */
	if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE)) {
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		if (rcdu->info->gen < 3) {
			dspr = (rcrtc->index % 2) + 1;
			hwplanes = 1 << (rcrtc->index % 2);
		} else {
			dspr = (rcrtc->index % 2) ? 3 : 1;
			hwplanes = 1 << ((rcrtc->index % 2) ? 2 : 0);
		}
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	}

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	/*
	 * Update the planes to display timing and dot clock generator
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	 * associations.
	 *
	 * Updating the DPTSR register requires restarting the CRTC group,
	 * resulting in visible flicker. To mitigate the issue only update the
	 * association if needed by enabled planes. Planes being disabled will
	 * keep their current association.
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	 */
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	mutex_lock(&rcrtc->group->lock);

	dptsr_planes = rcrtc->index % 2 ? rcrtc->group->dptsr_planes | hwplanes
		     : rcrtc->group->dptsr_planes & ~hwplanes;

	if (dptsr_planes != rcrtc->group->dptsr_planes) {
		rcar_du_group_write(rcrtc->group, DPTSR,
				    (dptsr_planes << 16) | dptsr_planes);
		rcrtc->group->dptsr_planes = dptsr_planes;

		if (rcrtc->group->used_crtcs)
			rcar_du_group_restart(rcrtc->group);
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	}

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	/* Restart the group if plane sources have changed. */
	if (rcrtc->group->need_restart)
		rcar_du_group_restart(rcrtc->group);

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	mutex_unlock(&rcrtc->group->lock);

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	rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR,
			    dspr);
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}

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/* -----------------------------------------------------------------------------
 * Page Flip
 */

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void rcar_du_crtc_finish_page_flip(struct rcar_du_crtc *rcrtc)
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{
	struct drm_pending_vblank_event *event;
	struct drm_device *dev = rcrtc->crtc.dev;
	unsigned long flags;

	spin_lock_irqsave(&dev->event_lock, flags);
	event = rcrtc->event;
	rcrtc->event = NULL;
	spin_unlock_irqrestore(&dev->event_lock, flags);

	if (event == NULL)
		return;

	spin_lock_irqsave(&dev->event_lock, flags);
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	drm_crtc_send_vblank_event(&rcrtc->crtc, event);
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	wake_up(&rcrtc->flip_wait);
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	spin_unlock_irqrestore(&dev->event_lock, flags);

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	drm_crtc_vblank_put(&rcrtc->crtc);
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}

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static bool rcar_du_crtc_page_flip_pending(struct rcar_du_crtc *rcrtc)
{
	struct drm_device *dev = rcrtc->crtc.dev;
	unsigned long flags;
	bool pending;

	spin_lock_irqsave(&dev->event_lock, flags);
	pending = rcrtc->event != NULL;
	spin_unlock_irqrestore(&dev->event_lock, flags);

	return pending;
}

static void rcar_du_crtc_wait_page_flip(struct rcar_du_crtc *rcrtc)
{
	struct rcar_du_device *rcdu = rcrtc->group->dev;

	if (wait_event_timeout(rcrtc->flip_wait,
			       !rcar_du_crtc_page_flip_pending(rcrtc),
			       msecs_to_jiffies(50)))
		return;

	dev_warn(rcdu->dev, "page flip timeout\n");

	rcar_du_crtc_finish_page_flip(rcrtc);
}

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/* -----------------------------------------------------------------------------
 * Start/Stop and Suspend/Resume
 */

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static void rcar_du_crtc_setup(struct rcar_du_crtc *rcrtc)
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{
	/* Set display off and background to black */
	rcar_du_crtc_write(rcrtc, DOOR, DOOR_RGB(0, 0, 0));
	rcar_du_crtc_write(rcrtc, BPOR, BPOR_RGB(0, 0, 0));

	/* Configure display timings and output routing */
	rcar_du_crtc_set_display_timing(rcrtc);
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	rcar_du_group_set_routing(rcrtc->group);
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	/* Start with all planes disabled. */
	rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR, 0);
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	/* Enable the VSP compositor. */
	if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
		rcar_du_vsp_enable(rcrtc);

	/* Turn vertical blanking interrupt reporting on. */
	drm_crtc_vblank_on(&rcrtc->crtc);
}

static void rcar_du_crtc_start(struct rcar_du_crtc *rcrtc)
{
	bool interlaced;

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	/*
	 * Select master sync mode. This enables display operation in master
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	 * sync mode (with the HSYNC and VSYNC signals configured as outputs and
	 * actively driven).
	 */
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	interlaced = rcrtc->crtc.mode.flags & DRM_MODE_FLAG_INTERLACE;
	rcar_du_crtc_clr_set(rcrtc, DSYSR, DSYSR_TVM_MASK | DSYSR_SCM_MASK,
			     (interlaced ? DSYSR_SCM_INT_VIDEO : 0) |
			     DSYSR_TVM_MASTER);
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	rcar_du_group_start_stop(rcrtc->group, true);
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}

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static void rcar_du_crtc_disable_planes(struct rcar_du_crtc *rcrtc)
{
	struct rcar_du_device *rcdu = rcrtc->group->dev;
	struct drm_crtc *crtc = &rcrtc->crtc;
	u32 status;

	/* Make sure vblank interrupts are enabled. */
	drm_crtc_vblank_get(crtc);

	/*
	 * Disable planes and calculate how many vertical blanking interrupts we
	 * have to wait for. If a vertical blanking interrupt has been triggered
	 * but not processed yet, we don't know whether it occurred before or
	 * after the planes got disabled. We thus have to wait for two vblank
	 * interrupts in that case.
	 */
	spin_lock_irq(&rcrtc->vblank_lock);
	rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR, 0);
	status = rcar_du_crtc_read(rcrtc, DSSR);
	rcrtc->vblank_count = status & DSSR_VBK ? 2 : 1;
	spin_unlock_irq(&rcrtc->vblank_lock);

	if (!wait_event_timeout(rcrtc->vblank_wait, rcrtc->vblank_count == 0,
				msecs_to_jiffies(100)))
		dev_warn(rcdu->dev, "vertical blanking timeout\n");

	drm_crtc_vblank_put(crtc);
}

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static void rcar_du_crtc_stop(struct rcar_du_crtc *rcrtc)
{
	struct drm_crtc *crtc = &rcrtc->crtc;

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	/*
	 * Disable all planes and wait for the change to take effect. This is
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	 * required as the plane enable registers are updated on vblank, and no
	 * vblank will occur once the CRTC is stopped. Disabling planes when
	 * starting the CRTC thus wouldn't be enough as it would start scanning
	 * out immediately from old frame buffers until the next vblank.
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	 *
	 * This increases the CRTC stop delay, especially when multiple CRTCs
	 * are stopped in one operation as we now wait for one vblank per CRTC.
	 * Whether this can be improved needs to be researched.
	 */
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	rcar_du_crtc_disable_planes(rcrtc);
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	/*
	 * Disable vertical blanking interrupt reporting. We first need to wait
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	 * for page flip completion before stopping the CRTC as userspace
	 * expects page flips to eventually complete.
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	 */
	rcar_du_crtc_wait_page_flip(rcrtc);
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	drm_crtc_vblank_off(crtc);
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	/* Disable the VSP compositor. */
	if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
		rcar_du_vsp_disable(rcrtc);

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	/*
	 * Select switch sync mode. This stops display operation and configures
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	 * the HSYNC and VSYNC signals as inputs.
	 */
	rcar_du_crtc_clr_set(rcrtc, DSYSR, DSYSR_TVM_MASK, DSYSR_TVM_SWITCH);

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	rcar_du_group_start_stop(rcrtc->group, false);
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}

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/* -----------------------------------------------------------------------------
 * CRTC Functions
 */

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static void rcar_du_crtc_atomic_enable(struct drm_crtc *crtc,
				       struct drm_crtc_state *old_state)
608 609 610
{
	struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);

611 612 613 614 615 616 617 618 619 620
	/*
	 * If the CRTC has already been setup by the .atomic_begin() handler we
	 * can skip the setup stage.
	 */
	if (!rcrtc->initialized) {
		rcar_du_crtc_get(rcrtc);
		rcar_du_crtc_setup(rcrtc);
		rcrtc->initialized = true;
	}

621 622 623
	rcar_du_crtc_start(rcrtc);
}

624 625
static void rcar_du_crtc_atomic_disable(struct drm_crtc *crtc,
					struct drm_crtc_state *old_state)
626 627
{
	struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
628

629 630
	rcar_du_crtc_stop(rcrtc);
	rcar_du_crtc_put(rcrtc);
631

632 633 634 635 636 637 638
	spin_lock_irq(&crtc->dev->event_lock);
	if (crtc->state->event) {
		drm_crtc_send_vblank_event(crtc, crtc->state->event);
		crtc->state->event = NULL;
	}
	spin_unlock_irq(&crtc->dev->event_lock);

639
	rcrtc->initialized = false;
640
	rcrtc->outputs = 0;
641 642
}

643 644
static void rcar_du_crtc_atomic_begin(struct drm_crtc *crtc,
				      struct drm_crtc_state *old_crtc_state)
645 646
{
	struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
647

648 649 650 651 652 653 654 655 656 657 658 659 660
	WARN_ON(!crtc->state->enable);

	/*
	 * If a mode set is in progress we can be called with the CRTC disabled.
	 * We then need to first setup the CRTC in order to configure planes.
	 * The .atomic_enable() handler will notice and skip the CRTC setup.
	 */
	if (!rcrtc->initialized) {
		rcar_du_crtc_get(rcrtc);
		rcar_du_crtc_setup(rcrtc);
		rcrtc->initialized = true;
	}

661 662
	if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
		rcar_du_vsp_atomic_begin(rcrtc);
663 664
}

665 666
static void rcar_du_crtc_atomic_flush(struct drm_crtc *crtc,
				      struct drm_crtc_state *old_crtc_state)
667 668
{
	struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
669 670
	struct drm_device *dev = rcrtc->crtc.dev;
	unsigned long flags;
671

672
	rcar_du_crtc_update_planes(rcrtc);
673

674 675 676 677 678 679 680 681 682
	if (crtc->state->event) {
		WARN_ON(drm_crtc_vblank_get(crtc) != 0);

		spin_lock_irqsave(&dev->event_lock, flags);
		rcrtc->event = crtc->state->event;
		crtc->state->event = NULL;
		spin_unlock_irqrestore(&dev->event_lock, flags);
	}

683 684
	if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
		rcar_du_vsp_atomic_flush(rcrtc);
685 686
}

687
static const struct drm_crtc_helper_funcs crtc_helper_funcs = {
688 689
	.atomic_begin = rcar_du_crtc_atomic_begin,
	.atomic_flush = rcar_du_crtc_atomic_flush,
690
	.atomic_enable = rcar_du_crtc_atomic_enable,
691
	.atomic_disable = rcar_du_crtc_atomic_disable,
692 693
};

694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739
static struct drm_crtc_state *
rcar_du_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
{
	struct rcar_du_crtc_state *state;
	struct rcar_du_crtc_state *copy;

	if (WARN_ON(!crtc->state))
		return NULL;

	state = to_rcar_crtc_state(crtc->state);
	copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
	if (copy == NULL)
		return NULL;

	__drm_atomic_helper_crtc_duplicate_state(crtc, &copy->state);

	return &copy->state;
}

static void rcar_du_crtc_atomic_destroy_state(struct drm_crtc *crtc,
					      struct drm_crtc_state *state)
{
	__drm_atomic_helper_crtc_destroy_state(state);
	kfree(to_rcar_crtc_state(state));
}

static void rcar_du_crtc_reset(struct drm_crtc *crtc)
{
	struct rcar_du_crtc_state *state;

	if (crtc->state) {
		rcar_du_crtc_atomic_destroy_state(crtc, crtc->state);
		crtc->state = NULL;
	}

	state = kzalloc(sizeof(*state), GFP_KERNEL);
	if (state == NULL)
		return;

	state->crc.source = VSP1_DU_CRC_NONE;
	state->crc.index = 0;

	crtc->state = &state->state;
	crtc->state->crtc = crtc;
}

740 741 742 743 744 745
static int rcar_du_crtc_enable_vblank(struct drm_crtc *crtc)
{
	struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);

	rcar_du_crtc_write(rcrtc, DSRCR, DSRCR_VBCL);
	rcar_du_crtc_set(rcrtc, DIER, DIER_VBE);
746
	rcrtc->vblank_enable = true;
747 748 749 750 751 752 753 754 755

	return 0;
}

static void rcar_du_crtc_disable_vblank(struct drm_crtc *crtc)
{
	struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);

	rcar_du_crtc_clr(rcrtc, DIER, DIER_VBE);
756
	rcrtc->vblank_enable = false;
757 758
}

759 760 761
static int rcar_du_crtc_parse_crc_source(struct rcar_du_crtc *rcrtc,
					 const char *source_name,
					 enum vsp1_du_crc_source *source)
762
{
763
	unsigned int index;
764 765 766 767 768 769 770
	int ret;

	/*
	 * Parse the source name. Supported values are "plane%u" to compute the
	 * CRC on an input plane (%u is the plane ID), and "auto" to compute the
	 * CRC on the composer (VSP) output.
	 */
771

772
	if (!source_name) {
773 774
		*source = VSP1_DU_CRC_NONE;
		return 0;
775
	} else if (!strcmp(source_name, "auto")) {
776 777
		*source = VSP1_DU_CRC_OUTPUT;
		return 0;
778
	} else if (strstarts(source_name, "plane")) {
779 780 781
		unsigned int i;

		*source = VSP1_DU_CRC_PLANE;
782 783 784 785 786 787

		ret = kstrtouint(source_name + strlen("plane"), 10, &index);
		if (ret < 0)
			return ret;

		for (i = 0; i < rcrtc->vsp->num_planes; ++i) {
788 789
			if (index == rcrtc->vsp->planes[i].plane.base.id)
				return i;
790
		}
791
	}
792

793 794 795 796 797 798 799 800 801 802 803 804
	return -EINVAL;
}

static int rcar_du_crtc_verify_crc_source(struct drm_crtc *crtc,
					  const char *source_name,
					  size_t *values_cnt)
{
	struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
	enum vsp1_du_crc_source source;

	if (rcar_du_crtc_parse_crc_source(rcrtc, source_name, &source) < 0) {
		DRM_DEBUG_DRIVER("unknown source %s\n", source_name);
805 806 807
		return -EINVAL;
	}

808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828
	*values_cnt = 1;
	return 0;
}

static int rcar_du_crtc_set_crc_source(struct drm_crtc *crtc,
				       const char *source_name,
				       size_t *values_cnt)
{
	struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
	struct drm_modeset_acquire_ctx ctx;
	struct drm_crtc_state *crtc_state;
	struct drm_atomic_state *state;
	enum vsp1_du_crc_source source;
	unsigned int index;
	int ret;

	ret = rcar_du_crtc_parse_crc_source(rcrtc, source_name, &source);
	if (ret < 0)
		return ret;

	index = ret;
829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883
	*values_cnt = 1;

	/* Perform an atomic commit to set the CRC source. */
	drm_modeset_acquire_init(&ctx, 0);

	state = drm_atomic_state_alloc(crtc->dev);
	if (!state) {
		ret = -ENOMEM;
		goto unlock;
	}

	state->acquire_ctx = &ctx;

retry:
	crtc_state = drm_atomic_get_crtc_state(state, crtc);
	if (!IS_ERR(crtc_state)) {
		struct rcar_du_crtc_state *rcrtc_state;

		rcrtc_state = to_rcar_crtc_state(crtc_state);
		rcrtc_state->crc.source = source;
		rcrtc_state->crc.index = index;

		ret = drm_atomic_commit(state);
	} else {
		ret = PTR_ERR(crtc_state);
	}

	if (ret == -EDEADLK) {
		drm_atomic_state_clear(state);
		drm_modeset_backoff(&ctx);
		goto retry;
	}

	drm_atomic_state_put(state);

unlock:
	drm_modeset_drop_locks(&ctx);
	drm_modeset_acquire_fini(&ctx);

	return 0;
}

static const struct drm_crtc_funcs crtc_funcs_gen2 = {
	.reset = rcar_du_crtc_reset,
	.destroy = drm_crtc_cleanup,
	.set_config = drm_atomic_helper_set_config,
	.page_flip = drm_atomic_helper_page_flip,
	.atomic_duplicate_state = rcar_du_crtc_atomic_duplicate_state,
	.atomic_destroy_state = rcar_du_crtc_atomic_destroy_state,
	.enable_vblank = rcar_du_crtc_enable_vblank,
	.disable_vblank = rcar_du_crtc_disable_vblank,
};

static const struct drm_crtc_funcs crtc_funcs_gen3 = {
	.reset = rcar_du_crtc_reset,
884
	.destroy = drm_crtc_cleanup,
885
	.set_config = drm_atomic_helper_set_config,
886
	.page_flip = drm_atomic_helper_page_flip,
887 888
	.atomic_duplicate_state = rcar_du_crtc_atomic_duplicate_state,
	.atomic_destroy_state = rcar_du_crtc_atomic_destroy_state,
889 890
	.enable_vblank = rcar_du_crtc_enable_vblank,
	.disable_vblank = rcar_du_crtc_disable_vblank,
891
	.set_crc_source = rcar_du_crtc_set_crc_source,
892
	.verify_crc_source = rcar_du_crtc_verify_crc_source,
893 894
};

895 896 897 898 899 900 901
/* -----------------------------------------------------------------------------
 * Interrupt Handling
 */

static irqreturn_t rcar_du_crtc_irq(int irq, void *arg)
{
	struct rcar_du_crtc *rcrtc = arg;
902
	struct rcar_du_device *rcdu = rcrtc->group->dev;
903 904 905
	irqreturn_t ret = IRQ_NONE;
	u32 status;

906 907
	spin_lock(&rcrtc->vblank_lock);

908 909 910
	status = rcar_du_crtc_read(rcrtc, DSSR);
	rcar_du_crtc_write(rcrtc, DSRCR, status & DSRCR_MASK);

911 912 913 914 915 916 917 918 919 920 921 922 923 924
	if (status & DSSR_VBK) {
		/*
		 * Wake up the vblank wait if the counter reaches 0. This must
		 * be protected by the vblank_lock to avoid races in
		 * rcar_du_crtc_disable_planes().
		 */
		if (rcrtc->vblank_count) {
			if (--rcrtc->vblank_count == 0)
				wake_up(&rcrtc->vblank_wait);
		}
	}

	spin_unlock(&rcrtc->vblank_lock);

925
	if (status & DSSR_VBK) {
926 927
		if (rcdu->info->gen < 3) {
			drm_crtc_handle_vblank(&rcrtc->crtc);
928
			rcar_du_crtc_finish_page_flip(rcrtc);
929
		}
930

931 932 933 934 935 936 937 938 939 940
		ret = IRQ_HANDLED;
	}

	return ret;
}

/* -----------------------------------------------------------------------------
 * Initialization
 */

941 942
int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int swindex,
			unsigned int hwindex)
943
{
944
	static const unsigned int mmio_offsets[] = {
945
		DU0_REG_OFFSET, DU1_REG_OFFSET, DU2_REG_OFFSET, DU3_REG_OFFSET
946 947
	};

948
	struct rcar_du_device *rcdu = rgrp->dev;
949
	struct platform_device *pdev = to_platform_device(rcdu->dev);
950
	struct rcar_du_crtc *rcrtc = &rcdu->crtcs[swindex];
951
	struct drm_crtc *crtc = &rcrtc->crtc;
952
	struct drm_plane *primary;
953
	unsigned int irqflags;
954 955
	struct clk *clk;
	char clk_name[9];
956 957
	char *name;
	int irq;
958 959
	int ret;

960
	/* Get the CRTC clock and the optional external clock. */
961
	if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
962
		sprintf(clk_name, "du.%u", hwindex);
963 964 965 966 967 968 969
		name = clk_name;
	} else {
		name = NULL;
	}

	rcrtc->clock = devm_clk_get(rcdu->dev, name);
	if (IS_ERR(rcrtc->clock)) {
970
		dev_err(rcdu->dev, "no clock for DU channel %u\n", hwindex);
971 972 973
		return PTR_ERR(rcrtc->clock);
	}

974
	sprintf(clk_name, "dclkin.%u", hwindex);
975 976 977 978
	clk = devm_clk_get(rcdu->dev, clk_name);
	if (!IS_ERR(clk)) {
		rcrtc->extclock = clk;
	} else if (PTR_ERR(rcrtc->clock) == -EPROBE_DEFER) {
979
		dev_info(rcdu->dev, "can't get external clock %u\n", hwindex);
980 981 982
		return -EPROBE_DEFER;
	}

983
	init_waitqueue_head(&rcrtc->flip_wait);
984 985
	init_waitqueue_head(&rcrtc->vblank_wait);
	spin_lock_init(&rcrtc->vblank_lock);
986

987
	rcrtc->group = rgrp;
988 989
	rcrtc->mmio_offset = mmio_offsets[hwindex];
	rcrtc->index = hwindex;
990

991
	if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE))
992
		primary = &rcrtc->vsp->planes[rcrtc->vsp_pipe].plane;
993
	else
994
		primary = &rgrp->planes[swindex % 2].plane;
995

996 997 998 999
	ret = drm_crtc_init_with_planes(rcdu->ddev, crtc, primary, NULL,
					rcdu->info->gen <= 2 ?
					&crtc_funcs_gen2 : &crtc_funcs_gen3,
					NULL);
1000 1001 1002 1003 1004
	if (ret < 0)
		return ret;

	drm_crtc_helper_add(crtc, &crtc_helper_funcs);

1005 1006 1007
	/* Start with vertical blanking interrupt reporting disabled. */
	drm_crtc_vblank_off(crtc);

1008 1009
	/* Register the interrupt handler. */
	if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
1010 1011
		/* The IRQ's are associated with the CRTC (sw)index. */
		irq = platform_get_irq(pdev, swindex);
1012 1013 1014 1015 1016 1017 1018
		irqflags = 0;
	} else {
		irq = platform_get_irq(pdev, 0);
		irqflags = IRQF_SHARED;
	}

	if (irq < 0) {
1019
		dev_err(rcdu->dev, "no IRQ for CRTC %u\n", swindex);
1020
		return irq;
1021 1022 1023 1024 1025 1026
	}

	ret = devm_request_irq(rcdu->dev, irq, rcar_du_crtc_irq, irqflags,
			       dev_name(rcdu->dev), rcrtc);
	if (ret < 0) {
		dev_err(rcdu->dev,
1027
			"failed to register IRQ for CRTC %u\n", swindex);
1028 1029 1030
		return ret;
	}

1031 1032
	return 0;
}