boot.c 44.9 KB
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/*
 *  boot.c - Architecture-Specific Low-Level ACPI Boot Support
 *
 *  Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
 *  Copyright (C) 2001 Jun Nakajima <jun.nakajima@intel.com>
 *
 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 */

#include <linux/init.h>
#include <linux/acpi.h>
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#include <linux/acpi_pmtmr.h>
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#include <linux/efi.h>
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#include <linux/cpumask.h>
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#include <linux/module.h>
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#include <linux/dmi.h>
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#include <linux/irq.h>
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#include <linux/bootmem.h>
#include <linux/ioport.h>
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#include <asm/pgtable.h>
#include <asm/io_apic.h>
#include <asm/apic.h>
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#include <asm/genapic.h>
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#include <asm/io.h>
#include <asm/mpspec.h>
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#include <asm/smp.h>
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#ifdef CONFIG_X86_LOCAL_APIC
# include <mach_apic.h>
#endif

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static int __initdata acpi_force = 0;
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u32 acpi_rsdt_forced;
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#ifdef	CONFIG_ACPI
int acpi_disabled = 0;
#else
int acpi_disabled = 1;
#endif
EXPORT_SYMBOL(acpi_disabled);

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#ifdef	CONFIG_X86_64

#include <asm/proto.h>
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#else				/* X86 */
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#ifdef	CONFIG_X86_LOCAL_APIC
#include <mach_apic.h>
#include <mach_mpparse.h>
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#endif				/* CONFIG_X86_LOCAL_APIC */
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#endif				/* X86 */
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#define BAD_MADT_ENTRY(entry, end) (					    \
		(!entry) || (unsigned long)entry + sizeof(*entry) > end ||  \
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		((struct acpi_subtable_header *)entry)->length < sizeof(*entry))
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#define PREFIX			"ACPI: "

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int acpi_noirq;				/* skip ACPI IRQ initialization */
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int acpi_pci_disabled;		/* skip ACPI PCI scan and IRQ initialization */
EXPORT_SYMBOL(acpi_pci_disabled);
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int acpi_ht __initdata = 1;	/* enable HT */

int acpi_lapic;
int acpi_ioapic;
int acpi_strict;

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u8 acpi_sci_flags __initdata;
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int acpi_sci_override_gsi __initdata;
int acpi_skip_timer_override __initdata;
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int acpi_use_timer_override __initdata;
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#ifdef CONFIG_X86_LOCAL_APIC
static u64 acpi_lapic_addr __initdata = APIC_DEFAULT_PHYS_BASE;
#endif

#ifndef __HAVE_ARCH_CMPXCHG
#warning ACPI uses CMPXCHG, i486 and later hardware
#endif

/* --------------------------------------------------------------------------
                              Boot-time Configuration
   -------------------------------------------------------------------------- */

/*
 * The default interrupt routing model is PIC (8259).  This gets
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 * overridden if IOAPICs are enumerated (below).
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 */
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enum acpi_irq_model_id acpi_irq_model = ACPI_IRQ_MODEL_PIC;
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/*
 * Temporarily use the virtual area starting from FIX_IO_APIC_BASE_END,
 * to map the target physical address. The problem is that set_fixmap()
 * provides a single page, and it is possible that the page is not
 * sufficient.
 * By using this area, we can map up to MAX_IO_APICS pages temporarily,
 * i.e. until the next __va_range() call.
 *
 * Important Safety Note:  The fixed I/O APIC page numbers are *subtracted*
 * from the fixed base.  That's why we start at FIX_IO_APIC_BASE_END and
 * count idx down while incrementing the phys address.
 */
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char *__init __acpi_map_table(unsigned long phys, unsigned long size)
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{
	unsigned long base, offset, mapped_size;
	int idx;

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	if (!phys || !size)
		return NULL;

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	if (phys+size <= (max_low_pfn_mapped << PAGE_SHIFT))
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		return __va(phys);
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	offset = phys & (PAGE_SIZE - 1);
	mapped_size = PAGE_SIZE - offset;
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	clear_fixmap(FIX_ACPI_END);
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	set_fixmap(FIX_ACPI_END, phys);
	base = fix_to_virt(FIX_ACPI_END);

	/*
	 * Most cases can be covered by the below.
	 */
	idx = FIX_ACPI_END;
	while (mapped_size < size) {
		if (--idx < FIX_ACPI_BEGIN)
			return NULL;	/* cannot handle this */
		phys += PAGE_SIZE;
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		clear_fixmap(idx);
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		set_fixmap(idx, phys);
		mapped_size += PAGE_SIZE;
	}

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	return ((unsigned char *)base + offset);
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}

#ifdef CONFIG_PCI_MMCONFIG
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static int acpi_mcfg_64bit_base_addr __initdata = FALSE;

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/* The physical address of the MMCONFIG aperture.  Set from ACPI tables. */
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struct acpi_mcfg_allocation *pci_mmcfg_config;
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int pci_mmcfg_config_num;

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static int __init acpi_mcfg_oem_check(struct acpi_table_mcfg *mcfg)
{
	if (!strcmp(mcfg->header.oem_id, "SGI"))
		acpi_mcfg_64bit_base_addr = TRUE;

	return 0;
}

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int __init acpi_parse_mcfg(struct acpi_table_header *header)
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{
	struct acpi_table_mcfg *mcfg;
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	unsigned long i;
	int config_size;
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	if (!header)
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		return -EINVAL;

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	mcfg = (struct acpi_table_mcfg *)header;
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	/* how many config structures do we have */
	pci_mmcfg_config_num = 0;
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	i = header->length - sizeof(struct acpi_table_mcfg);
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	while (i >= sizeof(struct acpi_mcfg_allocation)) {
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		++pci_mmcfg_config_num;
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		i -= sizeof(struct acpi_mcfg_allocation);
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	};
	if (pci_mmcfg_config_num == 0) {
		printk(KERN_ERR PREFIX "MMCONFIG has no entries\n");
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		return -ENODEV;
	}

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	config_size = pci_mmcfg_config_num * sizeof(*pci_mmcfg_config);
	pci_mmcfg_config = kmalloc(config_size, GFP_KERNEL);
	if (!pci_mmcfg_config) {
		printk(KERN_WARNING PREFIX
		       "No memory for MCFG config tables\n");
		return -ENOMEM;
	}

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	memcpy(pci_mmcfg_config, &mcfg[1], config_size);
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	acpi_mcfg_oem_check(mcfg);

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	for (i = 0; i < pci_mmcfg_config_num; ++i) {
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		if ((pci_mmcfg_config[i].address > 0xFFFFFFFF) &&
		    !acpi_mcfg_64bit_base_addr) {
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			printk(KERN_ERR PREFIX
			       "MMCONFIG not in low 4GB of memory\n");
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			kfree(pci_mmcfg_config);
			pci_mmcfg_config_num = 0;
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			return -ENODEV;
		}
	}
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	return 0;
}
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#endif				/* CONFIG_PCI_MMCONFIG */
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#ifdef CONFIG_X86_LOCAL_APIC
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static int __init acpi_parse_madt(struct acpi_table_header *table)
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{
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	struct acpi_table_madt *madt = NULL;
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	if (!cpu_has_apic)
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		return -EINVAL;

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	madt = (struct acpi_table_madt *)table;
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	if (!madt) {
		printk(KERN_WARNING PREFIX "Unable to map MADT\n");
		return -ENODEV;
	}

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	if (madt->address) {
		acpi_lapic_addr = (u64) madt->address;
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		printk(KERN_DEBUG PREFIX "Local APIC address 0x%08x\n",
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		       madt->address);
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	}

	acpi_madt_oem_check(madt->header.oem_id, madt->header.oem_table_id);
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	return 0;
}

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static void __cpuinit acpi_register_lapic(int id, u8 enabled)
{
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	unsigned int ver = 0;

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	if (!enabled) {
		++disabled_cpus;
		return;
	}

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	if (boot_cpu_physical_apicid != -1U)
		ver = apic_version[boot_cpu_physical_apicid];

	generic_processor_info(id, ver);
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}

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static int __init
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acpi_parse_lapic(struct acpi_subtable_header * header, const unsigned long end)
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{
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	struct acpi_madt_local_apic *processor = NULL;
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	processor = (struct acpi_madt_local_apic *)header;
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	if (BAD_MADT_ENTRY(processor, end))
		return -EINVAL;

	acpi_table_print_madt_entry(header);

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	/*
	 * We need to register disabled CPU as well to permit
	 * counting disabled CPUs. This allows us to size
	 * cpus_possible_map more accurately, to permit
	 * to not preallocating memory for all NR_CPUS
	 * when we use CPU hotplug.
	 */
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	acpi_register_lapic(processor->id,	/* APIC ID */
			    processor->lapic_flags & ACPI_MADT_ENABLED);
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	return 0;
}

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static int __init
acpi_parse_sapic(struct acpi_subtable_header *header, const unsigned long end)
{
	struct acpi_madt_local_sapic *processor = NULL;

	processor = (struct acpi_madt_local_sapic *)header;

	if (BAD_MADT_ENTRY(processor, end))
		return -EINVAL;

	acpi_table_print_madt_entry(header);

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	acpi_register_lapic((processor->id << 8) | processor->eid,/* APIC ID */
			    processor->lapic_flags & ACPI_MADT_ENABLED);
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	return 0;
}

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static int __init
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acpi_parse_lapic_addr_ovr(struct acpi_subtable_header * header,
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			  const unsigned long end)
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{
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	struct acpi_madt_local_apic_override *lapic_addr_ovr = NULL;
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	lapic_addr_ovr = (struct acpi_madt_local_apic_override *)header;
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	if (BAD_MADT_ENTRY(lapic_addr_ovr, end))
		return -EINVAL;

	acpi_lapic_addr = lapic_addr_ovr->address;

	return 0;
}

static int __init
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acpi_parse_lapic_nmi(struct acpi_subtable_header * header, const unsigned long end)
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{
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	struct acpi_madt_local_apic_nmi *lapic_nmi = NULL;
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	lapic_nmi = (struct acpi_madt_local_apic_nmi *)header;
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	if (BAD_MADT_ENTRY(lapic_nmi, end))
		return -EINVAL;

	acpi_table_print_madt_entry(header);

	if (lapic_nmi->lint != 1)
		printk(KERN_WARNING PREFIX "NMI not connected to LINT 1!\n");

	return 0;
}

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#endif				/*CONFIG_X86_LOCAL_APIC */
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#ifdef CONFIG_X86_IO_APIC
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static int __init
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acpi_parse_ioapic(struct acpi_subtable_header * header, const unsigned long end)
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{
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	struct acpi_madt_io_apic *ioapic = NULL;
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	ioapic = (struct acpi_madt_io_apic *)header;
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	if (BAD_MADT_ENTRY(ioapic, end))
		return -EINVAL;
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	acpi_table_print_madt_entry(header);

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	mp_register_ioapic(ioapic->id,
			   ioapic->address, ioapic->global_irq_base);

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	return 0;
}

/*
 * Parse Interrupt Source Override for the ACPI SCI
 */
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static void __init acpi_sci_ioapic_setup(u32 gsi, u16 polarity, u16 trigger)
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{
	if (trigger == 0)	/* compatible SCI trigger is level */
		trigger = 3;

	if (polarity == 0)	/* compatible SCI polarity is low */
		polarity = 3;

	/* Command-line over-ride via acpi_sci= */
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	if (acpi_sci_flags & ACPI_MADT_TRIGGER_MASK)
		trigger = (acpi_sci_flags & ACPI_MADT_TRIGGER_MASK) >> 2;
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	if (acpi_sci_flags & ACPI_MADT_POLARITY_MASK)
		polarity = acpi_sci_flags & ACPI_MADT_POLARITY_MASK;
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	/*
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	 * mp_config_acpi_legacy_irqs() already setup IRQs < 16
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	 * If GSI is < 16, this will update its flags,
	 * else it will create a new mp_irqs[] entry.
	 */
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	mp_override_legacy_irq(gsi, polarity, trigger, gsi);
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	/*
	 * stash over-ride to indicate we've been here
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	 * and for later update of acpi_gbl_FADT
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	 */
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	acpi_sci_override_gsi = gsi;
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	return;
}

static int __init
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acpi_parse_int_src_ovr(struct acpi_subtable_header * header,
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		       const unsigned long end)
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{
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	struct acpi_madt_interrupt_override *intsrc = NULL;
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	intsrc = (struct acpi_madt_interrupt_override *)header;
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	if (BAD_MADT_ENTRY(intsrc, end))
		return -EINVAL;

	acpi_table_print_madt_entry(header);

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	if (intsrc->source_irq == acpi_gbl_FADT.sci_interrupt) {
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		acpi_sci_ioapic_setup(intsrc->global_irq,
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				      intsrc->inti_flags & ACPI_MADT_POLARITY_MASK,
				      (intsrc->inti_flags & ACPI_MADT_TRIGGER_MASK) >> 2);
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		return 0;
	}

	if (acpi_skip_timer_override &&
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	    intsrc->source_irq == 0 && intsrc->global_irq == 2) {
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		printk(PREFIX "BIOS IRQ0 pin2 override ignored.\n");
		return 0;
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	}

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	mp_override_legacy_irq(intsrc->source_irq,
				intsrc->inti_flags & ACPI_MADT_POLARITY_MASK,
				(intsrc->inti_flags & ACPI_MADT_TRIGGER_MASK) >> 2,
				intsrc->global_irq);
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	return 0;
}

static int __init
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acpi_parse_nmi_src(struct acpi_subtable_header * header, const unsigned long end)
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{
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	struct acpi_madt_nmi_source *nmi_src = NULL;
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	nmi_src = (struct acpi_madt_nmi_source *)header;
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	if (BAD_MADT_ENTRY(nmi_src, end))
		return -EINVAL;

	acpi_table_print_madt_entry(header);

	/* TBD: Support nimsrc entries? */

	return 0;
}

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#endif				/* CONFIG_X86_IO_APIC */
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/*
 * acpi_pic_sci_set_trigger()
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 *
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 * use ELCR to set PIC-mode trigger type for SCI
 *
 * If a PIC-mode SCI is not recognized or gives spurious IRQ7's
 * it may require Edge Trigger -- use "acpi_sci=edge"
 *
 * Port 0x4d0-4d1 are ECLR1 and ECLR2, the Edge/Level Control Registers
 * for the 8259 PIC.  bit[n] = 1 means irq[n] is Level, otherwise Edge.
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 * ECLR1 is IRQs 0-7 (IRQ 0, 1, 2 must be 0)
 * ECLR2 is IRQs 8-15 (IRQ 8, 13 must be 0)
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 */

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void __init acpi_pic_sci_set_trigger(unsigned int irq, u16 trigger)
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{
	unsigned int mask = 1 << irq;
	unsigned int old, new;

	/* Real old ELCR mask */
	old = inb(0x4d0) | (inb(0x4d1) << 8);

	/*
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	 * If we use ACPI to set PCI IRQs, then we should clear ELCR
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	 * since we will set it correctly as we enable the PCI irq
	 * routing.
	 */
	new = acpi_noirq ? old : 0;

	/*
	 * Update SCI information in the ELCR, it isn't in the PCI
	 * routing tables..
	 */
	switch (trigger) {
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	case 1:		/* Edge - clear */
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		new &= ~mask;
		break;
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	case 3:		/* Level - set */
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		new |= mask;
		break;
	}

	if (old == new)
		return;

	printk(PREFIX "setting ELCR to %04x (from %04x)\n", new, old);
	outb(new, 0x4d0);
	outb(new >> 8, 0x4d1);
}

int acpi_gsi_to_irq(u32 gsi, unsigned int *irq)
{
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	*irq = gsi;
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	return 0;
}

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/*
 * success: return IRQ number (>=0)
 * failure: return < 0
 */
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int acpi_register_gsi(u32 gsi, int triggering, int polarity)
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{
	unsigned int irq;
	unsigned int plat_gsi = gsi;

#ifdef CONFIG_PCI
	/*
	 * Make sure all (legacy) PCI IRQs are set as level-triggered.
	 */
	if (acpi_irq_model == ACPI_IRQ_MODEL_PIC) {
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		if (triggering == ACPI_LEVEL_SENSITIVE)
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			eisa_set_level_irq(gsi);
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	}
#endif

#ifdef CONFIG_X86_IO_APIC
	if (acpi_irq_model == ACPI_IRQ_MODEL_IOAPIC) {
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		plat_gsi = mp_register_gsi(gsi, triggering, polarity);
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	}
#endif
	acpi_gsi_to_irq(plat_gsi, &irq);
	return irq;
}
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/*
 *  ACPI based hotplug support for CPU
 */
#ifdef CONFIG_ACPI_HOTPLUG_CPU
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static int __cpuinit _acpi_map_lsapic(acpi_handle handle, int *pcpu)
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{
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	struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
	union acpi_object *obj;
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	struct acpi_madt_local_apic *lapic;
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	cpumask_t tmp_map, new_map;
	u8 physid;
	int cpu;

	if (ACPI_FAILURE(acpi_evaluate_object(handle, "_MAT", NULL, &buffer)))
		return -EINVAL;

	if (!buffer.length || !buffer.pointer)
		return -EINVAL;

	obj = buffer.pointer;
	if (obj->type != ACPI_TYPE_BUFFER ||
	    obj->buffer.length < sizeof(*lapic)) {
		kfree(buffer.pointer);
		return -EINVAL;
	}

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	lapic = (struct acpi_madt_local_apic *)obj->buffer.pointer;
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	if (lapic->header.type != ACPI_MADT_TYPE_LOCAL_APIC ||
	    !(lapic->lapic_flags & ACPI_MADT_ENABLED)) {
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		kfree(buffer.pointer);
		return -EINVAL;
	}

	physid = lapic->id;

	kfree(buffer.pointer);
	buffer.length = ACPI_ALLOCATE_BUFFER;
	buffer.pointer = NULL;

	tmp_map = cpu_present_map;
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	acpi_register_lapic(physid, lapic->lapic_flags & ACPI_MADT_ENABLED);
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	/*
	 * If mp_register_lapic successfully generates a new logical cpu
	 * number, then the following will get us exactly what was mapped
	 */
	cpus_andnot(new_map, cpu_present_map, tmp_map);
	if (cpus_empty(new_map)) {
		printk ("Unable to map lapic to logical cpu number\n");
		return -EINVAL;
	}

	cpu = first_cpu(new_map);

	*pcpu = cpu;
	return 0;
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}

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/* wrapper to silence section mismatch warning */
int __ref acpi_map_lsapic(acpi_handle handle, int *pcpu)
{
	return _acpi_map_lsapic(handle, pcpu);
}
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EXPORT_SYMBOL(acpi_map_lsapic);
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int acpi_unmap_lsapic(int cpu)
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{
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	per_cpu(x86_cpu_to_apicid, cpu) = -1;
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	cpu_clear(cpu, cpu_present_map);
	num_processors--;

	return (0);
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}
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EXPORT_SYMBOL(acpi_unmap_lsapic);
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#endif				/* CONFIG_ACPI_HOTPLUG_CPU */
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int acpi_register_ioapic(acpi_handle handle, u64 phys_addr, u32 gsi_base)
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{
	/* TBD */
	return -EINVAL;
}
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EXPORT_SYMBOL(acpi_register_ioapic);

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int acpi_unregister_ioapic(acpi_handle handle, u32 gsi_base)
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{
	/* TBD */
	return -EINVAL;
}
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EXPORT_SYMBOL(acpi_unregister_ioapic);

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static int __init acpi_parse_sbf(struct acpi_table_header *table)
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{
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	struct acpi_table_boot *sb;
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	sb = (struct acpi_table_boot *)table;
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	if (!sb) {
		printk(KERN_WARNING PREFIX "Unable to map SBF\n");
		return -ENODEV;
	}

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	sbf_port = sb->cmos_index;	/* Save CMOS port */
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	return 0;
}

#ifdef CONFIG_HPET_TIMER
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#include <asm/hpet.h>
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static struct __initdata resource *hpet_res;

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static int __init acpi_parse_hpet(struct acpi_table_header *table)
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{
	struct acpi_table_hpet *hpet_tbl;

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	hpet_tbl = (struct acpi_table_hpet *)table;
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	if (!hpet_tbl) {
		printk(KERN_WARNING PREFIX "Unable to map HPET\n");
		return -ENODEV;
	}

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	if (hpet_tbl->address.space_id != ACPI_SPACE_MEM) {
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		printk(KERN_WARNING PREFIX "HPET timers must be located in "
		       "memory.\n");
		return -1;
	}
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	hpet_address = hpet_tbl->address.address;
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	/*
	 * Some broken BIOSes advertise HPET at 0x0. We really do not
	 * want to allocate a resource there.
	 */
	if (!hpet_address) {
		printk(KERN_WARNING PREFIX
		       "HPET id: %#x base: %#lx is invalid\n",
		       hpet_tbl->id, hpet_address);
		return 0;
	}
#ifdef CONFIG_X86_64
	/*
	 * Some even more broken BIOSes advertise HPET at
	 * 0xfed0000000000000 instead of 0xfed00000. Fix it up and add
	 * some noise:
	 */
	if (hpet_address == 0xfed0000000000000UL) {
		if (!hpet_force_user) {
			printk(KERN_WARNING PREFIX "HPET id: %#x "
			       "base: 0xfed0000000000000 is bogus\n "
			       "try hpet=force on the kernel command line to "
			       "fix it up to 0xfed00000.\n", hpet_tbl->id);
			hpet_address = 0;
			return 0;
		}
		printk(KERN_WARNING PREFIX
		       "HPET id: %#x base: 0xfed0000000000000 fixed up "
		       "to 0xfed00000.\n", hpet_tbl->id);
		hpet_address >>= 32;
	}
#endif
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	printk(KERN_INFO PREFIX "HPET id: %#x base: %#lx\n",
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	       hpet_tbl->id, hpet_address);
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	/*
	 * Allocate and initialize the HPET firmware resource for adding into
	 * the resource tree during the lateinit timeframe.
	 */
#define HPET_RESOURCE_NAME_SIZE 9
	hpet_res = alloc_bootmem(sizeof(*hpet_res) + HPET_RESOURCE_NAME_SIZE);

	hpet_res->name = (void *)&hpet_res[1];
	hpet_res->flags = IORESOURCE_MEM;
	snprintf((char *)hpet_res->name, HPET_RESOURCE_NAME_SIZE, "HPET %u",
		 hpet_tbl->sequence);

	hpet_res->start = hpet_address;
	hpet_res->end = hpet_address + (1 * 1024) - 1;

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	return 0;
}
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/*
 * hpet_insert_resource inserts the HPET resources used into the resource
 * tree.
 */
static __init int hpet_insert_resource(void)
{
	if (!hpet_res)
		return 1;

	return insert_resource(&iomem_resource, hpet_res);
}

late_initcall(hpet_insert_resource);

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#else
#define	acpi_parse_hpet	NULL
#endif

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static int __init acpi_parse_fadt(struct acpi_table_header *table)
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{
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#ifdef CONFIG_X86_PM_TIMER
	/* detect the location of the ACPI PM Timer */
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	if (acpi_gbl_FADT.header.revision >= FADT2_REVISION_ID) {
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		/* FADT rev. 2 */
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		if (acpi_gbl_FADT.xpm_timer_block.space_id !=
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		    ACPI_ADR_SPACE_SYSTEM_IO)
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			return 0;

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		pmtmr_ioport = acpi_gbl_FADT.xpm_timer_block.address;
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		/*
		 * "X" fields are optional extensions to the original V1.0
		 * fields, so we must selectively expand V1.0 fields if the
		 * corresponding X field is zero.
	 	 */
		if (!pmtmr_ioport)
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			pmtmr_ioport = acpi_gbl_FADT.pm_timer_block;
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	} else {
		/* FADT rev. 1 */
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		pmtmr_ioport = acpi_gbl_FADT.pm_timer_block;
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	}
	if (pmtmr_ioport)
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		printk(KERN_INFO PREFIX "PM-Timer IO Port: %#x\n",
		       pmtmr_ioport);
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#endif
	return 0;
}

#ifdef	CONFIG_X86_LOCAL_APIC
/*
 * Parse LAPIC entries in MADT
 * returns 0 on success, < 0 on error
 */
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static void __init acpi_register_lapic_address(unsigned long address)
{
	mp_lapic_addr = address;

	set_fixmap_nocache(FIX_APIC_BASE, address);
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	if (boot_cpu_physical_apicid == -1U) {
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		boot_cpu_physical_apicid  = read_apic_id();
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		apic_version[boot_cpu_physical_apicid] =
			 GET_APIC_VERSION(apic_read(APIC_LVR));
	}
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}

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static int __init early_acpi_parse_madt_lapic_addr_ovr(void)
{
	int count;

	if (!cpu_has_apic)
		return -ENODEV;

	/*
	 * Note that the LAPIC address is obtained from the MADT (32-bit value)
	 * and (optionally) overriden by a LAPIC_ADDR_OVR entry (64-bit value).
	 */

	count =
	    acpi_table_parse_madt(ACPI_MADT_TYPE_LOCAL_APIC_OVERRIDE,
				  acpi_parse_lapic_addr_ovr, 0);
	if (count < 0) {
		printk(KERN_ERR PREFIX
		       "Error parsing LAPIC address override entry\n");
		return count;
	}

	acpi_register_lapic_address(acpi_lapic_addr);

	return count;
}

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static int __init acpi_parse_madt_lapic_entries(void)
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{
	int count;

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	if (!cpu_has_apic)
		return -ENODEV;

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	/*
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	 * Note that the LAPIC address is obtained from the MADT (32-bit value)
	 * and (optionally) overriden by a LAPIC_ADDR_OVR entry (64-bit value).
	 */

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	count =
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	    acpi_table_parse_madt(ACPI_MADT_TYPE_LOCAL_APIC_OVERRIDE,
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				  acpi_parse_lapic_addr_ovr, 0);
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	if (count < 0) {
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		printk(KERN_ERR PREFIX
		       "Error parsing LAPIC address override entry\n");
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		return count;
	}

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	acpi_register_lapic_address(acpi_lapic_addr);
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	count = acpi_table_parse_madt(ACPI_MADT_TYPE_LOCAL_SAPIC,
				      acpi_parse_sapic, MAX_APICS);

	if (!count)
		count = acpi_table_parse_madt(ACPI_MADT_TYPE_LOCAL_APIC,
					      acpi_parse_lapic, MAX_APICS);
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	if (!count) {
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		printk(KERN_ERR PREFIX "No LAPIC entries present\n");
		/* TBD: Cleanup to allow fallback to MPS */
		return -ENODEV;
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	} else if (count < 0) {
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		printk(KERN_ERR PREFIX "Error parsing LAPIC entry\n");
		/* TBD: Cleanup to allow fallback to MPS */
		return count;
	}

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	count =
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	    acpi_table_parse_madt(ACPI_MADT_TYPE_LOCAL_APIC_NMI, acpi_parse_lapic_nmi, 0);
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	if (count < 0) {
		printk(KERN_ERR PREFIX "Error parsing LAPIC NMI entry\n");
		/* TBD: Cleanup to allow fallback to MPS */
		return count;
	}
	return 0;
}
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#endif				/* CONFIG_X86_LOCAL_APIC */
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#ifdef	CONFIG_X86_IO_APIC
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#define MP_ISA_BUS		0

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#ifdef CONFIG_X86_ES7000
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extern int es7000_plat;
#endif

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static struct {
	int apic_id;
	int gsi_base;
	int gsi_end;
	DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
} mp_ioapic_routing[MAX_IO_APICS];
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static int mp_find_ioapic(int gsi)
{
	int i = 0;

	/* Find the IOAPIC that manages this GSI. */
	for (i = 0; i < nr_ioapics; i++) {
		if ((gsi >= mp_ioapic_routing[i].gsi_base)
		    && (gsi <= mp_ioapic_routing[i].gsi_end))
			return i;
	}

	printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
	return -1;
}

static u8 __init uniq_ioapic_id(u8 id)
{
#ifdef CONFIG_X86_32
	if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
	    !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
		return io_apic_get_unique_id(nr_ioapics, id);
	else
		return id;
#else
	int i;
	DECLARE_BITMAP(used, 256);
	bitmap_zero(used, 256);
	for (i = 0; i < nr_ioapics; i++) {
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		struct mp_config_ioapic *ia = &mp_ioapics[i];
		__set_bit(ia->mp_apicid, used);
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	}
	if (!test_bit(id, used))
		return id;
	return find_first_zero_bit(used, 256);
#endif
}

static int bad_ioapic(unsigned long address)
{
	if (nr_ioapics >= MAX_IO_APICS) {
		printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
		       "(found %d)\n", MAX_IO_APICS, nr_ioapics);
		panic("Recompile kernel with bigger MAX_IO_APICS!\n");
	}
	if (!address) {
		printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
		       " found in table, skipping!\n");
		return 1;
	}
	return 0;
}

void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
{
	int idx = 0;

	if (bad_ioapic(address))
		return;

	idx = nr_ioapics;

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	mp_ioapics[idx].mp_type = MP_IOAPIC;
	mp_ioapics[idx].mp_flags = MPC_APIC_USABLE;
	mp_ioapics[idx].mp_apicaddr = address;
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	set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
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	mp_ioapics[idx].mp_apicid = uniq_ioapic_id(id);
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#ifdef CONFIG_X86_32
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	mp_ioapics[idx].mp_apicver = io_apic_get_version(idx);
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#else
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	mp_ioapics[idx].mp_apicver = 0;
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#endif
	/*
	 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
	 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
	 */
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	mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mp_apicid;
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	mp_ioapic_routing[idx].gsi_base = gsi_base;
	mp_ioapic_routing[idx].gsi_end = gsi_base +
	    io_apic_get_redir_entries(idx);

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	printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%lx, "
	       "GSI %d-%d\n", idx, mp_ioapics[idx].mp_apicid,
	       mp_ioapics[idx].mp_apicver, mp_ioapics[idx].mp_apicaddr,
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	       mp_ioapic_routing[idx].gsi_base, mp_ioapic_routing[idx].gsi_end);

	nr_ioapics++;
}

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static void assign_to_mp_irq(struct mp_config_intsrc *m,
				    struct mp_config_intsrc *mp_irq)
{
	memcpy(mp_irq, m, sizeof(struct mp_config_intsrc));
}

static int mp_irq_cmp(struct mp_config_intsrc *mp_irq,
				struct mp_config_intsrc *m)
{
	return memcmp(mp_irq, m, sizeof(struct mp_config_intsrc));
}

static void save_mp_irq(struct mp_config_intsrc *m)
{
	int i;

	for (i = 0; i < mp_irq_entries; i++) {
		if (!mp_irq_cmp(&mp_irqs[i], m))
			return;
	}

	assign_to_mp_irq(m, &mp_irqs[mp_irq_entries]);
	if (++mp_irq_entries == MAX_IRQ_SOURCES)
		panic("Max # of irq sources exceeded!!\n");
}

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void __init mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi)
{
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	int ioapic;
	int pin;
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	struct mp_config_intsrc mp_irq;
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	/*
	 * Convert 'gsi' to 'ioapic.pin'.
	 */
	ioapic = mp_find_ioapic(gsi);
	if (ioapic < 0)
		return;
	pin = gsi - mp_ioapic_routing[ioapic].gsi_base;

	/*
	 * TBD: This check is for faulty timer entries, where the override
	 *      erroneously sets the trigger to level, resulting in a HUGE
	 *      increase of timer interrupts!
	 */
	if ((bus_irq == 0) && (trigger == 3))
		trigger = 1;

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	mp_irq.mp_type = MP_INTSRC;
	mp_irq.mp_irqtype = mp_INT;
	mp_irq.mp_irqflag = (trigger << 2) | polarity;
	mp_irq.mp_srcbus = MP_ISA_BUS;
	mp_irq.mp_srcbusirq = bus_irq;	/* IRQ */
	mp_irq.mp_dstapic = mp_ioapics[ioapic].mp_apicid; /* APIC ID */
	mp_irq.mp_dstirq = pin;	/* INTIN# */
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	save_mp_irq(&mp_irq);
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}

void __init mp_config_acpi_legacy_irqs(void)
{
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	int i;
	int ioapic;
	unsigned int dstapic;
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	struct mp_config_intsrc mp_irq;
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#if defined (CONFIG_MCA) || defined (CONFIG_EISA)
	/*
	 * Fabricate the legacy ISA bus (bus #31).
	 */
	mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
#endif
	set_bit(MP_ISA_BUS, mp_bus_not_pci);
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	pr_debug("Bus #%d is ISA\n", MP_ISA_BUS);
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#ifdef CONFIG_X86_ES7000
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	/*
	 * Older generations of ES7000 have no legacy identity mappings
	 */
	if (es7000_plat == 1)
		return;
#endif

	/*
	 * Locate the IOAPIC that manages the ISA IRQs (0-15).
	 */
	ioapic = mp_find_ioapic(0);
	if (ioapic < 0)
		return;
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	dstapic = mp_ioapics[ioapic].mp_apicid;
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	/*
	 * Use the default configuration for the IRQs 0-15.  Unless
	 * overridden by (MADT) interrupt source override entries.
	 */
	for (i = 0; i < 16; i++) {
		int idx;

		for (idx = 0; idx < mp_irq_entries; idx++) {
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			struct mp_config_intsrc *irq = mp_irqs + idx;
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			/* Do we already have a mapping for this ISA IRQ? */
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			if (irq->mp_srcbus == MP_ISA_BUS
			    && irq->mp_srcbusirq == i)
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				break;

			/* Do we already have a mapping for this IOAPIC pin */
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			if (irq->mp_dstapic == dstapic &&
			    irq->mp_dstirq == i)
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				break;
		}

		if (idx != mp_irq_entries) {
			printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
			continue;	/* IRQ already used */
		}

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		mp_irq.mp_type = MP_INTSRC;
		mp_irq.mp_irqflag = 0;	/* Conforming */
		mp_irq.mp_srcbus = MP_ISA_BUS;
		mp_irq.mp_dstapic = dstapic;
		mp_irq.mp_irqtype = mp_INT;
		mp_irq.mp_srcbusirq = i; /* Identity mapped */
		mp_irq.mp_dstirq = i;
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		save_mp_irq(&mp_irq);
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	}
}

int mp_register_gsi(u32 gsi, int triggering, int polarity)
{
	int ioapic;
	int ioapic_pin;
#ifdef CONFIG_X86_32
#define MAX_GSI_NUM	4096
#define IRQ_COMPRESSION_START	64

	static int pci_irq = IRQ_COMPRESSION_START;
	/*
	 * Mapping between Global System Interrupts, which
	 * represent all possible interrupts, and IRQs
	 * assigned to actual devices.
	 */
	static int gsi_to_irq[MAX_GSI_NUM];
#else

	if (acpi_irq_model != ACPI_IRQ_MODEL_IOAPIC)
		return gsi;
#endif

	/* Don't set up the ACPI SCI because it's already set up */
	if (acpi_gbl_FADT.sci_interrupt == gsi)
		return gsi;

	ioapic = mp_find_ioapic(gsi);
	if (ioapic < 0) {
		printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
		return gsi;
	}

	ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base;

#ifdef CONFIG_X86_32
	if (ioapic_renumber_irq)
		gsi = ioapic_renumber_irq(ioapic, gsi);
#endif

	/*
	 * Avoid pin reprogramming.  PRTs typically include entries
	 * with redundant pin->gsi mappings (but unique PCI devices);
	 * we only program the IOAPIC on the first.
	 */
	if (ioapic_pin > MP_MAX_IOAPIC_PIN) {
		printk(KERN_ERR "Invalid reference to IOAPIC pin "
		       "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
		       ioapic_pin);
		return gsi;
	}
	if (test_bit(ioapic_pin, mp_ioapic_routing[ioapic].pin_programmed)) {
1140
		pr_debug("Pin %d-%d already programmed\n",
1141
			 mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
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