Commit fbe931e2 authored by Connor Abbott's avatar Connor Abbott

bifrost: Opcode maintainance

parent 008ab277
......@@ -416,6 +416,7 @@ static const FMAOpInfo FMAOpInfos[] = {
{ 0xc8000, "FCMP.GL", FMAFcmp16 },
{ 0xcc000, "FCMP.D3D", FMAFcmp16 },
{ 0xcf900, "ADD.v2i16", FMATwoSrc },
{ 0xcfb00, "SUB.v2i16", FMATwoSrc },
{ 0xcfc10, "ADDC.i32", FMATwoSrc },
{ 0xcfd80, "ADD.i32.i16.X", FMATwoSrc },
{ 0xcfd90, "ADD.i32.u16.X", FMATwoSrc },
......@@ -1027,37 +1028,47 @@ static const ADDOpInfo ADDOpInfos[] = {
{ 0x08500, "LD_ATTR.v3f32", ADDLoadAttr, true },
{ 0x08600, "LD_ATTR.v3f32", ADDLoadAttr, true },
{ 0x08700, "LD_ATTR.v4f32", ADDLoadAttr, true },
{ 0x087c0, "LD_ATTR_TEX.v4f32", ADDThreeSrc, true },
{ 0x08800, "LD_ATTR.i32", ADDLoadAttr, true },
{ 0x08900, "LD_ATTR.v3i32", ADDLoadAttr, true },
{ 0x08a00, "LD_ATTR.v3i32", ADDLoadAttr, true },
{ 0x08b00, "LD_ATTR.v4i32", ADDLoadAttr, true },
{ 0x08bc0, "LD_ATTR_TEX.v4i32", ADDThreeSrc, true },
{ 0x08c00, "LD_ATTR.u32", ADDLoadAttr, true },
{ 0x08d00, "LD_ATTR.v3u32", ADDLoadAttr, true },
{ 0x08e00, "LD_ATTR.v3u32", ADDLoadAttr, true },
{ 0x08f00, "LD_ATTR.v4u32", ADDLoadAttr, true },
{ 0x08fc0, "LD_ATTR_TEX.v4u32", ADDThreeSrc, true },
{ 0x0a000, "LD_VAR.32", ADDVaryingInterp, true },
{ 0x0b000, "TEX", ADDTexCompact, true },
{ 0x0c188, "LOAD.i32", ADDTwoSrc, true },
{ 0x0c190, "LD_SHARED.i32", ADDTwoSrc, true },
{ 0x0c1a0, "LD_UBO.i32", ADDTwoSrc, true },
{ 0x0c1b8, "LD_SCRATCH.v2i32", ADDTwoSrc, true },
{ 0x0c1b8, "LD_SCRATCH.i32", ADDTwoSrc, true },
{ 0x0c1c8, "LOAD.v2i32", ADDTwoSrc, true },
{ 0x0c1d0, "LD_SHARED.v2i32", ADDTwoSrc, true },
{ 0x0c1e0, "LD_UBO.v2i32", ADDTwoSrc, true },
{ 0x0c1f8, "LD_SCRATCH.v2i32", ADDTwoSrc, true },
{ 0x0c208, "LOAD.v4i32", ADDTwoSrc, true },
{ 0x0c210, "LD_SHARED.v4i32", ADDTwoSrc, true },
// src0 = offset, src1 = binding
{ 0x0c220, "LD_UBO.v4i32", ADDTwoSrc, true },
{ 0x0c238, "LD_SCRATCH.v4i32", ADDTwoSrc, true },
{ 0x0c248, "STORE.v4i32", ADDTwoSrc, true },
{ 0x0c250, "ST_SHARED.v4i32", ADDTwoSrc, true },
{ 0x0c278, "ST_SCRATCH.v4i32", ADDTwoSrc, true },
{ 0x0c588, "STORE.i32", ADDTwoSrc, true },
{ 0x0c590, "ST_SHARED.i32", ADDTwoSrc, true },
{ 0x0c5b8, "ST_SCRATCH.i32", ADDTwoSrc, true },
{ 0x0c5c8, "STORE.v2i32", ADDTwoSrc, true },
{ 0x0c5d0, "ST_SHARED.v2i32", ADDTwoSrc, true },
{ 0x0c5f8, "ST_SCRATCH.v2i32", ADDTwoSrc, true },
{ 0x0c648, "LOAD.u16", ADDTwoSrc, true }, // zero-extends
{ 0x0ca88, "LOAD.v3i32", ADDTwoSrc, true },
{ 0x0caa0, "LD_UBO.v3i32", ADDTwoSrc, true },
{ 0x0cab8, "LD_SCRATCH.v3i32", ADDTwoSrc, true },
{ 0x0cb88, "STORE.v3i32", ADDTwoSrc, true },
{ 0x0cb90, "ST_SHARED.v3i32", ADDTwoSrc, true },
{ 0x0cbb8, "ST_SCRATCH.v3i32", ADDTwoSrc, true },
// *_FAST does not exist on G71 (added to G51, G72, and everything after)
{ 0x0cc00, "FRCP_FAST.f32", ADDOneSrc },
......@@ -1147,8 +1158,11 @@ static const ADDOpInfo ADDOpInfos[] = {
// This takes the sample coverage mask (computed by ATEST above) as a
// regular argument, in addition to the vec4 color in the special register.
{ 0x1952c, "BLEND", ADDBlending, true },
{ 0x196c0, "LD_TILE", ADDThreeSrc, true },
{ 0x197c0, "ST_TILE", ADDThreeSrc, true },
{ 0x1a000, "LD_VAR.16", ADDVaryingInterp, true },
{ 0x1ae60, "TEX", ADDTex, true },
{ 0x1af0e, "BARRIER", ADDOneSrc, false },
{ 0x1c000, "RSHIFT_NAND.i32", ADDThreeSrc },
{ 0x1c300, "RSHIFT_OR.i32", ADDThreeSrc },
{ 0x1c400, "RSHIFT_AND.i32", ADDThreeSrc },
......@@ -1172,8 +1186,8 @@ static const ADDOpInfo ADDOpInfos[] = {
{ 0x1dc00, "ARSHIFT_RSUB.i32", ADDThreeSrc },
{ 0x1dd18, "OR.i32", ADDTwoSrc },
{ 0x1dd20, "AND.i32", ADDTwoSrc },
{ 0x1dd60, "LSHIFT.i32", ADDTwoSrc },
{ 0x1dd50, "XOR.i32", ADDTwoSrc },
{ 0x1dd60, "LSHIFT.i32", ADDTwoSrc },
{ 0x1dd80, "RSHIFT.i32", ADDTwoSrc },
{ 0x1dda0, "ARSHIFT.i32", ADDTwoSrc },
};
......
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