Commit 6fd32829 authored by Connor Abbott's avatar Connor Abbott

bifrost: Add opcodes for atan(), asin(), acos()

parent d369a48c
......@@ -495,6 +495,8 @@ static const FMAOpInfo FMAOpInfos[] = {
{ 0xe0f40, "CSEL", FMAThreeSrc }, // src2 != 0 ? src1 : src0
{ 0xe1845, "CEIL", FMAOneSrc },
{ 0xe1885, "FLOOR", FMAOneSrc },
{ 0xe19b0, "ATAN_LDEXP.Y.f32", FMATwoSrc },
{ 0xe19b8, "ATAN_LDEXP.X.f32", FMATwoSrc },
// This acts like a normal 32-bit add, except that it sets a flag on
// overflow that gets listened to by load/store instructions in the ADD
// part of the instruction, and added appropriately to the upper 32 bits of
......@@ -1000,12 +1002,19 @@ static const ADDOpInfo ADDOpInfos[] = {
// infinity, and NaN all return 1.0.
// See the ARM patent for more information.
{ 0x0ce60, "FRCP_APPROX", ADDOneSrc },
{ 0x0cf40, "ATAN_ASSIST", ADDTwoSrc },
{ 0x0cf48, "ATAN_TABLE", ADDTwoSrc },
{ 0x0cf50, "SIN_TABLE", ADDOneSrc },
{ 0x0cf51, "COS_TABLE", ADDOneSrc },
{ 0x0cf58, "EXP_TABLE", ADDOneSrc },
{ 0x0cf60, "FLOG2_TABLE", ADDOneSrc },
{ 0x0cf64, "FLOGE_TABLE", ADDOneSrc },
{ 0x0d000, "BRANCH", ADDBranch },
// For each bit i, return src2[i] ? src0[i] : src1[i]. In other words, this
// is the same as (src2 & src0) | (~src2 & src1).
{ 0x0e8c0, "MUX", ADDThreeSrc },
{ 0x0e9b0, "ATAN_LDEXP.Y.f32", ADDTwoSrc },
{ 0x0e9b8, "ATAN_LDEXP.X.f32", ADDTwoSrc },
{ 0x0ea60, "SEL.XX.i16", ADDTwoSrc },
{ 0x0ea70, "SEL.XY.i16", ADDTwoSrc },
{ 0x0ea68, "SEL.YX.i16", ADDTwoSrc },
......
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