Commit 5a6b8ab9 authored by Connor Abbott's avatar Connor Abbott

bifrost: Add basic vertex shader opcodes

Now we can completely disassemble basic vertex shaders.
parent 57560fd6
......@@ -736,6 +736,8 @@ enum ADDSrcType {
ADDTex, // texture instruction with sampler/etc. in uniform port
ADDVaryingInterp,
ADDBlending,
ADDLoadAttr,
ADDVaryingAddress,
};
struct ADDOpInfo {
......@@ -785,6 +787,22 @@ static const ADDOpInfo ADDOpInfos[] = {
{ 0x07d45, "CEIL", ADDOneSrc },
{ 0x07d85, "FLOOR", ADDOneSrc },
{ 0x07f18, "ADD_HIGH32", ADDTwoSrc },
{ 0x08000, "LD_ATTR.f16", ADDLoadAttr, true },
{ 0x08100, "LD_ATTR.v2f16", ADDLoadAttr, true },
{ 0x08200, "LD_ATTR.v3f16", ADDLoadAttr, true },
{ 0x08300, "LD_ATTR.v4f16", ADDLoadAttr, true },
{ 0x08400, "LD_ATTR.f32", ADDLoadAttr, true },
{ 0x08500, "LD_ATTR.v3f32", ADDLoadAttr, true },
{ 0x08600, "LD_ATTR.v3f32", ADDLoadAttr, true },
{ 0x08700, "LD_ATTR.v4f32", ADDLoadAttr, true },
{ 0x08800, "LD_ATTR.i32", ADDLoadAttr, true },
{ 0x08900, "LD_ATTR.v3i32", ADDLoadAttr, true },
{ 0x08a00, "LD_ATTR.v3i32", ADDLoadAttr, true },
{ 0x08b00, "LD_ATTR.v4i32", ADDLoadAttr, true },
{ 0x08c00, "LD_ATTR.u32", ADDLoadAttr, true },
{ 0x08d00, "LD_ATTR.v3u32", ADDLoadAttr, true },
{ 0x08e00, "LD_ATTR.v3u32", ADDLoadAttr, true },
{ 0x08f00, "LD_ATTR.v4u32", ADDLoadAttr, true },
{ 0x0a000, "LD_VAR.32", ADDVaryingInterp, true },
{ 0x0b000, "TEX", ADDTexCompact, true },
{ 0x0c188, "LOAD.i32", ADDTwoSrc, true },
......@@ -796,6 +814,8 @@ static const ADDOpInfo ADDOpInfos[] = {
{ 0x0c648, "LOAD.u16", ADDTwoSrc, true }, // zero-extends
{ 0x0ca88, "LOAD.v3i32", ADDTwoSrc, true },
{ 0x0cb88, "STORE.v3i32", ADDTwoSrc, true },
// Does not exist on G71 (added to G51, G72, and everything after)
{ 0x0cc00, "FRCP_FAST.f32", ADDOneSrc },
// Produce appropriate scale
{ 0x0ce00, "FRCP_SCALE", ADDOneSrc },
// Used in the argument reduction for log.
......@@ -804,12 +824,12 @@ static const ADDOpInfo ADDOpInfos[] = {
{ 0x0cf50, "SIN_TABLE", ADDOneSrc },
{ 0x0cf51, "COS_TABLE", ADDOneSrc },
{ 0x0cf60, "FLOG2_TABLE", ADDOneSrc },
{ 0x0cf64, "FLOGE_TABLE", ADDOneSrc },
{ 0x0ea60, "SEL.XX.i16", ADDTwoSrc },
{ 0x0ea70, "SEL.XY.i16", ADDTwoSrc },
{ 0x0ea68, "SEL.YX.i16", ADDTwoSrc },
{ 0x0ea78, "SEL.YY.i16", ADDTwoSrc },
{ 0x0ec00, "F32_TO_F16", ADDTwoSrc },
{ 0x0cf64, "FLOGE_TABLE", ADDOneSrc },
{ 0x0f640, "ICMP.GL.GT", ADDTwoSrc }, // src0 > src1 ? 1 : 0
{ 0x0f648, "ICMP.GL.GE", ADDTwoSrc },
{ 0x0f650, "UCMP.GL.GT", ADDTwoSrc },
......@@ -828,6 +848,10 @@ static const ADDOpInfo ADDOpInfos[] = {
{ 0x17900, "ADD.v2i16", ADDTwoSrc },
{ 0x17ac0, "SUB.i32", ADDTwoSrc },
{ 0x17c10, "ADDC.i32", ADDTwoSrc }, // adds src0 to the bottom bit of src1
// Compute varying address and datatype (for storing in the vertex shader),
// and store the vec3 result in the data register. The result is passed as
// the 3 normal arguments to ST_VAR.
{ 0x18100, "LD_VAR_ADDR", ADDVaryingAddress, true },
// Implements alpha-to-coverage, as well as possibly the late depth and
// stencil tests. The first source is the existing sample mask in R60
// (possibly modified by gl_SampleMask), and the second source is the alpha
......@@ -839,6 +863,11 @@ static const ADDOpInfo ADDOpInfos[] = {
{ 0x191e8, "ATEST.f32", ADDTwoSrc, true },
{ 0x191f0, "ATEST.X.f16", ADDTwoSrc, true },
{ 0x191f8, "ATEST.Y.f16", ADDTwoSrc, true },
// store a varying given the descriptor
{ 0x19300, "ST_VAR.f32", ADDThreeSrc, true },
{ 0x19340, "ST_VAR.v2f32", ADDThreeSrc, true },
{ 0x19380, "ST_VAR.v3f32", ADDThreeSrc, true },
{ 0x193c0, "ST_VAR.v4f32", ADDThreeSrc, true },
// This takes the sample coverage mask (computed by ATEST above) as a
// regular argument, in addition to the vec4 color in the special register.
{ 0x1952c, "BLEND", ADDBlending, true },
......@@ -908,6 +937,12 @@ static ADDOpInfo findADDOpInfo(unsigned op)
case ADDVaryingInterp:
opCmp = op & ~0x7ff;
break;
case ADDVaryingAddress:
opCmp = op & ~0xff;
break;
case ADDLoadAttr:
opCmp = op & ~0x7f;
break;
}
if (ADDOpInfos[i].op == opCmp)
return ADDOpInfos[i];
......@@ -1131,6 +1166,25 @@ static void DumpADD(uint64_t word, Regs regs, Regs nextRegs, uint64_t *consts, u
DumpSrc(ADD.src0, regs, consts, false);
break;
}
case ADDVaryingAddress: {
DumpSrc(ADD.src0, regs, consts, false);
printf(", ");
DumpSrc(ADD.op & 0x7, regs, consts, false);
printf(", ");
unsigned location = (ADD.op >> 3) & 0x1f;
if (location < 16) {
printf("location:%d", location);
} else if (location == 20) {
printf("location:%u", (uint32_t) GetConst(consts, regs));
} else if (location == 21) {
printf("location:%u", (uint32_t) (GetConst(consts, regs) >> 32));
} else {
printf("location:%d(unk)", location);
}
break;
}
case ADDLoadAttr:
printf("location:%d, ", (ADD.op >> 3) & 0xf);
case ADDTwoSrc:
DumpSrc(ADD.src0, regs, consts, false);
printf(", ");
......
......@@ -319,7 +319,7 @@ bool ParseSingleBlock(unsigned indent, uint8_t* blockBlob, uint32_t cookie, uint
// XXX: Sometimes different
// Probably a bitfield
assert(block->unk2 == 0x0);
//assert(block->unk2 == 0x0);
}
break;
case COOKIE("SPDv"):
......@@ -361,6 +361,7 @@ bool ParseSingleBlock(unsigned indent, uint8_t* blockBlob, uint32_t cookie, uint
break;
case 11: // G71
case 12: // G51
case 13: // G72
DisassembleBifrost(blockBlob, size);
break;
}
......
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